* [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5
@ 2021-02-21 15:10 Takuto Naito
2021-02-21 15:10 ` [PATCH v2 1/2] TigerlakeOpenBoardPkg: " Takuto Naito
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Takuto Naito @ 2021-02-21 15:10 UTC (permalink / raw)
To: devel; +Cc: Sai Chaganty, Nate DeSimone, Heng Luo
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224
TigerlakeOpenBoard: Fix build errors with GCC5
v2:
- Split the v1 patch into 2 patches.
One is for Platform/Intel/TigerlakeOpenBoardPkg,
another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg.
https://github.com/naitaku/edk2-platforms/tree/tigerlake_fix_build_error_v2
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Heng Luo <heng.luo@intel.com>
Takuto Naito (2):
TigerlakeOpenBoardPkg: Fix build errors with GCC5
TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5
.../PeiFspPolicyInitLib.inf | 2 +-
.../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------
.../DxeSiliconPolicyUpdateLate.c | 2 +-
.../DxePchPcieRpPolicyLib.c | 2 +-
4 files changed, 3 insertions(+), 191 deletions(-)
--
2.30.1
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v2 1/2] TigerlakeOpenBoardPkg: Fix build errors with GCC5 2021-02-21 15:10 [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 Takuto Naito @ 2021-02-21 15:10 ` Takuto Naito 2021-02-22 1:06 ` Heng Luo 2021-02-21 15:10 ` [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: " Takuto Naito ` (3 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Takuto Naito @ 2021-02-21 15:10 UTC (permalink / raw) To: devel; +Cc: Sai Chaganty, Nate DeSimone, Heng Luo REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 - Fix the path of TigerLakeFspBinPkg - Fix misuse of RETURN_ERROR - Remove unused function CheckNationalSio. Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Heng Luo <heng.luo@intel.com> Signed-off-by: Takuto Naito <naitaku@gmail.com> --- Notes: v2: - Split the v1 patch into 2 patches, One is for Platform/Intel/TigerlakeOpenBoardPkg, another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. .../PeiFspPolicyInitLib.inf | 2 +- .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------ .../DxeSiliconPolicyUpdateLate.c | 2 +- 3 files changed, 2 insertions(+), 190 deletions(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf index 9d85d855f5..708fbac08f 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf @@ -52,7 +52,7 @@ MdeModulePkg/MdeModulePkg.dec IntelFsp2Pkg/IntelFsp2Pkg.dec TigerlakeSiliconPkg/SiPkg.dec - TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec + TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec TigerlakeOpenBoardPkg/OpenBoardPkg.dec UefiCpuPkg/UefiCpuPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c index 6209e50450..cc5337698b 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c @@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbond_x374[] = { {0x30, 0x01} // Enable it with Activation bit }; -/** - Detect if a National 393 SIO is docked. If yes, enable the docked SIO - and its serial port, and disable the onboard serial port. - - @retval EFI_SUCCESS Operations performed successfully. -**/ -STATIC -VOID -CheckNationalSio ( - VOID - ) -{ - UINT8 Data8; - - // - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). - // We use (0x2e, 0x2f) which is determined by BADD default strapping - // - - // - // Read the Pc87393 signature - // - IoWrite8 (0x2e, 0x20); - Data8 = IoRead8 (0x2f); - - if (Data8 == 0xea) { - // - // Signature matches - National PC87393 SIO is docked - // - - // - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at - // SIO_BASE_ADDRESS + 0x10) - // - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20); - - // - // Enable port switch - // - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); - - // - // Turn on docking power - // - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); - - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); - - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); - - // - // Enable port switch - // - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); - - // - // GPIO setting - // - IoWrite8 (0x2e, 0x24); - IoWrite8 (0x2f, 0x29); - - // - // Enable chip clock - // - IoWrite8 (0x2e, 0x29); - IoWrite8 (0x2f, 0x1e); - - - // - // Enable serial port - // - - // - // Select com1 - // - IoWrite8 (0x2e, 0x7); - IoWrite8 (0x2f, 0x3); - - // - // Base address: 0x3f8 - // - IoWrite8 (0x2e, 0x60); - IoWrite8 (0x2f, 0x03); - IoWrite8 (0x2e, 0x61); - IoWrite8 (0x2f, 0xf8); - - // - // Interrupt: 4 - // - IoWrite8 (0x2e, 0x70); - IoWrite8 (0x2f, 0x04); - - // - // Enable bank selection - // - IoWrite8 (0x2e, 0xf0); - IoWrite8 (0x2f, 0x82); - - // - // Activate - // - IoWrite8 (0x2e, 0x30); - IoWrite8 (0x2f, 0x01); - - // - // Disable onboard serial port - // - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); - - // - // Power Down UARTs - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); - - // - // Dissable COM1 decode - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); - - // - // Disable COM2 decode - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); - - // - // Disable interrupt - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); - - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); - - // - // Enable floppy - // - - // - // Select floppy - // - IoWrite8 (0x2e, 0x7); - IoWrite8 (0x2f, 0x0); - - // - // Base address: 0x3f0 - // - IoWrite8 (0x2e, 0x60); - IoWrite8 (0x2f, 0x03); - IoWrite8 (0x2e, 0x61); - IoWrite8 (0x2f, 0xf0); - - // - // Interrupt: 6 - // - IoWrite8 (0x2e, 0x70); - IoWrite8 (0x2f, 0x06); - - // - // DMA 2 - // - IoWrite8 (0x2e, 0x74); - IoWrite8 (0x2f, 0x02); - - // - // Activate - // - IoWrite8 (0x2e, 0x30); - IoWrite8 (0x2f, 0x01); - - } else { - - // - // No National pc87393 SIO is docked, turn off dock power and - // disable port switch - // - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); - // IoWrite8 (0x690, 0); - - // - // If no National pc87393, just return - // - return ; - } -} - /** Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c index 2eee9958be..410a8d1073 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c @@ -88,8 +88,8 @@ SiliconPolicyUpdateLate ( // GOP Dxe Policy Initialization // Status = GopPolicyInitDxe (gImageHandle); - RETURN_ERROR (Status); DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); + ASSERT_EFI_ERROR (Status); } return Policy; -- 2.30.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] TigerlakeOpenBoardPkg: Fix build errors with GCC5 2021-02-21 15:10 ` [PATCH v2 1/2] TigerlakeOpenBoardPkg: " Takuto Naito @ 2021-02-22 1:06 ` Heng Luo 0 siblings, 0 replies; 10+ messages in thread From: Heng Luo @ 2021-02-22 1:06 UTC (permalink / raw) To: Takuto Naito, devel@edk2.groups.io Cc: Chaganty, Rangasai V, Desimone, Nathaniel L Reviewed-by: Heng Luo <heng.luo@intel.com> > -----Original Message----- > From: Takuto Naito <naitaku@gmail.com> > Sent: Sunday, February 21, 2021 11:10 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, > Nathaniel L <nathaniel.l.desimone@intel.com>; Luo, Heng <heng.luo@intel.com> > Subject: [PATCH v2 1/2] TigerlakeOpenBoardPkg: Fix build errors with GCC5 > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 > > - Fix the path of TigerLakeFspBinPkg > - Fix misuse of RETURN_ERROR > - Remove unused function CheckNationalSio. > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Heng Luo <heng.luo@intel.com> > Signed-off-by: Takuto Naito <naitaku@gmail.com> > --- > > Notes: > v2: > - Split the v1 patch into 2 patches, > One is for Platform/Intel/TigerlakeOpenBoardPkg, > another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. > > .../PeiFspPolicyInitLib.inf | 2 +- > .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------ > .../DxeSiliconPolicyUpdateLate.c | 2 +- > 3 files changed, 2 insertions(+), 190 deletions(-) > > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi > b/PeiFspPolicyInitLib.inf > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi > b/PeiFspPolicyInitLib.inf > index 9d85d855f5..708fbac08f 100644 > --- > a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi > b/PeiFspPolicyInitLib.inf > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi > b/PeiFspPolicyInitLib.inf > @@ -52,7 +52,7 @@ > MdeModulePkg/MdeModulePkg.dec > IntelFsp2Pkg/IntelFsp2Pkg.dec > TigerlakeSiliconPkg/SiPkg.dec > - TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec > + TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec > TigerlakeOpenBoardPkg/OpenBoardPkg.dec > UefiCpuPkg/UefiCpuPkg.dec > IntelSiliconPkg/IntelSiliconPkg.dec > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.c > index 6209e50450..cc5337698b 100644 > --- > a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.c > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePl > atformHookLib.c > @@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE > mSioTableWinbond_x374[] = { > {0x30, 0x01} // Enable it with Activation bit > }; > > -/** > - Detect if a National 393 SIO is docked. If yes, enable the docked SIO > - and its serial port, and disable the onboard serial port. > - > - @retval EFI_SUCCESS Operations performed successfully. > -**/ > -STATIC > -VOID > -CheckNationalSio ( > - VOID > - ) > -{ > - UINT8 Data8; > - > - // > - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). > - // We use (0x2e, 0x2f) which is determined by BADD default strapping > - // > - > - // > - // Read the Pc87393 signature > - // > - IoWrite8 (0x2e, 0x20); > - Data8 = IoRead8 (0x2f); > - > - if (Data8 == 0xea) { > - // > - // Signature matches - National PC87393 SIO is docked > - // > - > - // > - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch > - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at > - // SIO_BASE_ADDRESS + 0x10) > - // > - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & > (UINT16)~0x7F), 0x20); > - > - // > - // Enable port switch > - // > - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); > - > - // > - // Turn on docking power > - // > - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); > - > - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); > - > - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); > - > - // > - // Enable port switch > - // > - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); > - > - // > - // GPIO setting > - // > - IoWrite8 (0x2e, 0x24); > - IoWrite8 (0x2f, 0x29); > - > - // > - // Enable chip clock > - // > - IoWrite8 (0x2e, 0x29); > - IoWrite8 (0x2f, 0x1e); > - > - > - // > - // Enable serial port > - // > - > - // > - // Select com1 > - // > - IoWrite8 (0x2e, 0x7); > - IoWrite8 (0x2f, 0x3); > - > - // > - // Base address: 0x3f8 > - // > - IoWrite8 (0x2e, 0x60); > - IoWrite8 (0x2f, 0x03); > - IoWrite8 (0x2e, 0x61); > - IoWrite8 (0x2f, 0xf8); > - > - // > - // Interrupt: 4 > - // > - IoWrite8 (0x2e, 0x70); > - IoWrite8 (0x2f, 0x04); > - > - // > - // Enable bank selection > - // > - IoWrite8 (0x2e, 0xf0); > - IoWrite8 (0x2f, 0x82); > - > - // > - // Activate > - // > - IoWrite8 (0x2e, 0x30); > - IoWrite8 (0x2f, 0x01); > - > - // > - // Disable onboard serial port > - // > - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); > - > - // > - // Power Down UARTs > - // > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); > - > - // > - // Dissable COM1 decode > - // > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); > - > - // > - // Disable COM2 decode > - // > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); > - > - // > - // Disable interrupt > - // > - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); > - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); > - > - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); > - > - // > - // Enable floppy > - // > - > - // > - // Select floppy > - // > - IoWrite8 (0x2e, 0x7); > - IoWrite8 (0x2f, 0x0); > - > - // > - // Base address: 0x3f0 > - // > - IoWrite8 (0x2e, 0x60); > - IoWrite8 (0x2f, 0x03); > - IoWrite8 (0x2e, 0x61); > - IoWrite8 (0x2f, 0xf0); > - > - // > - // Interrupt: 6 > - // > - IoWrite8 (0x2e, 0x70); > - IoWrite8 (0x2f, 0x06); > - > - // > - // DMA 2 > - // > - IoWrite8 (0x2e, 0x74); > - IoWrite8 (0x2f, 0x02); > - > - // > - // Activate > - // > - IoWrite8 (0x2e, 0x30); > - IoWrite8 (0x2f, 0x01); > - > - } else { > - > - // > - // No National pc87393 SIO is docked, turn off dock power and > - // disable port switch > - // > - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); > - // IoWrite8 (0x690, 0); > - > - // > - // If no National pc87393, just return > - // > - return ; > - } > -} > - > /** > Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports > > diff --git > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat > eLib/DxeSiliconPolicyUpdateLate.c > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat > eLib/DxeSiliconPolicyUpdateLate.c > index 2eee9958be..410a8d1073 100644 > --- > a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat > eLib/DxeSiliconPolicyUpdateLate.c > +++ > b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdat > eLib/DxeSiliconPolicyUpdateLate.c > @@ -88,8 +88,8 @@ SiliconPolicyUpdateLate ( > // GOP Dxe Policy Initialization > // > Status = GopPolicyInitDxe (gImageHandle); > - RETURN_ERROR (Status); > DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); > + ASSERT_EFI_ERROR (Status); > } > > return Policy; > -- > 2.30.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 2021-02-21 15:10 [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 Takuto Naito 2021-02-21 15:10 ` [PATCH v2 1/2] TigerlakeOpenBoardPkg: " Takuto Naito @ 2021-02-21 15:10 ` Takuto Naito 2021-02-22 1:06 ` Heng Luo 2021-02-22 1:09 ` [PATCH v2 0/2] TigerlakeOpenBoard: " Heng Luo ` (2 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Takuto Naito @ 2021-02-21 15:10 UTC (permalink / raw) To: devel; +Cc: Sai Chaganty, Nate DeSimone, Heng Luo REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 - Fix the Teton Glacier Endpoint entry in mPciDeviceTable Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> Cc: Heng Luo <heng.luo@intel.com> Signed-off-by: Takuto Naito <naitaku@gmail.com> --- Notes: v2: - Split the v1 patch into 2 patches, One is for Platform/Intel/TigerlakeOpenBoardPkg, another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. .../DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c index 577e436e32..1553d2e2aa 100644 --- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c @@ -98,7 +98,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = { // // Teton Glacier Endpoint // - { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5, 0, 0, 0, 0 }, + { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5, 0, 0 }, // // End of Table -- 2.30.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 2021-02-21 15:10 ` [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: " Takuto Naito @ 2021-02-22 1:06 ` Heng Luo 0 siblings, 0 replies; 10+ messages in thread From: Heng Luo @ 2021-02-22 1:06 UTC (permalink / raw) To: Takuto Naito, devel@edk2.groups.io Cc: Chaganty, Rangasai V, Desimone, Nathaniel L Reviewed-by: Heng Luo <heng.luo@intel.com> > -----Original Message----- > From: Takuto Naito <naitaku@gmail.com> > Sent: Sunday, February 21, 2021 11:10 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, > Nathaniel L <nathaniel.l.desimone@intel.com>; Luo, Heng <heng.luo@intel.com> > Subject: [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 > > - Fix the Teton Glacier Endpoint entry in mPciDeviceTable > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Heng Luo <heng.luo@intel.com> > Signed-off-by: Takuto Naito <naitaku@gmail.com> > --- > > Notes: > v2: > - Split the v1 patch into 2 patches, > One is for Platform/Intel/TigerlakeOpenBoardPkg, > another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. > > .../DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp > PolicyLib/DxePchPcieRpPolicyLib.c > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp > PolicyLib/DxePchPcieRpPolicyLib.c > index 577e436e32..1553d2e2aa 100644 > --- > a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp > PolicyLib/DxePchPcieRpPolicyLib.c > +++ > b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRp > PolicyLib/DxePchPcieRpPolicyLib.c > @@ -98,7 +98,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED > PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = { > // > // Teton Glacier Endpoint > // > - { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5, > 0, 0, 0, 0 }, > + { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5, > 0, 0 }, > > // > // End of Table > -- > 2.30.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 2021-02-21 15:10 [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 Takuto Naito 2021-02-21 15:10 ` [PATCH v2 1/2] TigerlakeOpenBoardPkg: " Takuto Naito 2021-02-21 15:10 ` [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: " Takuto Naito @ 2021-02-22 1:09 ` Heng Luo 2021-02-22 22:21 ` Nate DeSimone 2021-02-22 22:27 ` Nate DeSimone 4 siblings, 0 replies; 10+ messages in thread From: Heng Luo @ 2021-02-22 1:09 UTC (permalink / raw) To: Takuto Naito, devel@edk2.groups.io Cc: Chaganty, Rangasai V, Desimone, Nathaniel L Thanks Takuto Naito! For the series.. Reviewed-by: Heng Luo <heng.luo@intel.com> > -----Original Message----- > From: Takuto Naito <naitaku@gmail.com> > Sent: Sunday, February 21, 2021 11:10 PM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, > Nathaniel L <nathaniel.l.desimone@intel.com>; Luo, Heng <heng.luo@intel.com> > Subject: [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 > TigerlakeOpenBoard: Fix build errors with GCC5 > > v2: > - Split the v1 patch into 2 patches. > One is for Platform/Intel/TigerlakeOpenBoardPkg, > another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. > > https://github.com/naitaku/edk2-platforms/tree/tigerlake_fix_build_error_v2 > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Heng Luo <heng.luo@intel.com> > > Takuto Naito (2): > TigerlakeOpenBoardPkg: Fix build errors with GCC5 > TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 > > .../PeiFspPolicyInitLib.inf | 2 +- > .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------ > .../DxeSiliconPolicyUpdateLate.c | 2 +- > .../DxePchPcieRpPolicyLib.c | 2 +- > 4 files changed, 3 insertions(+), 191 deletions(-) > > -- > 2.30.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 2021-02-21 15:10 [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 Takuto Naito ` (2 preceding siblings ...) 2021-02-22 1:09 ` [PATCH v2 0/2] TigerlakeOpenBoard: " Heng Luo @ 2021-02-22 22:21 ` Nate DeSimone 2021-02-22 22:27 ` Nate DeSimone 4 siblings, 0 replies; 10+ messages in thread From: Nate DeSimone @ 2021-02-22 22:21 UTC (permalink / raw) To: Takuto Naito, devel@edk2.groups.io; +Cc: Chaganty, Rangasai V, Luo, Heng Thank You Takuto! For the series... Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com> > -----Original Message----- > From: Takuto Naito <naitaku@gmail.com> > Sent: Sunday, February 21, 2021 7:10 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, > Nathaniel L <nathaniel.l.desimone@intel.com>; Luo, Heng > <heng.luo@intel.com> > Subject: [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 > TigerlakeOpenBoard: Fix build errors with GCC5 > > v2: > - Split the v1 patch into 2 patches. > One is for Platform/Intel/TigerlakeOpenBoardPkg, > another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. > > https://github.com/naitaku/edk2- > platforms/tree/tigerlake_fix_build_error_v2 > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Heng Luo <heng.luo@intel.com> > > Takuto Naito (2): > TigerlakeOpenBoardPkg: Fix build errors with GCC5 > TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 > > .../PeiFspPolicyInitLib.inf | 2 +- > .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------ > .../DxeSiliconPolicyUpdateLate.c | 2 +- > .../DxePchPcieRpPolicyLib.c | 2 +- > 4 files changed, 3 insertions(+), 191 deletions(-) > > -- > 2.30.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 2021-02-21 15:10 [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 Takuto Naito ` (3 preceding siblings ...) 2021-02-22 22:21 ` Nate DeSimone @ 2021-02-22 22:27 ` Nate DeSimone 2021-02-23 17:01 ` Takuto Naito 4 siblings, 1 reply; 10+ messages in thread From: Nate DeSimone @ 2021-02-22 22:27 UTC (permalink / raw) To: Takuto Naito, devel@edk2.groups.io; +Cc: Chaganty, Rangasai V, Luo, Heng The series has been pushed as 12ef75d~.. 9fb5174 Thanks, Nate > -----Original Message----- > From: Takuto Naito <naitaku@gmail.com> > Sent: Sunday, February 21, 2021 7:10 AM > To: devel@edk2.groups.io > Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, > Nathaniel L <nathaniel.l.desimone@intel.com>; Luo, Heng > <heng.luo@intel.com> > Subject: [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 > TigerlakeOpenBoard: Fix build errors with GCC5 > > v2: > - Split the v1 patch into 2 patches. > One is for Platform/Intel/TigerlakeOpenBoardPkg, > another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. > > https://github.com/naitaku/edk2- > platforms/tree/tigerlake_fix_build_error_v2 > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > Cc: Heng Luo <heng.luo@intel.com> > > Takuto Naito (2): > TigerlakeOpenBoardPkg: Fix build errors with GCC5 > TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 > > .../PeiFspPolicyInitLib.inf | 2 +- > .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------ > .../DxeSiliconPolicyUpdateLate.c | 2 +- > .../DxePchPcieRpPolicyLib.c | 2 +- > 4 files changed, 3 insertions(+), 191 deletions(-) > > -- > 2.30.1 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 2021-02-22 22:27 ` Nate DeSimone @ 2021-02-23 17:01 ` Takuto Naito 2021-02-24 1:13 ` [edk2-devel] " Heng Luo 0 siblings, 1 reply; 10+ messages in thread From: Takuto Naito @ 2021-02-23 17:01 UTC (permalink / raw) To: Desimone, Nathaniel L Cc: Chaganty, Rangasai V, Luo, Heng, devel@edk2.groups.io [-- Attachment #1: Type: text/plain, Size: 1871 bytes --] Hi Nate and Heng, The RELEASE build now succeeds, but I noticed that DEBUG build still fails. I'm trying to fix it. Do you need me to submit another BZ ticket or use the same ticket? Best regards, Takuto Naito On Tue, Feb 23, 2021 at 7:27 AM Desimone, Nathaniel L < nathaniel.l.desimone@intel.com> wrote: > The series has been pushed as 12ef75d~.. 9fb5174 > > Thanks, > Nate > > > -----Original Message----- > > From: Takuto Naito <naitaku@gmail.com> > > Sent: Sunday, February 21, 2021 7:10 AM > > To: devel@edk2.groups.io > > Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, > > Nathaniel L <nathaniel.l.desimone@intel.com>; Luo, Heng > > <heng.luo@intel.com> > > Subject: [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 > > > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 > > TigerlakeOpenBoard: Fix build errors with GCC5 > > > > v2: > > - Split the v1 patch into 2 patches. > > One is for Platform/Intel/TigerlakeOpenBoardPkg, > > another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. > > > > https://github.com/naitaku/edk2- > > platforms/tree/tigerlake_fix_build_error_v2 > > > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com> > > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com> > > Cc: Heng Luo <heng.luo@intel.com> > > > > Takuto Naito (2): > > TigerlakeOpenBoardPkg: Fix build errors with GCC5 > > TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 > > > > .../PeiFspPolicyInitLib.inf | 2 +- > > .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------ > > .../DxeSiliconPolicyUpdateLate.c | 2 +- > > .../DxePchPcieRpPolicyLib.c | 2 +- > > 4 files changed, 3 insertions(+), 191 deletions(-) > > > > -- > > 2.30.1 > > -- 内藤 卓人 Takuto Naito [-- Attachment #2: Type: text/html, Size: 3560 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [edk2-devel] [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 2021-02-23 17:01 ` Takuto Naito @ 2021-02-24 1:13 ` Heng Luo 0 siblings, 0 replies; 10+ messages in thread From: Heng Luo @ 2021-02-24 1:13 UTC (permalink / raw) To: devel@edk2.groups.io, naitaku@gmail.com, Desimone, Nathaniel L Cc: Chaganty, Rangasai V [-- Attachment #1: Type: text/plain, Size: 2575 bytes --] Hi Takuto Naito, I think you can add comments in the same BZ ticket and then use it. Thanks, Heng From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Takuto Naito Sent: Wednesday, February 24, 2021 1:02 AM To: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Luo, Heng <heng.luo@intel.com>; devel@edk2.groups.io Subject: Re: [edk2-devel] [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 Hi Nate and Heng, The RELEASE build now succeeds, but I noticed that DEBUG build still fails. I'm trying to fix it. Do you need me to submit another BZ ticket or use the same ticket? Best regards, Takuto Naito On Tue, Feb 23, 2021 at 7:27 AM Desimone, Nathaniel L <nathaniel.l.desimone@intel.com<mailto:nathaniel.l.desimone@intel.com>> wrote: The series has been pushed as 12ef75d~.. 9fb5174 Thanks, Nate > -----Original Message----- > From: Takuto Naito <naitaku@gmail.com<mailto:naitaku@gmail.com>> > Sent: Sunday, February 21, 2021 7:10 AM > To: devel@edk2.groups.io<mailto:devel@edk2.groups.io> > Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com<mailto:rangasai.v.chaganty@intel.com>>; Desimone, > Nathaniel L <nathaniel.l.desimone@intel.com<mailto:nathaniel.l.desimone@intel.com>>; Luo, Heng > <heng.luo@intel.com<mailto:heng.luo@intel.com>> > Subject: [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 > > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 > TigerlakeOpenBoard: Fix build errors with GCC5 > > v2: > - Split the v1 patch into 2 patches. > One is for Platform/Intel/TigerlakeOpenBoardPkg, > another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. > > https://github.com/naitaku/edk2- > platforms/tree/tigerlake_fix_build_error_v2 > > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com<mailto:rangasai.v.chaganty@intel.com>> > Cc: Nate DeSimone <nathaniel.l.desimone@intel.com<mailto:nathaniel.l.desimone@intel.com>> > Cc: Heng Luo <heng.luo@intel.com<mailto:heng.luo@intel.com>> > > Takuto Naito (2): > TigerlakeOpenBoardPkg: Fix build errors with GCC5 > TigerlakeSiliconPkg/IpBlock: Fix build errors with GCC5 > > .../PeiFspPolicyInitLib.inf | 2 +- > .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------ > .../DxeSiliconPolicyUpdateLate.c | 2 +- > .../DxePchPcieRpPolicyLib.c | 2 +- > 4 files changed, 3 insertions(+), 191 deletions(-) > > -- > 2.30.1 -- 内藤 卓人 Takuto Naito [-- Attachment #2: Type: text/html, Size: 6946 bytes --] ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2021-02-24 1:13 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-02-21 15:10 [PATCH v2 0/2] TigerlakeOpenBoard: Fix build errors with GCC5 Takuto Naito 2021-02-21 15:10 ` [PATCH v2 1/2] TigerlakeOpenBoardPkg: " Takuto Naito 2021-02-22 1:06 ` Heng Luo 2021-02-21 15:10 ` [PATCH v2 2/2] TigerlakeSiliconPkg/IpBlock: " Takuto Naito 2021-02-22 1:06 ` Heng Luo 2021-02-22 1:09 ` [PATCH v2 0/2] TigerlakeOpenBoard: " Heng Luo 2021-02-22 22:21 ` Nate DeSimone 2021-02-22 22:27 ` Nate DeSimone 2021-02-23 17:01 ` Takuto Naito 2021-02-24 1:13 ` [edk2-devel] " Heng Luo
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