[PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.

[PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.

[Chiu, Chasel]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391

FSP should support the scenario that CPU microcode already loaded
before calling LoadMicrocodeDefault(), in this case it should return
directly without spending more time.
Also the LoadMicrocodeDefault() should only attempt to load one version
of the microcode for current CPU and return.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 18 ++++++++++++++----
 IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm  | 16 ++++++++++++----
 2 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 2cff8b3643..b902d017ee 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -245,6 +245,19 @@ ASM_PFX(LoadMicrocodeDefault):
    cmp    esp, 0
    jz     ParamError
 
+   ;
+   ; If microcode already loaded before this function, exit this function with SUCCESS.
+   ;
+   mov   eax, 1
+   cpuid
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID
+   rdmsr                         ; Get current microcode signature
+   xor   eax, eax
+   test  edx, edx
+   jnz   Exit2
+
+
+
    ; skip loading Microcode if the MicrocodeCodeSize is zero
    ; and report error if size is less than 2k
    ; first check UPD header revision
@@ -450,7 +463,7 @@ LoadCheck:
 
    ; Verify this microcode update is not already loaded
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
-   je    Continue
+   je    Done ; if already one version microcode loaded, go to done
 
 LoadMicrocode:
    ; EAX contains the linear address of the start of the Update Data
@@ -465,9 +478,6 @@ LoadMicrocode:
    mov   eax, 1
    cpuid
 
-Continue:
-   jmp   NextMicrocode
-
 Done:
    mov   eax, 1
    cpuid
diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index b32fa32a89..2a23c33c9b 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -141,6 +141,17 @@ ASM_PFX(LoadMicrocodeDefault):
    jz     ParamError
    mov    rsp, rcx
 
+   ;
+   ; If microcode already loaded before this function, exit this function with SUCCESS.
+   ;
+   mov   eax, 1
+   cpuid
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID
+   rdmsr                         ; Get current microcode signature
+   xor   rax, rax
+   test  edx, edx
+   jnz   Exit2
+
    ; skip loading Microcode if the MicrocodeCodeSize is zero
    ; and report error if size is less than 2k
    ; first check UPD header revision
@@ -291,7 +302,7 @@ LoadCheck:
 
    ; Verify this microcode update is not already loaded
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx
-   je    Continue
+   je    Done ; if already one version microcode loaded, go to done
 
 LoadMicrocode:
    ; EAX contains the linear address of the start of the Update Data
@@ -306,9 +317,6 @@ LoadMicrocode:
    mov   eax, 1
    cpuid
 
-Continue:
-   jmp   NextMicrocode
-
 Done:
    mov   eax, 1
    cpuid
-- 
2.35.0.windows.1

Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.

[Kuo, Ted]

Reviewed-by: Ted Kuo <ted.kuo@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Chiu, Chasel
Sent: Wednesday, March 29, 2023 11:44 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star <star.zeng@intel.com>; Ni, Ray <ray.ni@intel.com>
Subject: [edk2-devel] [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391

FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time.
Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
---
 IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 18 ++++++++++++++----  IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm  | 16 ++++++++++++----
 2 files changed, 26 insertions(+), 8 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 2cff8b3643..b902d017ee 100644
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -245,6 +245,19 @@ ASM_PFX(LoadMicrocodeDefault):
    cmp    esp, 0    jz     ParamError +   ;+   ; If microcode already loaded before this function, exit this function with SUCCESS.+   ;+   mov   eax, 1+   cpuid+   mov   ecx, MSR_IA32_BIOS_SIGN_ID+   rdmsr                         ; Get current microcode signature+   xor   eax, eax+   test  edx, edx+   jnz   Exit2+++    ; skip loading Microcode if the MicrocodeCodeSize is zero    ; and report error if size is less than 2k    ; first check UPD header revision@@ -450,7 +463,7 @@ LoadCheck:
     ; Verify this microcode update is not already loaded    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx-   je    Continue+   je    Done ; if already one version microcode loaded, go to done  LoadMicrocode:    ; EAX contains the linear address of the start of the Update Data@@ -465,9 +478,6 @@ LoadMicrocode:
    mov   eax, 1    cpuid -Continue:-   jmp   NextMicrocode- Done:    mov   eax, 1    cpuiddiff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index b32fa32a89..2a23c33c9b 100644
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -141,6 +141,17 @@ ASM_PFX(LoadMicrocodeDefault):
    jz     ParamError    mov    rsp, rcx +   ;+   ; If microcode already loaded before this function, exit this function with SUCCESS.+   ;+   mov   eax, 1+   cpuid+   mov   ecx, MSR_IA32_BIOS_SIGN_ID+   rdmsr                         ; Get current microcode signature+   xor   rax, rax+   test  edx, edx+   jnz   Exit2+    ; skip loading Microcode if the MicrocodeCodeSize is zero    ; and report error if size is less than 2k    ; first check UPD header revision@@ -291,7 +302,7 @@ LoadCheck:
     ; Verify this microcode update is not already loaded    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx-   je    Continue+   je    Done ; if already one version microcode loaded, go to done  LoadMicrocode:    ; EAX contains the linear address of the start of the Update Data@@ -306,9 +317,6 @@ LoadMicrocode:
    mov   eax, 1    cpuid -Continue:-   jmp   NextMicrocode- Done:    mov   eax, 1    cpuid-- 
2.35.0.windows.1



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Re: [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.

[Ni, Ray]

> 
> +   mov   eax, 1
> 
> +   cpuid
> 
> +   mov   ecx, MSR_IA32_BIOS_SIGN_ID
> 
> +   rdmsr                         ; Get current microcode signature
> 
> +   xor   eax, eax
> 
> +   test  edx, edx
> 
> +   jnz   Exit2
> 
1. SDM uses following assembly to read current microcode signature.

Example 10-9. Assembly Code to Retrieve the Update Revision
MOV ECX, 08BH ;IA32_BIOS_SIGN_ID
XOR EAX, EAX ;clear EAX
XOR EDX, EDX ;clear EDX
WRMSR ;Load 0 to MSR at 8BH
MOV EAX, 1
Cupid
MOV ECX, 08BH ;IA32_BIOS_SIGN_ID
rdmsr ;Read Model Specific Register


Comparing against yours, I think there are two diffs:
1). you missed the write-zero to msr 8b
2). you cleared RAX (I don't know why)

And the existing code "LoadCheck:" actually contains exactly the SDM
recommended logic to get current microcode revision.
Why not use that directly?

> -   je    Continue
> 
> +   je    Done ; if already one version microcode loaded, go to done

2. You changed another behavior: from load all microcodes to load one only.
Can you separate it in a standalone patch and explain in commit?
I guess since the 1st check you added will skip loading when cpu microcode revision
is not 0, so the change here is to align with that behavior.

Re: [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.

[Chiu, Chasel]

Thanks for reviewing Ray!
Please see my reply below inline.


> -----Original Message-----
> From: Ni, Ray <ray.ni@intel.com>
> Sent: Wednesday, March 29, 2023 10:31 PM
> To: Chiu, Chasel <chasel.chiu@intel.com>; devel@edk2.groups.io
> Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Zeng, Star
> <star.zeng@intel.com>
> Subject: RE: [PATCH v2] IntelFsp2Pkg: LoadMicrocodeDefault() causing
> unnecessary delay.
> 
> >
> > +   mov   eax, 1
> >
> > +   cpuid
> >
> > +   mov   ecx, MSR_IA32_BIOS_SIGN_ID
> >
> > +   rdmsr                         ; Get current microcode signature
> >
> > +   xor   eax, eax
> >
> > +   test  edx, edx
> >
> > +   jnz   Exit2
> >
> 1. SDM uses following assembly to read current microcode signature.
> 
> Example 10-9. Assembly Code to Retrieve the Update Revision MOV ECX,
> 08BH ;IA32_BIOS_SIGN_ID XOR EAX, EAX ;clear EAX XOR EDX, EDX ;clear EDX
> WRMSR ;Load 0 to MSR at 8BH MOV EAX, 1 Cupid MOV ECX,
> 08BH ;IA32_BIOS_SIGN_ID rdmsr ;Read Model Specific Register
> 
> 
> Comparing against yours, I think there are two diffs:
> 1). you missed the write-zero to msr 8b


I will add this back.


> 2). you cleared RAX (I don't know why)


This is for returning 0 (EFI_SUCCESS) to caller when microcode already loaded.



> 
> And the existing code "LoadCheck:" actually contains exactly the SDM
> recommended logic to get current microcode revision.
> Why not use that directly?
> 
> > -   je    Continue
> >
> > +   je    Done ; if already one version microcode loaded, go to done
> 
> 2. You changed another behavior: from load all microcodes to load one only.
> Can you separate it in a standalone patch and explain in commit?
> I guess since the 1st check you added will skip loading when cpu microcode
> revision is not 0, so the change here is to align with that behavior.



This is another optimization for reducing unnecessary delay and I explained this in commit message (second line).
Because that we usually only put one version microcode for one CPU in FV, if LoadMicrocodeDefault() already found one matching microcode and attempted to load it, then it should return with either SUCCESS or ERROR and no need to parse rest of the microcode files in FV. 

Commit message:
FSP should support the scenario that CPU microcode already loaded before calling LoadMicrocodeDefault(), in this case it should return directly without spending more time.
Also the LoadMicrocodeDefault() should only attempt to load one version of the microcode for current CPU and return.