From: "Duran, Leo" <leo.duran@amd.com>
To: "'Fan, Jeff'" <jeff.fan@intel.com>,
"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: "Justen, Jordan L" <jordan.l.justen@intel.com>,
"Gao, Liming" <liming.gao@intel.com>,
"Singh, Brijesh" <brijesh.singh@amd.com>
Subject: Re: [PATCH v5 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
Date: Wed, 21 Jun 2017 17:46:28 +0000 [thread overview]
Message-ID: <DM5PR12MB124329080DAD81CDB1C3CACAF9DA0@DM5PR12MB1243.namprd12.prod.outlook.com> (raw)
In-Reply-To: <542CF652F8836A4AB8DBFAAD40ED192A4C610A9F@shsmsx102.ccr.corp.intel.com>
Excellent, Jeff.
Thanks,
Leo.
> -----Original Message-----
> From: Fan, Jeff [mailto:jeff.fan@intel.com]
> Sent: Tuesday, June 20, 2017 9:10 PM
> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@lists.01.org
> Cc: Justen, Jordan L <jordan.l.justen@intel.com>; Gao, Liming
> <liming.gao@intel.com>; Singh, Brijesh <brijesh.singh@amd.com>
> Subject: RE: [PATCH v5 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
>
> I noticed this serial of patches depend on another SEV patch on UefiCpuPkg(
> I have reviewed-by it before).
> I will push them together in a couple of days if you have no other comments.
>
> Thanks!
> Jeff
>
> -----Original Message-----
> From: Leo Duran [mailto:leo.duran@amd.com]
> Sent: Saturday, June 17, 2017 8:42 AM
> To: edk2-devel@lists.01.org
> Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh
> Subject: [PATCH v5 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId()
> to support AMD.
>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Jeff Fan <jeff.fan@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Brijesh Singh <brijesh.singh@amd.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran <leo.duran@amd.com>
> ---
> UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 157
> ++++++++++++++++-----
> .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 157 ++++++++++++++++-
> ----
> 2 files changed, 250 insertions(+), 64 deletions(-)
>
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> index f81bbb2..2091e5e 100644
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> @@ -4,6 +4,8 @@
> This local APIC library instance supports xAPIC mode only.
>
> Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> +
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of the BSD
> License
> which accompanies this distribution. The full text of the license may be
> found at @@ -15,6 +17,7 @@ **/
>
> #include <Register/Cpuid.h>
> +#include <Register/Amd/Cpuid.h>
> #include <Register/Msr.h>
> #include <Register/LocalApic.h>
>
> @@ -30,6 +33,28 @@
> //
>
> /**
> + Determine if the standard CPU signature is "AuthenticAMD".
> +
> + @retval TRUE The CPU signature matches.
> + @retval FALSE The CPU signature does not match.
> +
> +**/
> +BOOLEAN
> +StandardSignatureIsAuthenticAMD (
> + VOID
> + )
> +{
> + UINT32 RegEbx;
> + UINT32 RegEcx;
> + UINT32 RegEdx;
> +
> + AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
> +}
> +
> +/**
> Determine if the CPU supports the Local APIC Base Address MSR.
>
> @retval TRUE The CPU supports the Local APIC Base Address MSR.
> @@ -966,20 +991,30 @@ GetProcessorLocationByApicId (
> OUT UINT32 *Thread OPTIONAL
> )
> {
> - BOOLEAN TopologyLeafSupported;
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> + BOOLEAN TopologyLeafSupported;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> + UINT32 MaxStandardCpuIdIndex;
> + UINT32 MaxExtendedCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> + UINT32 MaxThreadPerPackageMask;
> + UINT32 ActualThreadPerPackageMask;
> + UINT32 MaxCoresPerNode;
> + UINT32 CorePerNodeMask;
> + UINT32 ApicIdShift;
> + UINTN ThreadBits;
> + UINTN CoreBits;
>
> //
> // Check if the processor is capable of supporting more than one logical
> processor.
> @@ -987,10 +1022,10 @@ GetProcessorLocationByApicId (
> AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> if (VersionInfoEdx.Bits.HTT == 0) {
> if (Thread != NULL) {
> - *Thread = 0;
> + *Thread = 0;
> }
> if (Core != NULL) {
> - *Core = 0;
> + *Core = 0;
> }
> if (Package != NULL) {
> *Package = 0;
> @@ -998,24 +1033,24 @@ GetProcessorLocationByApicId (
> return;
> }
>
> + //
> + // Assume three-level mapping of APIC ID: Package|Core|Thread.
> + //
> ThreadBits = 0;
> CoreBits = 0;
>
> //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + // Get max index of CPUID
> //
> - TopologyLeafSupported = FALSE;
> -
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> NULL);
> + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> NULL, NULL,
> + NULL);
>
> //
> // If the extended topology enumeration leaf is available, it
> // is the preferred mechanism for enumerating topology.
> //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + TopologyLeafSupported = FALSE;
> + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> AsmCpuidEx(
> CPUID_EXTENDED_TOPOLOGY,
> 0,
> @@ -1065,27 +1100,85 @@ GetProcessorLocationByApicId (
> }
>
> if (!TopologyLeafSupported) {
> + //
> + // Get logical processor count
> + //
> AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> NULL);
> MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> - MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> +
> + //
> + // Assume single-core processor
> + //
> + MaxCoresPerPackage = 1;
> +
> + //
> + // Check for topology extensions on AMD processor
> + //
> + if (StandardSignatureIsAuthenticAMD()) {
> + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> &AmdExtendedCpuSigEcx.Uint32, NULL);
> + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> &AmdProcessorTopologyEbx.Uint32,
> + &AmdProcessorTopologyEcx.Uint32, NULL);
> + //
> + // Get cores per processor package
> + //
> + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> +
> + //
> + // Account for actual thread count (e.g., SMT disabled)
> + //
> + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> + MaxThreadPerPackageMask = 1 <<
> AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> + ActualThreadPerPackageMask = 1;
> + while (ActualThreadPerPackageMask <
> MaxLogicProcessorsPerPackage) {
> + ActualThreadPerPackageMask <<= 1;
> + }
> +
> + //
> + // Adjust APIC Id to report concatenation of Package|Core|Thread.
> + //
> + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> + MaxCoresPerNode = MaxCoresPerPackage /
> + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> +
> + CorePerNodeMask = 1;
> + while (CorePerNodeMask < MaxCoresPerNode) {
> + CorePerNodeMask <<= 1;
> + }
> + CorePerNodeMask -= 1;
> +
> + ApicIdShift = 0;
> + do {
> + ApicIdShift += 1;
> + ActualThreadPerPackageMask <<= 1;
> + } while (ActualThreadPerPackageMask <
> + MaxThreadPerPackageMask);
> +
> + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) |
> (InitialApicId & CorePerNodeMask);
> + }
> + }
> + }
> }
> else {
> //
> - // Must be a single-core processor.
> + // Extract core count based on CACHE information
> //
> - MaxCoresPerPackage = 1;
> + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + if (CacheParamsEax.Uint32 != 0) {
> + MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + }
> + }
> }
>
> ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
>
> if (Thread != NULL) {
> - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> }
> if (Core != NULL) {
> - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> }
> if (Package != NULL) {
> *Package = (InitialApicId >> (ThreadBits + CoreBits)); diff --git
> a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> index e690d2a..d5d4efa 100644
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> @@ -5,6 +5,8 @@
> which have xAPIC and x2APIC modes.
>
> Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> +
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of the BSD
> License
> which accompanies this distribution. The full text of the license may be
> found at @@ -16,6 +18,7 @@ **/
>
> #include <Register/Cpuid.h>
> +#include <Register/Amd/Cpuid.h>
> #include <Register/Msr.h>
> #include <Register/LocalApic.h>
>
> @@ -31,6 +34,28 @@
> //
>
> /**
> + Determine if the standard CPU signature is "AuthenticAMD".
> +
> + @retval TRUE The CPU signature matches.
> + @retval FALSE The CPU signature does not match.
> +
> +**/
> +BOOLEAN
> +StandardSignatureIsAuthenticAMD (
> + VOID
> + )
> +{
> + UINT32 RegEbx;
> + UINT32 RegEcx;
> + UINT32 RegEdx;
> +
> + AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx);
> + return (RegEbx == CPUID_SIGNATURE_AUTHENTIC_AMD_EBX &&
> + RegEcx == CPUID_SIGNATURE_AUTHENTIC_AMD_ECX &&
> + RegEdx == CPUID_SIGNATURE_AUTHENTIC_AMD_EDX);
> +}
> +
> +/**
> Determine if the CPU supports the Local APIC Base Address MSR.
>
> @retval TRUE The CPU supports the Local APIC Base Address MSR.
> @@ -1061,20 +1086,30 @@ GetProcessorLocationByApicId (
> OUT UINT32 *Thread OPTIONAL
> )
> {
> - BOOLEAN TopologyLeafSupported;
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> + BOOLEAN TopologyLeafSupported;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> + UINT32 MaxStandardCpuIdIndex;
> + UINT32 MaxExtendedCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> + UINT32 MaxThreadPerPackageMask;
> + UINT32 ActualThreadPerPackageMask;
> + UINT32 MaxCoresPerNode;
> + UINT32 CorePerNodeMask;
> + UINT32 ApicIdShift;
> + UINTN ThreadBits;
> + UINTN CoreBits;
>
> //
> // Check if the processor is capable of supporting more than one logical
> processor.
> @@ -1082,10 +1117,10 @@ GetProcessorLocationByApicId (
> AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> if (VersionInfoEdx.Bits.HTT == 0) {
> if (Thread != NULL) {
> - *Thread = 0;
> + *Thread = 0;
> }
> if (Core != NULL) {
> - *Core = 0;
> + *Core = 0;
> }
> if (Package != NULL) {
> *Package = 0;
> @@ -1093,24 +1128,24 @@ GetProcessorLocationByApicId (
> return;
> }
>
> + //
> + // Assume three-level mapping of APIC ID: Package|Core|Thread.
> + //
> ThreadBits = 0;
> CoreBits = 0;
>
> //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + // Get max index of CPUID
> //
> - TopologyLeafSupported = FALSE;
> -
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> NULL);
> + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> NULL, NULL,
> + NULL);
>
> //
> // If the extended topology enumeration leaf is available, it
> // is the preferred mechanism for enumerating topology.
> //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + TopologyLeafSupported = FALSE;
> + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> AsmCpuidEx(
> CPUID_EXTENDED_TOPOLOGY,
> 0,
> @@ -1160,27 +1195,85 @@ GetProcessorLocationByApicId (
> }
>
> if (!TopologyLeafSupported) {
> + //
> + // Get logical processor count
> + //
> AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> NULL);
> MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> - MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> +
> + //
> + // Assume single-core processor
> + //
> + MaxCoresPerPackage = 1;
> +
> + //
> + // Check for topology extensions on AMD processor
> + //
> + if (StandardSignatureIsAuthenticAMD()) {
> + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> &AmdExtendedCpuSigEcx.Uint32, NULL);
> + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> &AmdProcessorTopologyEbx.Uint32,
> + &AmdProcessorTopologyEcx.Uint32, NULL);
> + //
> + // Get cores per processor package
> + //
> + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> +
> + //
> + // Account for actual thread count (e.g., SMT disabled)
> + //
> + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> + MaxThreadPerPackageMask = 1 <<
> AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> + ActualThreadPerPackageMask = 1;
> + while (ActualThreadPerPackageMask <
> MaxLogicProcessorsPerPackage) {
> + ActualThreadPerPackageMask <<= 1;
> + }
> +
> + //
> + // Adjust APIC Id to report concatenation of Package|Core|Thread.
> + //
> + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> + MaxCoresPerNode = MaxCoresPerPackage /
> + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> +
> + CorePerNodeMask = 1;
> + while (CorePerNodeMask < MaxCoresPerNode) {
> + CorePerNodeMask <<= 1;
> + }
> + CorePerNodeMask -= 1;
> +
> + ApicIdShift = 0;
> + do {
> + ApicIdShift += 1;
> + ActualThreadPerPackageMask <<= 1;
> + } while (ActualThreadPerPackageMask <
> + MaxThreadPerPackageMask);
> +
> + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) |
> (InitialApicId & CorePerNodeMask);
> + }
> + }
> + }
> }
> else {
> //
> - // Must be a single-core processor.
> + // Extract core count based on CACHE information
> //
> - MaxCoresPerPackage = 1;
> + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + if (CacheParamsEax.Uint32 != 0) {
> + MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + }
> + }
> }
>
> ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
>
> if (Thread != NULL) {
> - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> }
> if (Core != NULL) {
> - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> }
> if (Package != NULL) {
> *Package = (InitialApicId >> (ThreadBits + CoreBits));
> --
> 2.7.4
prev parent reply other threads:[~2017-06-21 17:45 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-17 0:41 [PATCH v5 0/2] UefiCpuPkg: Add CPUID support for AMD Leo Duran
2017-06-17 0:41 ` [PATCH v5 1/2] UefiCpuPkg: Add CPUID definitions " Leo Duran
2017-06-21 2:06 ` Fan, Jeff
2017-06-17 0:41 ` [PATCH v5 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD Leo Duran
2017-06-21 2:09 ` Fan, Jeff
2017-06-21 17:46 ` Duran, Leo [this message]
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