From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0619.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe41::619]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4D9CD81DE4 for ; Fri, 28 Oct 2016 09:49:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=Dw1cbZYT5x8Q37Hdws6C44bqbDuUf8lA85952tuAnMk=; b=IqB5+UTA6f9//5cwPi8HVADKw+qIpSCv3gS/RpjwxkMcLF8qkEo4DuDKfH9AQpWpo1j/L1jye9EygUUQ2cSKpt5ON12tGqZjmX+dxR/RsfpZygZTQuy/f3wPkIokcyGfZA24JkG67zkjGGkkplQ0MtRAcJZI3LTlTnx7O6ogPAc= Received: from DM5PR12MB1243.namprd12.prod.outlook.com (10.168.237.22) by DM5PR12MB1243.namprd12.prod.outlook.com (10.168.237.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.679.12; Fri, 28 Oct 2016 16:49:42 +0000 Received: from DM5PR12MB1243.namprd12.prod.outlook.com ([10.168.237.22]) by DM5PR12MB1243.namprd12.prod.outlook.com ([10.168.237.22]) with mapi id 15.01.0679.018; Fri, 28 Oct 2016 16:49:42 +0000 From: "Duran, Leo" To: 'Laszlo Ersek' , "edk2-devel@ml01.01.org" CC: "liming.gao@intel.com" Thread-Topic: [edk2] [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Thread-Index: AQHSMTgundBvCprSJUurvGFL0Fsu8aC+ENwAgAADDDA= Date: Fri, 28 Oct 2016 16:49:42 +0000 Message-ID: References: <1477672015-17583-1-git-send-email-leo.duran@amd.com> <1477672015-17583-2-git-send-email-leo.duran@amd.com> <2e1124ad-1093-5be3-e789-0eb78f9fa8fb@redhat.com> In-Reply-To: <2e1124ad-1093-5be3-e789-0eb78f9fa8fb@redhat.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=leo.duran@amd.com; x-originating-ip: [165.204.77.1] x-ms-office365-filtering-correlation-id: 636a7cfb-303d-4c8f-56b4-08d3ff526a69 x-microsoft-exchange-diagnostics: 1; DM5PR12MB1243; 7:Fg+fucfO6x7ZohP1DaHu1fyWbW2b/u7Zycp9WbIaXJZt8f4Ls7NI3aSzd5+MKpWLe99xMiaIzSDXhEDvBVbE5BWWN3+CRr6HtvAcyS9EpY1aNTmyzgKdx3Gw0DJQT2g2XXvnGP6AZJBoi7+g+/gVsS4r+TX54+GKE/Qm4ClArLSAA6SNjOm/aWMmhoIgNtgCSKIe6tMnyBa653R+WjaAcQmrCx9zDtHiwZsX+bQt08QV0kusL+ftvprh/ZHWF6viHziH03XHNYh5sb+vMrqHx6yHFtQeBUQjBRnPsG/Y4GUzAJBluF4Mrv1Pxr59hAN61/FTICiNhsFgp+6BSatkTUPTyU6PSJpWOuffwDgpWJ4=; 20:Sp6ONqiwBf8jnpwRflCkYmyNyLuY/GUEdOVskc349cE2RTbp+qSBGyVVXDnNTwlPtQh2Tu/4N657v5ka2ICnxv2U4Uj2N35lc8FdVrMA/5WGvZNXvHpsjIz1OdJnj0+FN7xn2W7/JzbWo3LsFkP9ee5bSAGYeAllZWHGDTvh9/oGtfw2bXH1SsMWlkv6HZ3bmi7S9uHqMyuxAnMWDWxi2rsZlcmkP/CTcOVY6QuVmiyt5IInDV8RdXmW6G/COX3q x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DM5PR12MB1243; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(767451399110)(228905959029699); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040176)(601004)(2401047)(5005006)(8121501046)(3002001)(10201501046)(6055026); SRVR:DM5PR12MB1243; BCL:0; PCL:0; RULEID:; SRVR:DM5PR12MB1243; x-forefront-prvs: 0109D382B0 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(7916002)(199003)(377454003)(24454002)(13464003)(189002)(102836003)(33656002)(122556002)(586003)(19580395003)(92566002)(77096005)(3846002)(2950100002)(7696004)(6116002)(4326007)(2906002)(5660300001)(575784001)(86362001)(8676002)(81166006)(81156014)(74316002)(7846002)(7736002)(305945005)(97736004)(76576001)(2900100001)(19580405001)(66066001)(189998001)(5001770100001)(9686002)(76176999)(99286002)(106356001)(105586002)(106116001)(10400500002)(3280700002)(50986999)(68736007)(3660700001)(2501003)(11100500001)(54356999)(87936001)(101416001)(8936002)(5002640100001)(567584001)(579004)(19627235001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1243; H:DM5PR12MB1243.namprd12.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2016 16:49:42.4329 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1243 Subject: Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Oct 2016 16:49:44 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reply below. > -----Original Message----- > From: Laszlo Ersek [mailto:lersek@redhat.com] > Sent: Friday, October 28, 2016 11:38 AM > To: Duran, Leo ; edk2-devel@ml01.01.org > Cc: liming.gao@intel.com > Subject: Re: [edk2] [PATCH] UefiCpuPkg: Move GetProcessorLocation() to > LocalApicLib library >=20 > On 10/28/16 18:26, Leo Duran wrote: > > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. > > 2) Remove ExtractProcessorLocation() from MpInitLib library. > > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. > > > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Signed-off-by: Leo Duran > > --- > > UefiCpuPkg/Include/Library/LocalApicLib.h | 18 +++ > > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 > +++++++++++++++++++++ > > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 > +++++++++++++++++++++ > > UefiCpuPkg/Library/MpInitLib/MpLib.c | 128 +------------= ------- > > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 121 +------------= ------ > > 5 files changed, 280 insertions(+), 247 deletions(-) mode change > > 100644 =3D> 100755 UefiCpuPkg/Include/Library/LocalApicLib.h > > mode change 100644 =3D> 100755 > > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > mode change 100644 =3D> 100755 > > UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > mode change 100644 =3D> 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c > > mode change 100644 =3D> 100755 > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c >=20 > Can you please remove the file mode changes from the patch? [Duran, Leo] Sure thing... I'll resend it. >=20 > Thank you, > Laszlo >=20 > > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h > > b/UefiCpuPkg/Include/Library/LocalApicLib.h > > old mode 100644 > > new mode 100755 > > index cd4e613..1d5599a > > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h > > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h > > @@ -21,6 +21,9 @@ > > #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode. > > #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode. > > > > +#include > > +#include > > + > > /** > > Retrieve the base address of local APIC. > > > > @@ -410,6 +413,21 @@ GetApicMsiValue ( > > IN BOOLEAN LevelTriggered, > > IN BOOLEAN AssertionLevel > > ); > > + > > +/** > > +Get Package ID/Core ID/Thread ID of a processor. > > + > > +The algorithm assumes the target system has symmetry across physical > > +package boundaries with respect to the number of logical processors pe= r > package, number of cores per package. > > + > > +@param InitialApicId Must be the initial APIC ID of the target logic= al > processor. > > +@param Location Returns the processor location information. > > +**/ > > +VOID > > +GetProcessorLocation( > > + IN UINT32 InitialApicId, > > + OUT EFI_CPU_PHYSICAL_LOCATION *Location ); > > > > #endif > > > > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > old mode 100644 > > new mode 100755 > > index 8d0fb02..2995ac3 > > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > @@ -941,3 +941,133 @@ GetApicMsiValue ( > > } > > return MsiData.Uint64; > > } > > + > > +/** > > +Get Package ID/Core ID/Thread ID of a processor. > > + > > +The algorithm assumes the target system has symmetry across physical > > +package boundaries with respect to the number of logical processors pe= r > package, number of cores per package. > > + > > +@param InitialApicId Must be the initial APIC ID of the target logic= al > processor. > > +@param Location Returns the processor location information. > > +**/ > > +VOID > > +GetProcessorLocation( > > +IN UINT32 InitialApicId, > > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > > +) > > +{ > > + BOOLEAN TopologyLeafSupported; > > + UINTN ThreadBits; > > + UINTN CoreBits; > > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > + UINT32 MaxCpuIdIndex; > > + UINT32 SubIndex; > > + UINTN LevelType; > > + UINT32 MaxLogicProcessorsPerPackage; > > + UINT32 MaxCoresPerPackage; > > + > > + // > > + // Check if the processor is capable of supporting more than one > logical processor. > > + // > > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > > + if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > + Location->Thread =3D 0; > > + Location->Core =3D 0; > > + Location->Package =3D 0; > > + return; > > + } > > + > > + ThreadBits =3D 0; > > + CoreBits =3D 0; > > + > > + // > > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > > + // > > + > > + TopologyLeafSupported =3D FALSE; > > + // > > + // Get the max index of basic CPUID > > + // > > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, > NULL); > > + > > + // > > + // If the extended topology enumeration leaf is available, it > > + // is the preferred mechanism for enumerating topology. > > + // > > + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + 0, > > + &ExtendedTopologyEax.Uint32, > > + &ExtendedTopologyEbx.Uint32, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + // > > + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and > maximum input value for > > + // basic CPUID information is greater than 0BH, then > CPUID.0BH leaf is not > > + // supported on that processor. > > + // > > + if (ExtendedTopologyEbx.Uint32 !=3D 0) { > > + TopologyLeafSupported =3D TRUE; > > + > > + // > > + // Sub-leaf index 0 (ECX=3D 0 as input) provides > enumeration parameters to extract > > + // the SMT sub-field of x2APIC ID. > > + // > > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > + ASSERT(LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > > + > > + // > > + // Software must not assume any "level type" > encoding > > + // value to be related to any sub-leaf index, except > sub-leaf 0. > > + // > > + SubIndex =3D 1; > > + do { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + SubIndex, > > + &ExtendedTopologyEax.Uint32, > > + NULL, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + LevelType =3D > ExtendedTopologyEcx.Bits.LevelType; > > + if (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > > + CoreBits =3D > ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > > + break; > > + } > > + SubIndex++; > > + } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > + } > > + } > > + > > + if (!TopologyLeafSupported) { > > + AsmCpuid(CPUID_VERSION_INFO, NULL, > &VersionInfoEbx.Uint32, NULL, NULL); > > + MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, > &CacheParamsEax.Uint32, NULL, NULL, NULL); > > + MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > + } > > + else { > > + // > > + // Must be a single-core processor. > > + // > > + MaxCoresPerPackage =3D 1; > > + } > > + > > + ThreadBits =3D > (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + > 1); > > + } > > + > > + Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > + Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) -= 1); > > + Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); } > > diff --git > > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > old mode 100644 > > new mode 100755 > > index 4c42696..60d32d2 > > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > @@ -1036,3 +1036,133 @@ GetApicMsiValue ( > > } > > return MsiData.Uint64; > > } > > + > > +/** > > +Get Package ID/Core ID/Thread ID of a processor. > > + > > +The algorithm assumes the target system has symmetry across physical > > +package boundaries with respect to the number of logical processors pe= r > package, number of cores per package. > > + > > +@param InitialApicId Must be the initial APIC ID of the target logic= al > processor. > > +@param Location Returns the processor location information. > > +**/ > > +VOID > > +GetProcessorLocation( > > +IN UINT32 InitialApicId, > > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > > +) > > +{ > > + BOOLEAN TopologyLeafSupported; > > + UINTN ThreadBits; > > + UINTN CoreBits; > > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > + UINT32 MaxCpuIdIndex; > > + UINT32 SubIndex; > > + UINTN LevelType; > > + UINT32 MaxLogicProcessorsPerPackage; > > + UINT32 MaxCoresPerPackage; > > + > > + // > > + // Check if the processor is capable of supporting more than one > logical processor. > > + // > > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > > + if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > + Location->Thread =3D 0; > > + Location->Core =3D 0; > > + Location->Package =3D 0; > > + return; > > + } > > + > > + ThreadBits =3D 0; > > + CoreBits =3D 0; > > + > > + // > > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > > + // > > + > > + TopologyLeafSupported =3D FALSE; > > + // > > + // Get the max index of basic CPUID > > + // > > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, > NULL); > > + > > + // > > + // If the extended topology enumeration leaf is available, it > > + // is the preferred mechanism for enumerating topology. > > + // > > + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + 0, > > + &ExtendedTopologyEax.Uint32, > > + &ExtendedTopologyEbx.Uint32, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + // > > + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and > maximum input value for > > + // basic CPUID information is greater than 0BH, then > CPUID.0BH leaf is not > > + // supported on that processor. > > + // > > + if (ExtendedTopologyEbx.Uint32 !=3D 0) { > > + TopologyLeafSupported =3D TRUE; > > + > > + // > > + // Sub-leaf index 0 (ECX=3D 0 as input) provides > enumeration parameters to extract > > + // the SMT sub-field of x2APIC ID. > > + // > > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > + ASSERT(LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > > + > > + // > > + // Software must not assume any "level type" > encoding > > + // value to be related to any sub-leaf index, except > sub-leaf 0. > > + // > > + SubIndex =3D 1; > > + do { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + SubIndex, > > + &ExtendedTopologyEax.Uint32, > > + NULL, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + LevelType =3D > ExtendedTopologyEcx.Bits.LevelType; > > + if (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > > + CoreBits =3D > ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > > + break; > > + } > > + SubIndex++; > > + } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > + } > > + } > > + > > + if (!TopologyLeafSupported) { > > + AsmCpuid(CPUID_VERSION_INFO, NULL, > &VersionInfoEbx.Uint32, NULL, NULL); > > + MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, > &CacheParamsEax.Uint32, NULL, NULL, NULL); > > + MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > + } > > + else { > > + // > > + // Must be a single-core processor. > > + // > > + MaxCoresPerPackage =3D 1; > > + } > > + > > + ThreadBits =3D > (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + > 1); > > + } > > + > > + Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > + Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) -= 1); > > + Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); } > > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c > > b/UefiCpuPkg/Library/MpInitLib/MpLib.c > > old mode 100644 > > new mode 100755 > > index c3fe721..902e212 > > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( } > > > > /** > > - Get CPU Package/Core/Thread location information. > > - > > - @param[in] InitialApicId CPU APIC ID > > - @param[out] Location Pointer to CPU location information > > -**/ > > -VOID > > -ExtractProcessorLocation ( > > - IN UINT32 InitialApicId, > > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > > - ) > > -{ > > - BOOLEAN TopologyLeafSupported; > > - UINTN ThreadBits; > > - UINTN CoreBits; > > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > - UINT32 MaxCpuIdIndex; > > - UINT32 SubIndex; > > - UINTN LevelType; > > - UINT32 MaxLogicProcessorsPerPackage; > > - UINT32 MaxCoresPerPackage; > > - > > - // > > - // Check if the processor is capable of supporting more than one log= ical > processor. > > - // > > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, > > &VersionInfoEdx.Uint32); > > - if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > - Location->Thread =3D 0; > > - Location->Core =3D 0; > > - Location->Package =3D 0; > > - return; > > - } > > - > > - ThreadBits =3D 0; > > - CoreBits =3D 0; > > - > > - // > > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > > - // > > - > > - TopologyLeafSupported =3D FALSE; > > - // > > - // Get the max index of basic CPUID > > - // > > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > > - > > - // > > - // If the extended topology enumeration leaf is available, it > > - // is the preferred mechanism for enumerating topology. > > - // > > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > - AsmCpuidEx ( > > - CPUID_EXTENDED_TOPOLOGY, > > - 0, > > - &ExtendedTopologyEax.Uint32, > > - &ExtendedTopologyEbx.Uint32, > > - &ExtendedTopologyEcx.Uint32, > > - NULL > > - ); > > - // > > - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum inp= ut > value for > > - // basic CPUID information is greater than 0BH, then CPUID.0BH lea= f is > not > > - // supported on that processor. > > - // > > - if (ExtendedTopologyEbx.Uint32 !=3D 0) { > > - TopologyLeafSupported =3D TRUE; > > - > > - // > > - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration par= ameters > to extract > > - // the SMT sub-field of x2APIC ID. > > - // > > - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > - ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > - ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > > - > > - // > > - // Software must not assume any "level type" encoding > > - // value to be related to any sub-leaf index, except sub-leaf 0. > > - // > > - SubIndex =3D 1; > > - do { > > - AsmCpuidEx ( > > - CPUID_EXTENDED_TOPOLOGY, > > - SubIndex, > > - &ExtendedTopologyEax.Uint32, > > - NULL, > > - &ExtendedTopologyEcx.Uint32, > > - NULL > > - ); > > - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) = { > > - CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBi= ts; > > - break; > > - } > > - SubIndex++; > > - } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > - } > > - } > > - > > - if (!TopologyLeafSupported) { > > - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, > NULL, NULL); > > - MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > > - MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > - } else { > > - // > > - // Must be a single-core processor. > > - // > > - MaxCoresPerPackage =3D 1; > > - } > > - > > - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage= / > MaxCoresPerPackage - 1) + 1); > > - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > > - } > > - > > - Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > - Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBit= s) - 1); > > - Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); -} > > - > > -/** > > Worker function for SwitchBSP(). > > > > Worker function for SwitchBSP(), assigned to the AP which is > > intended @@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo ( > > // > > // Get processor location information > > // > > - ExtractProcessorLocation > > (CpuMpData->CpuData[ProcessorNumber].ApicId, > > &ProcessorInfoBuffer->Location); > > + GetProcessorLocation (CpuMpData- > >CpuData[ProcessorNumber].ApicId, > > + &ProcessorInfoBuffer->Location); > > > > if (HealthData !=3D NULL) { > > HealthData->Uint32 =3D CpuMpData->CpuData[ProcessorNumber].Health; > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > old mode 100644 > > new mode 100755 > > index 40f2a17..75b5fc0 > > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL > mSmmCpuService =3D { > > }; > > > > /** > > - Get Package ID/Core ID/Thread ID of a processor. > > - > > - APIC ID must be an initial APIC ID. > > - > > - The algorithm below assumes the target system has symmetry across > > physical package boundaries > > - with respect to the number of logical processors per package, number= of > cores per package. > > - > > - @param ApicId APIC ID of the target logical processor. > > - @param Location Returns the processor location information. > > -**/ > > -VOID > > -SmmGetProcessorLocation ( > > - IN UINT32 ApicId, > > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > > - ) > > -{ > > - UINTN ThreadBits; > > - UINTN CoreBits; > > - UINT32 RegEax; > > - UINT32 RegEbx; > > - UINT32 RegEcx; > > - UINT32 RegEdx; > > - UINT32 MaxCpuIdIndex; > > - UINT32 SubIndex; > > - UINTN LevelType; > > - UINT32 MaxLogicProcessorsPerPackage; > > - UINT32 MaxCoresPerPackage; > > - BOOLEAN TopologyLeafSupported; > > - > > - ASSERT (Location !=3D NULL); > > - > > - ThreadBits =3D 0; > > - CoreBits =3D 0; > > - TopologyLeafSupported =3D FALSE; > > - > > - // > > - // Check if the processor is capable of supporting more than one log= ical > processor. > > - // > > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); > > - ASSERT ((RegEdx & BIT28) !=3D 0); > > - > > - // > > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > > - // > > - > > - // > > - // Get the max index of basic CPUID > > - // > > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > > - > > - // > > - // If the extended topology enumeration leaf is available, it > > - // is the preferred mechanism for enumerating topology. > > - // > > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, > &RegEcx, NULL); > > - // > > - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum inp= ut > value for > > - // basic CPUID information is greater than 0BH, then CPUID.0BH lea= f is > not > > - // supported on that processor. > > - // > > - if ((RegEbx & 0xffff) !=3D 0) { > > - TopologyLeafSupported =3D TRUE; > > - > > - // > > - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration par= ameters > to extract > > - // the SMT sub-field of x2APIC ID. > > - // > > - LevelType =3D (RegEcx >> 8) & 0xff; > > - ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > - if ((RegEbx & 0xffff) > 1 ) { > > - ThreadBits =3D RegEax & 0x1f; > > - } else { > > - // > > - // HT is not supported > > - // > > - ThreadBits =3D 0; > > - } > > - > > - // > > - // Software must not assume any "level type" encoding > > - // value to be related to any sub-leaf index, except sub-leaf 0. > > - // > > - SubIndex =3D 1; > > - do { > > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, > NULL, &RegEcx, NULL); > > - LevelType =3D (RegEcx >> 8) & 0xff; > > - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) = { > > - CoreBits =3D (RegEax & 0x1f) - ThreadBits; > > - break; > > - } > > - SubIndex++; > > - } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > - } > > - } > > - > > - if (!TopologyLeafSupported) { > > - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); > > - MaxLogicProcessorsPerPackage =3D (RegEbx >> 16) & 0xff; > > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); > > - MaxCoresPerPackage =3D (RegEax >> 26) + 1; > > - } else { > > - // > > - // Must be a single-core processor. > > - // > > - MaxCoresPerPackage =3D 1; > > - } > > - > > - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage= / > MaxCoresPerPackage - 1) + 1); > > - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > > - } > > - > > - Location->Thread =3D ApicId & ~((-1) << ThreadBits); > > - Location->Core =3D (ApicId >> ThreadBits) & ~((-1) << CoreBits); > > - Location->Package =3D (ApicId >> (ThreadBits+ CoreBits)); -} > > - > > -/** > > Gets processor information on the requested processor at the instant= this > call is made. > > > > @param[in] This A pointer to the > EFI_SMM_CPU_SERVICE_PROTOCOL instance. > > @@ -280,7 +161,7 @@ SmmAddProcessor ( > > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D=3D > INVALID_APIC_ID) { > > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D ProcessorId= ; > > gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag =3D 0; > > - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate- > >ProcessorInfo[Index].Location); > > + GetProcessorLocation ((UINT32)ProcessorId, > > + &gSmmCpuPrivate->ProcessorInfo[Index].Location); > > > > *ProcessorNumber =3D Index; > > gSmmCpuPrivate->Operation[Index] =3D SmmCpuAdd; > >