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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Star,=20 Please double-check the complete [PATCH v3 2/4]. Yes, there is a non-functional change where I did break a 'very long' line = into 2 lines as you noted (I can put that back as it was before if so requi= red). However the intended functional changes are applied in the rest of the patc= h in lines where I reference 'AddressSetMask'. As for [PATCH v3 4/4] The intended functional changes are applied... please confirm, or please le= t me know what seems to be missing. Thanks, Leo. > -----Original Message----- > From: Zeng, Star [mailto:star.zeng@intel.com] > Sent: Monday, February 20, 2017 12:05 AM > To: Duran, Leo ; edk2-devel@ml01.01.org > Cc: Laszlo Ersek ; Feng Tian ; > Singh, Brijesh ; star.zeng@intel.com > Subject: Re: [edk2] [PATCH v3 2/4] MdeModulePkg/Universal/CapsulePei: > Add support for PCD PcdPteMemoryEncryptionAddressOrMask >=20 > Leo, >=20 > Comments added inline. >=20 > On 2017/2/17 5:02, Leo Duran wrote: > > This PCD holds the address mask for page table entries when memory > > encryption is enabled on AMD processors supporting the Secure > > Encrypted Virtualization (SEV) feature. > > > > The mask is applied when 4GB tables are created (UefiCapsule.c), and > > when the tables are expanded on-demand by page-faults above 4GB's > (X64Entry.c). > > > > Cc: Feng Tian > > Cc: Star Zeng > > Cc: Laszlo Ersek > > Cc: Brijesh Singh > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Signed-off-by: Leo Duran > > Reviewed-by: Star Zeng > > --- > > MdeModulePkg/Universal/CapsulePei/CapsulePei.inf | 2 ++ > > .../Universal/CapsulePei/Common/CommonHeader.h | 7 +++++++ > > MdeModulePkg/Universal/CapsulePei/UefiCapsule.c | 13 ++++++++---- > > MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c | 23 > +++++++++++++++------- > > 4 files changed, 34 insertions(+), 11 deletions(-) > > >=20 > [snipped] >=20 > > diff --git a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c > > b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c > > index 5ad95d2..2197502 100644 > > --- a/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c > > +++ b/MdeModulePkg/Universal/CapsulePei/X64/X64Entry.c > > @@ -2,6 +2,8 @@ > > The X64 entrypoint is used to process capsule in long mode. > > > > Copyright (c) 2011 - 2016, Intel Corporation. All rights > > reserved.
> > +Copyright (c) 2017, AMD Incorporated. All rights reserved.
> > + > > This program and the accompanying materials are licensed and made > > available under the terms and conditions of the BSD License which > > accompanies this distribution. The full text of the license may be > > found at @@ -29,6 +31,7 @@ typedef struct _PAGE_FAULT_CONTEXT { > > UINT64 PhyMask; > > UINTN PageFaultBuffer; > > UINTN PageFaultIndex; > > + UINT64 PteMemoryEncryptionAddressOrMask; > > // > > // Store the uplink information for each page being used. > > // > > @@ -114,6 +117,7 @@ AcquirePage ( > > ) > > { > > UINTN Address; > > + UINT64 AddressSetMask; > > > > Address =3D PageFaultContext->PageFaultBuffer + EFI_PAGES_TO_SIZE > (PageFaultContext->PageFaultIndex); > > ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1)); @@ -121,14 > > +125,16 @@ AcquirePage ( > > // > > // Cut the previous uplink if it exists and wasn't overwritten. > > // > > - if > > ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] > > !=3D NULL) && > > ((*PageFaultContext->PageFaultUplink[PageFaultContext- > >PageFaultIndex] > > & PageFaultContext->PhyMask) =3D=3D Address)) { > > + if ((PageFaultContext->PageFaultUplink[PageFaultContext- > >PageFaultIndex] !=3D NULL) && > > + > > + ((*PageFaultContext->PageFaultUplink[PageFaultContext- > >PageFaultInde > > + x] & PageFaultContext->PhyMask) =3D=3D Address)) { >=20 > No real change at here except the line feed added. > You were going to update code at here, but forgot to do the real change? >=20 > Will you do similar change for [PATCH v3 4/4] >=20 > Thanks, > Star >=20 > > *PageFaultContext->PageFaultUplink[PageFaultContext- > >PageFaultIndex] =3D 0; > > } > > > > // > > // Link & Record the current uplink. > > // > > - *Uplink =3D Address | IA32_PG_P | IA32_PG_RW; > > + AddressSetMask =3D > > + PageFaultContext->PteMemoryEncryptionAddressOrMask; > > + *Uplink =3D Address | (AddressSetMask & > PAGING_4K_ADDRESS_MASK_64) | > > + IA32_PG_P | IA32_PG_RW; > > PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] > > =3D Uplink; > > > > PageFaultContext->PageFaultIndex =3D > > (PageFaultContext->PageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES; > @@ -153,6 +159,7 @@ PageFaultHandler ( > > UINT64 *PageTable; > > UINT64 PFAddress; > > UINTN PTIndex; > > + UINT64 AddressSetMask; > > > > // > > // Get the IDT Descriptor. > > @@ -163,6 +170,7 @@ PageFaultHandler ( > > // > > PageFaultContext =3D (PAGE_FAULT_CONTEXT *) (UINTN) (Idtr.Base - > sizeof (PAGE_FAULT_CONTEXT)); > > PhyMask =3D PageFaultContext->PhyMask; > > + AddressSetMask =3D > > + PageFaultContext->PteMemoryEncryptionAddressOrMask; > > > > PFAddress =3D AsmReadCr2 (); > > DEBUG ((EFI_D_ERROR, "CapsuleX64 - PageFaultHandler: Cr2 - %lx\n", > > PFAddress)); @@ -179,19 +187,19 @@ PageFaultHandler ( > > if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { > > AcquirePage (PageFaultContext, &PageTable[PTIndex]); > > } > > - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask); > > + PageTable =3D (UINT64*)(UINTN)((PageTable[PTIndex] & > ~(AddressSetMask > > + & PAGING_4K_ADDRESS_MASK_64)) & PhyMask); > > PTIndex =3D BitFieldRead64 (PFAddress, 30, 38); > > // PDPTE > > if (PageFaultContext->Page1GSupport) { > > - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 30) - 1)) | IA32_PG= _P | > IA32_PG_RW | IA32_PG_PS; > > + PageTable[PTIndex] =3D ((PFAddress | (AddressSetMask & > > + PAGING_1G_ADDRESS_MASK_64)) & ~((1ull << 30) - 1)) | IA32_PG_P | > > + IA32_PG_RW | IA32_PG_PS; > > } else { > > if ((PageTable[PTIndex] & IA32_PG_P) =3D=3D 0) { > > AcquirePage (PageFaultContext, &PageTable[PTIndex]); > > } > > - PageTable =3D (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask); > > + PageTable =3D (UINT64*)(UINTN)((PageTable[PTIndex] & > > + ~(AddressSetMask & PAGING_4K_ADDRESS_MASK_64)) & PhyMask); > > PTIndex =3D BitFieldRead64 (PFAddress, 21, 29); > > // PD > > - PageTable[PTIndex] =3D (PFAddress & ~((1ull << 21) - 1)) | IA32_PG= _P | > IA32_PG_RW | IA32_PG_PS; > > + PageTable[PTIndex] =3D ((PFAddress | (AddressSetMask & > > + PAGING_2M_ADDRESS_MASK_64)) & ~((1ull << 21) - 1)) | IA32_PG_P | > > + IA32_PG_RW | IA32_PG_PS; > > } > > > > return NULL; > > @@ -244,6 +252,7 @@ _ModuleEntryPoint ( > > // Hook page fault handler to handle >4G request. > > // > > PageFaultIdtTable.PageFaultContext.Page1GSupport =3D > > EntrypointContext->Page1GSupport; > > + > PageFaultIdtTable.PageFaultContext.PteMemoryEncryptionAddressOrMask > > + =3D EntrypointContext->PteMemoryEncryptionAddressOrMask; > > IdtEntry =3D (IA32_IDT_GATE_DESCRIPTOR *) (X64Idtr.Base + (14 * size= of > (IA32_IDT_GATE_DESCRIPTOR))); > > HookPageFaultHandler (IdtEntry, > > &(PageFaultIdtTable.PageFaultContext)); > > > > @@ -298,4 +307,4 @@ _ModuleEntryPoint ( > > // > > ASSERT (FALSE); > > return EFI_SUCCESS; > > -} > > \ No newline at end of file > > +} > >