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Thread-Index: AQHTQsmGEES8Mp+Sr0GSX5QnxHcxuKLhBlYAgAKAdUA= Date: Sat, 14 Oct 2017 16:08:16 +0000 Message-ID: References: <1507751131-32404-1-git-send-email-leo.duran@amd.com> <74D8A39837DF1E4DA445A8C0B3885C503A9E505E@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503A9E505E@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=leo.duran@amd.com; x-originating-ip: [24.55.35.68] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DM5PR12MB1243; 20:up9e5JhZyDj3kWg+SLEeE35+PHNaWXPz2Fr081BeRF2Gz4VsgTmqZFxBN0XEysP2Wqk1Dtb2nlgGLPPR/Y/okqpgiJNW8CBgtlSFKGSbk0l97KmAhaSouJVYwkTDXc2opuEQrejvDYSxjn3qJglNY+E49KWCEv6HwiYRjsJuU/zf9cOc7HAZxVSsqP4EiH5OjBidgBgPSUftmMD338jVE4/sbKmhp1mlbx/4uVWq9tPCrbtDN3n2ns1drSypGZiP x-ms-exchange-antispam-srfa-diagnostics: SSOS; x-ms-office365-filtering-correlation-id: 982ecb98-2aaa-45f7-8e8a-08d5131dc7ec x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254152)(48565401081)(2017052603199)(201703131423075)(201703031133081)(201702281549075); SRVR:DM5PR12MB1243; x-ms-traffictypediagnostic: DM5PR12MB1243: x-exchange-antispam-report-test: UriScan:(767451399110)(788757137089)(162533806227266)(228905959029699); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(5005006)(8121501046)(100000703101)(100105400095)(10201501046)(3002001)(93006095)(93001095)(6055026)(6041248)(20161123564025)(20161123560025)(20161123555025)(20161123562025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123558100)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:DM5PR12MB1243; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:DM5PR12MB1243; x-forefront-prvs: 046060344D x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(376002)(39860400002)(346002)(377454003)(189002)(199003)(13464003)(45984002)(33656002)(53936002)(76176999)(54356999)(77096006)(2900100001)(6436002)(7736002)(74316002)(6506006)(55016002)(305945005)(99286003)(105586002)(5660300001)(101416001)(106356001)(6246003)(189998001)(50986999)(7696004)(229853002)(68736007)(25786009)(8936002)(316002)(53546010)(3280700002)(3660700001)(2950100002)(97736004)(966005)(9686003)(81156014)(81166006)(2501003)(478600001)(6306002)(8676002)(110136005)(2906002)(3846002)(102836003)(66066001)(14454004)(86362001)(6116002)(19627235001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1243; H:DM5PR12MB1243.namprd12.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 14 Oct 2017 16:08:17.0066 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1243 Subject: Re: [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 systems. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Oct 2017 16:04:45 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Yao, Jiewen [mailto:jiewen.yao@intel.com] > Sent: Thursday, October 12, 2017 9:37 PM > To: Duran, Leo ; edk2-devel@lists.01.org > Subject: RE: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based > x86 systems. > Hi Leo > I just have another thought, when I review code again. > > Do we *have to* make AMD SMM PSD offset to 0xfc00? > SMM PSD is just a *software* concept. Not hardware requirement. > What is broken, if we design AMD SMM PSD offset to be 0xfb00, (same as ex= isting code)? > HI Yao, I will look further into this to see if it's possible to re-use the same of= fset without too much pain. Thanks, Leo. > Thank you > Yao Jiewen > -----Original Message----- > From: Yao, Jiewen [mailto:jiewen.yao@intel.com] > Sent: Thursday, October 12, 2017 8:53 PM > To: Duran, Leo ; edk2-devel@lists.01.org > Subject: RE: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based > x86 systems. >=20 > HI Leo > Thank you very much. This patch looks good to me in general. >=20 > Some minor comment: >=20 > 1) For AMD smm save state. > I saw Paolo gave the comment on how to detect AMD save state. I do not > have strong opinion on that. I think you and Paolo can make decision. >=20 > I recommend we move AMD_SMRAM_SAVE_STATE_MAP_OFFSET to > UefiCpuPkg\Include\Register\Amd\SmramSaveStateMap.h, because it is > standard. > +// > +// Definitions for AMD systems are based on contents of the // AMD64 > +Architecture Programmer's Manual // Volume 2: System Programming, > +Section 10 System-Management Mode // #define > +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00 >=20 > We can leave AMD_SMM_PSD_OFFSET in UefiCpuPkg/PiSmmCpuDxeSmm, > if it is implementation specific. > +#define AMD_SMM_PSD_OFFSET 0xfc00 >=20 >=20 >=20 > 2) For Intel save state, I assume you already did some test to make sure > there is no regression. > If so, would you please add some description on what test you have done? > For example, > If both IA32 and X64 are validated? > If all three .S, .asm, .nasm are validated? > If OS boot and S3 resume are validated? >=20 > If you did any other test, please also add. >=20 > Thank you > Yao Jiewen >=20 >=20 > > -----Original Message----- > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > > Leo Duran > > Sent: Thursday, October 12, 2017 3:45 AM > > To: edk2-devel@lists.01.org > > Subject: [edk2] [PATCH v5 0/2] Enhanced SMM support for AMD-based x86 > > systems. > > > > This patch-set replaces Intel-specific macros with global variables to > > provide support for AMD-based x86 systems. > > > > The replaced macros are: > > 1) SRAM_SAVE_STATE_MAP_OFFSET > > 2) TXT_SMM_PSD_OFFSET > > 3) SMM_PSD_OFFSET > > > > Changes since v4: > > Make runtime CPUID checks and use global variables instead of PCD's. > > > > Changes since v3: > > Correction on cover letter. > > > > Changes since v2: > > The intent of this revision is to maintain compatibility with existing > > packages. To that end, changes to OvmgfPkg and QuarkSocPkg are > reverted. > > Moreover, pertinent macros are replaced in the C code, rather than on > > header files that are shared globally. > > > > Changes since v1: > > Revision to Cc list for UefiCpuPkg. > > > > Leo Duran (2): > > UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros > > UefiCpuPkg/PiSmmCpuDxeSmm: Use global variables to replace macros > > > > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++--- > > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 ++++++--- > > .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 +++++++++---- > > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48 > > +++++++++++++++ > > .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59 > > +++++++++++++++--- > > .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 + > > .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 + > > UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 ++++++++++- > - > > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++--- > > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 ++++++--- > > .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 ++++++++++---- > > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c | 22 ++++--- > > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 28 ++++++--- > > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 21 +++++-- > > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 43 > > +++++++++---- > > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 72 > > ++++++++++++++++++++-- > > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 17 ++++- > > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 18 > +++--- > > UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c | 20 +++--- > > UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c | 22 ++++--- > > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 34 ++++++---- > > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 22 +++++-- > > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 45 > > ++++++++++---- > > 23 files changed, 547 insertions(+), 174 deletions(-) create mode > > 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h > > > > -- > > 2.7.4 > > > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel