From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0087.outbound.protection.outlook.com [104.47.33.87]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D920221CC535F for ; Thu, 6 Jul 2017 06:46:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=w0LaJ70aObRrzFLAWxUTZ9SmQCO9J6ZiFaXD8kC6kMQ=; b=f5bDL42hAapv+RWUwONEsOu6Bc3kESf0TP45zG6CxWIN4FkAl9vz6ozAFrYzYOjsSnyOpDNpWLGZhGTvLZblkIG8l28hTRdTRD5nHMczCBkOPowCLcoVM5rCP/9wxV6bfNDM7suNxnjrogTQny5pjtjlHJSV+55Kes/EjtkRhbs= Received: from DM5PR12MB1243.namprd12.prod.outlook.com (10.168.237.22) by DM5PR12MB1243.namprd12.prod.outlook.com (10.168.237.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1220.11; Thu, 6 Jul 2017 13:48:10 +0000 Received: from DM5PR12MB1243.namprd12.prod.outlook.com ([10.168.237.22]) by DM5PR12MB1243.namprd12.prod.outlook.com ([10.168.237.22]) with mapi id 15.01.1220.018; Thu, 6 Jul 2017 13:48:10 +0000 From: "Duran, Leo" To: "'Ni, Ruiyu'" , "Fan, Jeff" , "edk2-devel@lists.01.org" CC: "Justen, Jordan L" , "Dong, Eric" , "Gao, Liming" Thread-Topic: [PATCH v2] UefiCpuPkg: ApicLib Thread-Index: AQHS8ru32kOeEZ8nV0SUaK/jrq5WoaI/keQAgAZ2uACAAAdIAIAAx3pA Date: Thu, 6 Jul 2017 13:48:10 +0000 Message-ID: References: <1498949104-11986-1-git-send-email-leo.duran@amd.com> <1498949104-11986-2-git-send-email-leo.duran@amd.com> <542CF652F8836A4AB8DBFAAD40ED192A4C6207FF@shsmsx102.ccr.corp.intel.com> <734D49CCEBEEF84792F5B80ED585239D5B9B06D6@SHSMSX104.ccr.corp.intel.com> In-Reply-To: <734D49CCEBEEF84792F5B80ED585239D5B9B06D6@SHSMSX104.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=amd.com; x-originating-ip: [165.204.77.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; DM5PR12MB1243; 20:Vk3rc5QQnolKEZMCRVppbUSNXgvNvYPire0+W/JGiZg3o+3momLxR/Ifm3m/hpSPs76FqL8W8ONNL9E6TJqjGLxrD5P7DRYPWO3PT7nqRbD7ztD6Ltlvj4qHdFZYAHVGXiygC/zIuGWvnMnMRwZw90qEUKJ0YNapLISeucemhRwXZhYvNHa9MnadULVZoPFdp32bsRzK7HUzC+J2xTrDZOAK2OHty/h6Jznz1fh5bFi1XCkUEO9roS1ci14oyHCA x-ms-office365-filtering-correlation-id: 4bdb493d-3fab-49cb-c668-08d4c475a3c7 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254075)(48565401081)(300000503095)(300135400095)(2017052603031)(201703131423075)(201703031133081)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095); SRVR:DM5PR12MB1243; x-ms-traffictypediagnostic: DM5PR12MB1243: x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(20558992708506)(236129657087228)(767451399110)(162533806227266)(228905959029699)(247924648384137); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(8121501046)(5005006)(100000703101)(100105400095)(93006095)(93001095)(10201501046)(3002001)(6055026)(6041248)(20161123555025)(20161123560025)(20161123564025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123558100)(6072148)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:DM5PR12MB1243; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:DM5PR12MB1243; x-forefront-prvs: 03607C04F0 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(39400400002)(39850400002)(39450400003)(39410400002)(39860400002)(39840400002)(377454003)(7736002)(55016002)(33656002)(53936002)(54906002)(74316002)(9686003)(2950100002)(2906002)(86362001)(2501003)(3660700001)(5660300001)(7696004)(25786009)(53946003)(6306002)(6436002)(189998001)(99286003)(54356999)(4326008)(2900100001)(3280700002)(93886004)(3846002)(102836003)(38730400002)(6246003)(966005)(53546010)(6506006)(77096006)(76176999)(81166006)(8676002)(478600001)(14454004)(229853002)(8936002)(66066001)(50986999)(6116002)(305945005)(19627235001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1243; H:DM5PR12MB1243.namprd12.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Jul 2017 13:48:10.1506 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1243 Subject: Re: [PATCH v2] UefiCpuPkg: ApicLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Jul 2017 13:46:32 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Ray, > -----Original Message----- > From: Ni, Ruiyu [mailto:ruiyu.ni@intel.com] > Sent: Wednesday, July 05, 2017 8:54 PM > To: Fan, Jeff ; Duran, Leo ; > edk2-devel@lists.01.org > Cc: Justen, Jordan L ; Dong, Eric > ; Gao, Liming > Subject: RE: [PATCH v2] UefiCpuPkg: ApicLib >=20 > Leo, > Could you please separate the clean-up code into a separate patch? >=20 [Duran, Leo]=20 Sure thing, I will submit separate patches. > Thanks/Ray >=20 > > -----Original Message----- > > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > > Fan, Jeff > > Sent: Thursday, July 6, 2017 9:28 AM > > To: Leo Duran ; edk2-devel@lists.01.org > > Cc: Justen, Jordan L ; Dong, Eric > > ; Gao, Liming > > Subject: Re: [edk2] [PATCH v2] UefiCpuPkg: ApicLib > > > > Leo, > > > > How AMD public spec dos define the manner of sending startup IPI to Aps= ? > > Which chapter is it defined in AMD public spec? > > > > Does AMD public spec indicate the second startup IPI is not required? > > > > Thanks! > > Jeff > > > > -----Original Message----- > > From: Leo Duran [mailto:leo.duran@amd.com] > > Sent: Sunday, July 02, 2017 6:45 AM > > To: edk2-devel@lists.01.org > > Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh > > Subject: [PATCH v2] UefiCpuPkg: ApicLib > > > > 1) SendInitSipiSipi () > > Skip repeating SendIpi () on AMD processor. > > > > 2) SendInitSipiSipiAllExcludingSelf () Skip repeating SendIpi () on > > AMD processor. > > > > 3) GetProcessorLocationByApicId () > > Adjust InitialApicId to properly concatenate Package on AMD processor. > > Clean-ups on C Coding standards. > > > > Cc: Jordan Justen > > Cc: Jeff Fan > > Cc: Liming Gao > > Cc: Brijesh Singh > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Signed-off-by: Leo Duran > > --- > > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 52 +++++++++++++- > --- > > ----- > > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 50 +++++++++++++-= ---- > -- > > - > > 2 files changed, 63 insertions(+), 39 deletions(-) > > > > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > index 2091e5e..a6e4e2e 100644 > > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > @@ -338,7 +338,7 @@ GetInitialApicId ( > > AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > > > > // > > - // If CPUID Leaf B is supported, > > + // If CPUID Leaf B is supported, > > // And CPUID.0BH:EBX[15:0] reports a non-zero value, > > // Then the initial 32-bit APIC ID =3D CPUID.0BH:EDX > > // Else the initial 8-bit APIC ID =3D CPUID.1:EBX[31:24] @@ -554,8 > > +554,10 @@ SendInitSipiSipi ( > > IcrLow.Bits.DeliveryMode =3D LOCAL_APIC_DELIVERY_MODE_STARTUP; > > IcrLow.Bits.Level =3D 1; > > SendIpi (IcrLow.Uint32, ApicId); > > - MicroSecondDelay (200); > > - SendIpi (IcrLow.Uint32, ApicId); > > + if (!StandardSignatureIsAuthenticAMD ()) { > > + MicroSecondDelay (200); > > + SendIpi (IcrLow.Uint32, ApicId); > > + } > > } > > > > /** > > @@ -588,8 +590,10 @@ SendInitSipiSipiAllExcludingSelf ( > > IcrLow.Bits.Level =3D 1; > > IcrLow.Bits.DestinationShorthand =3D > > LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; > > SendIpi (IcrLow.Uint32, 0); > > - MicroSecondDelay (200); > > - SendIpi (IcrLow.Uint32, 0); > > + if (!StandardSignatureIsAuthenticAMD ()) { > > + MicroSecondDelay (200); > > + SendIpi (IcrLow.Uint32, 0); > > + } > > } > > > > /** > > @@ -1013,13 +1017,14 @@ GetProcessorLocationByApicId ( > > UINT32 MaxCoresPerNode; > > UINT32 CorePerNodeMask; > > UINT32 ApicIdShift; > > + UINT32 ApicIdMask; > > UINTN ThreadBits; > > UINTN CoreBits; > > > > // > > // Check if the processor is capable of supporting more than one > > logical processor. > > // > > - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > > &VersionInfoEdx.Uint32); > > + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, > > + &VersionInfoEdx.Uint32); > > if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > if (Thread !=3D NULL) { > > *Thread =3D 0; > > @@ -1042,8 +1047,8 @@ GetProcessorLocationByApicId ( > > // > > // Get max index of CPUID > > // > > - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > > NULL); > > - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > NULL, > > NULL, NULL); > > + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > > NULL); > > + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > > NULL, NULL, > > + NULL); > > > > // > > // If the extended topology enumeration leaf is available, it @@ > > -1051,7 > > +1056,7 @@ GetProcessorLocationByApicId ( > > // > > TopologyLeafSupported =3D FALSE; > > if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > - AsmCpuidEx( > > + AsmCpuidEx ( > > CPUID_EXTENDED_TOPOLOGY, > > 0, > > &ExtendedTopologyEax.Uint32, > > @@ -1072,7 +1077,7 @@ GetProcessorLocationByApicId ( > > // the SMT sub-field of x2APIC ID. > > // > > LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > - ASSERT(LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > + ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > > > > // > > @@ -1081,7 +1086,7 @@ GetProcessorLocationByApicId ( > > // > > SubIndex =3D 1; > > do { > > - AsmCpuidEx( > > + AsmCpuidEx ( > > CPUID_EXTENDED_TOPOLOGY, > > SubIndex, > > &ExtendedTopologyEax.Uint32, @@ -1103,7 +1108,7 @@ > > GetProcessorLocationByApicId ( > > // > > // Get logical processor count > > // > > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, > NULL, > > NULL); > > + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, > NULL, > > + NULL); > > MaxLogicProcessorsPerPackage =3D > > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > > > // > > @@ -1114,11 +1119,11 @@ GetProcessorLocationByApicId ( > > // > > // Check for topology extensions on AMD processor > > // > > - if (StandardSignatureIsAuthenticAMD()) { > > + if (StandardSignatureIsAuthenticAMD ()) { > > if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) > { > > - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, > > &AmdExtendedCpuSigEcx.Uint32, NULL); > > + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, > > + &AmdExtendedCpuSigEcx.Uint32, NULL); > > if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { > > - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > > &AmdProcessorTopologyEbx.Uint32, > > + AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > > + &AmdProcessorTopologyEbx.Uint32, > > &AmdProcessorTopologyEcx.Uint32, NULL); > > // > > // Get cores per processor package @@ -1128,7 +1133,7 @@ > > GetProcessorLocationByApicId ( > > // > > // Account for actual thread count (e.g., SMT disabled) > > // > > - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > > &AmdVirPhyAddressSizeEcx.Uint32, NULL); > > + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > > + &AmdVirPhyAddressSizeEcx.Uint32, NULL); > > MaxThreadPerPackageMask =3D 1 << > > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; > > ActualThreadPerPackageMask =3D 1; > > while (ActualThreadPerPackageMask < > > MaxLogicProcessorsPerPackage) { @@ -1136,7 +1141,7 @@ > GetProcessorLocationByApicId ( > > } > > > > // > > - // Adjust APIC Id to report concatenation of Package|Core|Th= read. > > + // Adjust APIC Id to report concatenation of Core|Thread. > > // > > if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { > > MaxCoresPerNode =3D MaxCoresPerPackage / > > (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); @@ -1148,13 > > +1153,20 @@ GetProcessorLocationByApicId ( > > CorePerNodeMask -=3D 1; > > > > ApicIdShift =3D 0; > > + ApicIdMask =3D ActualThreadPerPackageMask; > > do { > > ApicIdShift +=3D 1; > > - ActualThreadPerPackageMask <<=3D 1; > > - } while (ActualThreadPerPackageMask < > MaxThreadPerPackageMask); > > + ApicIdMask <<=3D 1; > > + } while (ApicIdMask < MaxThreadPerPackageMask); > > > > InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> > > ApicIdShift) | (InitialApicId & CorePerNodeMask); > > } > > + // > > + // Adjust APIC Id to report concatenation of Package|Core|Th= read. > > + // > > + if ((InitialApicId & ~(MaxThreadPerPackageMask - 1)) !=3D 0)= { > > + InitialApicId =3D (InitialApicId & > > + (ActualThreadPerPackageMask - 1)) | > > ActualThreadPerPackageMask; > > + } > > } > > } > > } > > @@ -1163,7 +1175,7 @@ GetProcessorLocationByApicId ( > > // Extract core count based on CACHE information > > // > > if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > > NULL, NULL, NULL); > > + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > > + NULL, NULL, NULL); > > if (CacheParamsEax.Uint32 !=3D 0) { > > MaxCoresPerPackage =3D > > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > } > > diff --git > > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > index d5d4efa..5945b55 100644 > > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > @@ -649,8 +649,10 @@ SendInitSipiSipi ( > > IcrLow.Bits.DeliveryMode =3D LOCAL_APIC_DELIVERY_MODE_STARTUP; > > IcrLow.Bits.Level =3D 1; > > SendIpi (IcrLow.Uint32, ApicId); > > - MicroSecondDelay (200); > > - SendIpi (IcrLow.Uint32, ApicId); > > + if (!StandardSignatureIsAuthenticAMD ()) { > > + MicroSecondDelay (200); > > + SendIpi (IcrLow.Uint32, ApicId); > > + } > > } > > > > /** > > @@ -683,8 +685,10 @@ SendInitSipiSipiAllExcludingSelf ( > > IcrLow.Bits.Level =3D 1; > > IcrLow.Bits.DestinationShorthand =3D > > LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF; > > SendIpi (IcrLow.Uint32, 0); > > - MicroSecondDelay (200); > > - SendIpi (IcrLow.Uint32, 0); > > + if (!StandardSignatureIsAuthenticAMD ()) { > > + MicroSecondDelay (200); > > + SendIpi (IcrLow.Uint32, 0); > > + } > > } > > > > /** > > @@ -1108,13 +1112,14 @@ GetProcessorLocationByApicId ( > > UINT32 MaxCoresPerNode; > > UINT32 CorePerNodeMask; > > UINT32 ApicIdShift; > > + UINT32 ApicIdMask; > > UINTN ThreadBits; > > UINTN CoreBits; > > > > // > > // Check if the processor is capable of supporting more than one > > logical processor. > > // > > - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > > &VersionInfoEdx.Uint32); > > + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, > > + &VersionInfoEdx.Uint32); > > if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > if (Thread !=3D NULL) { > > *Thread =3D 0; > > @@ -1137,8 +1142,8 @@ GetProcessorLocationByApicId ( > > // > > // Get max index of CPUID > > // > > - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > > NULL); > > - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > NULL, > > NULL, NULL); > > + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > > NULL); > > + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > > NULL, NULL, > > + NULL); > > > > // > > // If the extended topology enumeration leaf is available, it @@ > > -1146,7 > > +1151,7 @@ GetProcessorLocationByApicId ( > > // > > TopologyLeafSupported =3D FALSE; > > if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > - AsmCpuidEx( > > + AsmCpuidEx ( > > CPUID_EXTENDED_TOPOLOGY, > > 0, > > &ExtendedTopologyEax.Uint32, > > @@ -1167,7 +1172,7 @@ GetProcessorLocationByApicId ( > > // the SMT sub-field of x2APIC ID. > > // > > LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > - ASSERT(LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > + ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > > > > // > > @@ -1176,7 +1181,7 @@ GetProcessorLocationByApicId ( > > // > > SubIndex =3D 1; > > do { > > - AsmCpuidEx( > > + AsmCpuidEx ( > > CPUID_EXTENDED_TOPOLOGY, > > SubIndex, > > &ExtendedTopologyEax.Uint32, @@ -1198,7 +1203,7 @@ > > GetProcessorLocationByApicId ( > > // > > // Get logical processor count > > // > > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, > NULL, > > NULL); > > + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, > NULL, > > + NULL); > > MaxLogicProcessorsPerPackage =3D > > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > > > // > > @@ -1209,11 +1214,11 @@ GetProcessorLocationByApicId ( > > // > > // Check for topology extensions on AMD processor > > // > > - if (StandardSignatureIsAuthenticAMD()) { > > + if (StandardSignatureIsAuthenticAMD ()) { > > if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) > { > > - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, > > &AmdExtendedCpuSigEcx.Uint32, NULL); > > + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, > > + &AmdExtendedCpuSigEcx.Uint32, NULL); > > if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { > > - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > > &AmdProcessorTopologyEbx.Uint32, > > + AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > > + &AmdProcessorTopologyEbx.Uint32, > > &AmdProcessorTopologyEcx.Uint32, NULL); > > // > > // Get cores per processor package @@ -1223,7 +1228,7 @@ > > GetProcessorLocationByApicId ( > > // > > // Account for actual thread count (e.g., SMT disabled) > > // > > - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > > &AmdVirPhyAddressSizeEcx.Uint32, NULL); > > + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > > + &AmdVirPhyAddressSizeEcx.Uint32, NULL); > > MaxThreadPerPackageMask =3D 1 << > > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; > > ActualThreadPerPackageMask =3D 1; > > while (ActualThreadPerPackageMask < > > MaxLogicProcessorsPerPackage) { @@ -1231,7 +1236,7 @@ > GetProcessorLocationByApicId ( > > } > > > > // > > - // Adjust APIC Id to report concatenation of Package|Core|Th= read. > > + // Adjust APIC Id to report concatenation of Core|Thread. > > // > > if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { > > MaxCoresPerNode =3D MaxCoresPerPackage / > > (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); @@ -1243,13 > > +1248,20 @@ GetProcessorLocationByApicId ( > > CorePerNodeMask -=3D 1; > > > > ApicIdShift =3D 0; > > + ApicIdMask =3D ActualThreadPerPackageMask; > > do { > > ApicIdShift +=3D 1; > > - ActualThreadPerPackageMask <<=3D 1; > > - } while (ActualThreadPerPackageMask < > MaxThreadPerPackageMask); > > + ApicIdMask <<=3D 1; > > + } while (ApicIdMask < MaxThreadPerPackageMask); > > > > InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> > > ApicIdShift) | (InitialApicId & CorePerNodeMask); > > } > > + // > > + // Adjust APIC Id to report concatenation of Package|Core|Th= read. > > + // > > + if ((InitialApicId & ~(MaxThreadPerPackageMask - 1)) !=3D 0)= { > > + InitialApicId =3D (InitialApicId & > > + (ActualThreadPerPackageMask - 1)) | > > ActualThreadPerPackageMask; > > + } > > } > > } > > } > > @@ -1258,7 +1270,7 @@ GetProcessorLocationByApicId ( > > // Extract core count based on CACHE information > > // > > if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > > NULL, NULL, NULL); > > + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > > + NULL, NULL, NULL); > > if (CacheParamsEax.Uint32 !=3D 0) { > > MaxCoresPerPackage =3D > > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > } > > -- > > 2.7.4 > > > > _______________________________________________ > > edk2-devel mailing list > > edk2-devel@lists.01.org > > https://lists.01.org/mailman/listinfo/edk2-devel