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spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Jul 2017 18:08:54.2350 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1241 Subject: Re: [PATCH v3] UefiCpuPkg: ApicLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Jul 2017 18:07:15 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Mike, > -----Original Message----- > From: Kinney, Michael D [mailto:michael.d.kinney@intel.com] > Sent: Thursday, July 06, 2017 11:36 AM > To: Duran, Leo ; edk2-devel@lists.01.org; Kinney, > Michael D > Cc: Justen, Jordan L ; Fan, Jeff > ; Gao, Liming > Subject: RE: [edk2] [PATCH v3] UefiCpuPkg: ApicLib >=20 > Hi Leo, >=20 > Some of the change here do not follow the coding standard. For function > calls with many arguments, either put the function call on a single line,= or > break it up with each arg on its own line. >=20 [Duran, Leo]=20 Yes, I do see a malformed AsmCpuId() function call... Somehow that was miss= ed in the original submission that's already upstream. Anyway, good catch!... I'll fix it. Thanks. > This was clarified in the latest version of the EDK II C Coding Standard. >=20 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D425 > https://github.com/tianocore-docs/edk2- > CCodingStandardsSpecification/commit/3f1100beda60843361a9761b43ba7b1 > 8adf0d265 >=20 > Mike >=20 >=20 > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Leo Duran > Sent: Thursday, July 6, 2017 7:48 AM > To: edk2-devel@lists.01.org > Cc: Justen, Jordan L ; Leo Duran > ; Fan, Jeff ; Gao, Liming > > Subject: [edk2] [PATCH v3] UefiCpuPkg: ApicLib >=20 > GetProcessorLocationByApicId () > - Adjust InitialApicId to properly concatenate Package on AMD processor. > - Clean-ups on C Coding standards. >=20 > Cc: Jordan Justen > Cc: Jeff Fan > Cc: Liming Gao > Cc: Brijesh Singh > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Leo Duran > --- > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 42 +++++++++++++---= - > ----- > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 40 ++++++++++++----= ---- > - > 2 files changed, 49 insertions(+), 33 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > index 2091e5e..ce6d9d7 100644 > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > @@ -48,7 +48,7 @@ StandardSignatureIsAuthenticAMD ( > UINT32 RegEcx; > UINT32 RegEdx; >=20 > - AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); > + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); > return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && > RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && > RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); > @@ -338,7 +338,7 @@ GetInitialApicId ( > AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); >=20 > // > - // If CPUID Leaf B is supported, > + // If CPUID Leaf B is supported, > // And CPUID.0BH:EBX[15:0] reports a non-zero value, > // Then the initial 32-bit APIC ID =3D CPUID.0BH:EDX > // Else the initial 8-bit APIC ID =3D CPUID.1:EBX[31:24] @@ -1013,13 += 1013,14 > @@ GetProcessorLocationByApicId ( > UINT32 MaxCoresPerNode; > UINT32 CorePerNodeMask; > UINT32 ApicIdShift; > + UINT32 ApicIdMask; > UINTN ThreadBits; > UINTN CoreBits; >=20 > // > // Check if the processor is capable of supporting more than one logic= al > processor. > // > - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, > + &VersionInfoEdx.Uint32); > if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > if (Thread !=3D NULL) { > *Thread =3D 0; > @@ -1042,8 +1043,8 @@ GetProcessorLocationByApicId ( > // > // Get max index of CPUID > // > - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > NULL); > - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > NULL, NULL, NULL); > + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > NULL); > + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > NULL, NULL, > + NULL); >=20 > // > // If the extended topology enumeration leaf is available, it @@ -1051= ,7 > +1052,7 @@ GetProcessorLocationByApicId ( > // > TopologyLeafSupported =3D FALSE; > if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > - AsmCpuidEx( > + AsmCpuidEx ( > CPUID_EXTENDED_TOPOLOGY, > 0, > &ExtendedTopologyEax.Uint32, > @@ -1072,7 +1073,7 @@ GetProcessorLocationByApicId ( > // the SMT sub-field of x2APIC ID. > // > LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > - ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > + ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; >=20 > // > @@ -1081,7 +1082,7 @@ GetProcessorLocationByApicId ( > // > SubIndex =3D 1; > do { > - AsmCpuidEx( > + AsmCpuidEx ( > CPUID_EXTENDED_TOPOLOGY, > SubIndex, > &ExtendedTopologyEax.Uint32, > @@ -1103,7 +1104,7 @@ GetProcessorLocationByApicId ( > // > // Get logical processor count > // > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > NULL); > + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > + NULL); > MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; >=20 > // > @@ -1114,11 +1115,11 @@ GetProcessorLocationByApicId ( > // > // Check for topology extensions on AMD processor > // > - if (StandardSignatureIsAuthenticAMD()) { > + if (StandardSignatureIsAuthenticAMD ()) { > if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { > - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, > &AmdExtendedCpuSigEcx.Uint32, NULL); > + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, > + &AmdExtendedCpuSigEcx.Uint32, NULL); > if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { > - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > &AmdProcessorTopologyEbx.Uint32, > + AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > + &AmdProcessorTopologyEbx.Uint32, > &AmdProcessorTopologyEcx.Uint32, NULL); > // > // Get cores per processor package @@ -1128,7 +1129,7 @@ > GetProcessorLocationByApicId ( > // > // Account for actual thread count (e.g., SMT disabled) > // > - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > &AmdVirPhyAddressSizeEcx.Uint32, NULL); > + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > + &AmdVirPhyAddressSizeEcx.Uint32, NULL); > MaxThreadPerPackageMask =3D 1 << > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; > ActualThreadPerPackageMask =3D 1; > while (ActualThreadPerPackageMask < > MaxLogicProcessorsPerPackage) { @@ -1136,7 +1137,7 @@ > GetProcessorLocationByApicId ( > } >=20 > // > - // Adjust APIC Id to report concatenation of Package|Core|Thre= ad. > + // Adjust APIC Id to report concatenation of Core|Thread. > // > if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { > MaxCoresPerNode =3D MaxCoresPerPackage / > (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); @@ -1148,13 > +1149,20 @@ GetProcessorLocationByApicId ( > CorePerNodeMask -=3D 1; >=20 > ApicIdShift =3D 0; > + ApicIdMask =3D ActualThreadPerPackageMask; > do { > ApicIdShift +=3D 1; > - ActualThreadPerPackageMask <<=3D 1; > - } while (ActualThreadPerPackageMask < > MaxThreadPerPackageMask); > + ApicIdMask <<=3D 1; > + } while (ApicIdMask < MaxThreadPerPackageMask); >=20 > InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> Api= cIdShift) | > (InitialApicId & CorePerNodeMask); > } > + // > + // Adjust APIC Id to report concatenation of Package|Core|Thre= ad. > + // > + if ((InitialApicId & ~(MaxThreadPerPackageMask - 1)) !=3D 0) { > + InitialApicId =3D (InitialApicId & (ActualThreadPerPackageMa= sk - 1)) | > ActualThreadPerPackageMask; > + } > } > } > } > @@ -1163,7 +1171,7 @@ GetProcessorLocationByApicId ( > // Extract core count based on CACHE information > // > if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > + NULL, NULL, NULL); > if (CacheParamsEax.Uint32 !=3D 0) { > MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > } > diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > index d5d4efa..54ea492 100644 > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > @@ -49,7 +49,7 @@ StandardSignatureIsAuthenticAMD ( > UINT32 RegEcx; > UINT32 RegEdx; >=20 > - AsmCpuid(CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); > + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); > return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && > RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && > RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); > @@ -1108,13 +1108,14 @@ GetProcessorLocationByApicId ( > UINT32 MaxCoresPerNode; > UINT32 CorePerNodeMask; > UINT32 ApicIdShift; > + UINT32 ApicIdMask; > UINTN ThreadBits; > UINTN CoreBits; >=20 > // > // Check if the processor is capable of supporting more than one logic= al > processor. > // > - AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, > + &VersionInfoEdx.Uint32); > if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > if (Thread !=3D NULL) { > *Thread =3D 0; > @@ -1137,8 +1138,8 @@ GetProcessorLocationByApicId ( > // > // Get max index of CPUID > // > - AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > NULL); > - AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > NULL, NULL, NULL); > + AsmCpuid (CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > NULL); > + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > NULL, NULL, > + NULL); >=20 > // > // If the extended topology enumeration leaf is available, it @@ -1146= ,7 > +1147,7 @@ GetProcessorLocationByApicId ( > // > TopologyLeafSupported =3D FALSE; > if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > - AsmCpuidEx( > + AsmCpuidEx ( > CPUID_EXTENDED_TOPOLOGY, > 0, > &ExtendedTopologyEax.Uint32, > @@ -1167,7 +1168,7 @@ GetProcessorLocationByApicId ( > // the SMT sub-field of x2APIC ID. > // > LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > - ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > + ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; >=20 > // > @@ -1176,7 +1177,7 @@ GetProcessorLocationByApicId ( > // > SubIndex =3D 1; > do { > - AsmCpuidEx( > + AsmCpuidEx ( > CPUID_EXTENDED_TOPOLOGY, > SubIndex, > &ExtendedTopologyEax.Uint32, > @@ -1198,7 +1199,7 @@ GetProcessorLocationByApicId ( > // > // Get logical processor count > // > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > NULL); > + AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > + NULL); > MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; >=20 > // > @@ -1209,11 +1210,11 @@ GetProcessorLocationByApicId ( > // > // Check for topology extensions on AMD processor > // > - if (StandardSignatureIsAuthenticAMD()) { > + if (StandardSignatureIsAuthenticAMD ()) { > if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { > - AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, > &AmdExtendedCpuSigEcx.Uint32, NULL); > + AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, > + &AmdExtendedCpuSigEcx.Uint32, NULL); > if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { > - AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > &AmdProcessorTopologyEbx.Uint32, > + AsmCpuid (CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > + &AmdProcessorTopologyEbx.Uint32, > &AmdProcessorTopologyEcx.Uint32, NULL); > // > // Get cores per processor package @@ -1223,7 +1224,7 @@ > GetProcessorLocationByApicId ( > // > // Account for actual thread count (e.g., SMT disabled) > // > - AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > &AmdVirPhyAddressSizeEcx.Uint32, NULL); > + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > + &AmdVirPhyAddressSizeEcx.Uint32, NULL); > MaxThreadPerPackageMask =3D 1 << > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; > ActualThreadPerPackageMask =3D 1; > while (ActualThreadPerPackageMask < > MaxLogicProcessorsPerPackage) { @@ -1231,7 +1232,7 @@ > GetProcessorLocationByApicId ( > } >=20 > // > - // Adjust APIC Id to report concatenation of Package|Core|Thre= ad. > + // Adjust APIC Id to report concatenation of Core|Thread. > // > if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { > MaxCoresPerNode =3D MaxCoresPerPackage / > (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); @@ -1243,13 > +1244,20 @@ GetProcessorLocationByApicId ( > CorePerNodeMask -=3D 1; >=20 > ApicIdShift =3D 0; > + ApicIdMask =3D ActualThreadPerPackageMask; > do { > ApicIdShift +=3D 1; > - ActualThreadPerPackageMask <<=3D 1; > - } while (ActualThreadPerPackageMask < > MaxThreadPerPackageMask); > + ApicIdMask <<=3D 1; > + } while (ApicIdMask < MaxThreadPerPackageMask); >=20 > InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> Api= cIdShift) | > (InitialApicId & CorePerNodeMask); > } > + // > + // Adjust APIC Id to report concatenation of Package|Core|Thre= ad. > + // > + if ((InitialApicId & ~(MaxThreadPerPackageMask - 1)) !=3D 0) { > + InitialApicId =3D (InitialApicId & (ActualThreadPerPackageMa= sk - 1)) | > ActualThreadPerPackageMask; > + } > } > } > } > @@ -1258,7 +1266,7 @@ GetProcessorLocationByApicId ( > // Extract core count based on CACHE information > // > if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > + NULL, NULL, NULL); > if (CacheParamsEax.Uint32 !=3D 0) { > MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > } > -- > 2.7.4 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel