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Thread-Index: AQHSwO/C7MxdwjPBX0OTPcF/W8YHhaHhYzaA Date: Tue, 2 May 2017 18:41:39 +0000 Message-ID: References: <1493473882-7336-1-git-send-email-jiewen.yao@intel.com> In-Reply-To: <1493473882-7336-1-git-send-email-jiewen.yao@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=amd.com; x-originating-ip: [165.204.77.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; BY2PR12MB0148; 7:gWjtjVA4QuVmo6PeuMBnphX7D+o43wuSX4xt7m4cFg3lHLUArTfMDp4K5OMMIPr4oHIH2DIzLBvEksyxKFWV7D6B3LRT1pbsYfKo8Rnj/PPH2KYlv0fZm9XLxWSEMnT7lLe7bBzIi88XbeA5PjNZosmaTULksrP0Nv6lIXaIuN9hYJmbq13vt1UXMUmxguWrsa5KvQ5iJWLH/uWTMU6fnnvuZO4HqQ4aAHF+O/PXqsoX2ATw3+I5o9dpumIyCwFZg6kQBxxUzUdL/9IpH9vLqsjIboqC6oQ3E03kCmeZI1XdH0Ph85MJCD7klQcOEr5IWzYyC52HB0CFySlnTxb18w==; 20:VWvk1o6B30E1Y1bjnh2QtGOYplRBdyvEbGve8WYcwRMyFGpMiaGX3pwMlwjmp5E6A/xnOs/KMuEDFlL98j9Otcvp/fVBMQUIxYCA3PsLDk3+bECF/lNYZpd4ldCn1NBq8Aj90N438U2WT1N6+ZJ8+hNETnZJZi6FA7+JX+pyqW5+r07RzoXXr/X4O+WMIn1+HyDxXfrNMZmOyga0vvMW4y8BdDFkvPiVCOp8Y0+38WKXtGIdAb25OGlRG7n3DDaG x-forefront-antispam-report: SFV:SKI; SCL:-1SFV:NSPM; SFS:(10009020)(6009001)(39400400002)(39860400002)(39410400002)(39850400002)(39450400003)(39840400002)(13464003)(377454003)(38730400002)(54356999)(2906002)(25786009)(53546009)(508600001)(4326008)(76176999)(54906002)(6306002)(55016002)(229853002)(189998001)(122556002)(7696004)(2950100002)(3280700002)(8936002)(9686003)(99286003)(77096006)(6436002)(6246003)(66066001)(6506006)(6116002)(3846002)(102836003)(50986999)(81166006)(8676002)(53936002)(86362001)(74316002)(5660300001)(7736002)(2900100001)(305945005)(2501003)(3660700001); DIR:OUT; SFP:1101; SCL:1; SRVR:BY2PR12MB0148; H:DM5PR12MB1243.namprd12.prod.outlook.com; FPR:; SPF:None; MLV:sfv; LANG:en; x-ms-office365-filtering-correlation-id: 698c0ebb-cb3d-495d-302d-08d4918adefd x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081); SRVR:BY2PR12MB0148; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(166708455590820)(767451399110)(162533806227266)(228905959029699); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040450)(601004)(2401047)(8121501046)(5005006)(93006095)(93001095)(10201501046)(3002001)(6055026)(6041248)(20161123562025)(201703131423075)(201702281528075)(201703061421075)(20161123564025)(20161123560025)(20161123555025)(6072148); SRVR:BY2PR12MB0148; BCL:0; PCL:0; RULEID:; SRVR:BY2PR12MB0148; x-forefront-prvs: 02951C14DC spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 02 May 2017 18:41:39.7100 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY2PR12MB0148 Subject: Re: [RFC] [PATCH V4 0/3] Add IOMMU support. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 May 2017 18:41:42 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Yao, Would it make sense to have a default protocol producer driver that provide= s pass-thru functionality? This way consumers of the protocol may add a dependency on it, ensuring tha= t the protocol provider always run first. (In the SEV sample driver we run first because we added the driver to the A= PRIORI list, but it seems like a Depex would be more elegant) Leo. > -----Original Message----- > From: Jiewen Yao [mailto:jiewen.yao@intel.com] > Sent: Saturday, April 29, 2017 8:51 AM > To: edk2-devel@lists.01.org > Cc: Ruiyu Ni ; Duran, Leo ; > Singh, Brijesh ; Ard Biesheuvel > > Subject: [RFC] [PATCH V4 0/3] Add IOMMU support. >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V4 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > Refine the EDKII_IOMMU_PROTOCOL. >=20 > 1) Add AllocateBuffer/FreeBuffer/Map/Unmap() API. > They are similar to DmaLib in EmbeddedPkg and similar to the previous > BmDmaLib (by leo.duran@amd.com). >=20 > These APIs are invoked by PciHostBridge driver to allocate DMA memory. >=20 > The PciHostBridge driver (IOMMU consumer) is simplified: > It uses IOMMU, if IOMMU protocol is present. > Else it uses original logic. >=20 > 2) Add SetMappingAttribute() API. > It is similar to SetAttribute() API in V1. >=20 > This API is invoked by PciBus driver to set DMA access attribute (read/wr= ite) > for device. >=20 > The PciBus driver (IOMMU consumer) is simplified: > It sets access attribute in Map/Unmap, > if IOMMU protocol is present. >=20 > 3) Remove SetRemapAddress/GetRemapAddress() API. > Because PciHostBridge/PciBus can call the APIs defined above, there is no > need to provide remap capability. >=20 > -- Sample producer drivers: > 1) The sample VTd driver (IOMMU producer) is at > https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/IntelVTdDxe >=20 > It is added to show the concept. It is not fully implemented yet. > It will not be checked in in this patch. >=20 > 2) The sample AMD SEV driver (IOMMU producer) is at > https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleAmdSe > vDxe > (code is borrowed from leo.duran@amd.com and brijesh.singh@amd.com) >=20 > This is not a right place to put this driver. >=20 > It is added to show the concept. > It is not fully implemented. It will not be checked in. > Please do not use it directly. >=20 > 3) The sample STYX driver (IOMMU producer) is at > https://github.com/jyao1/edk2/tree/dma_v4/IntelSiliconPkg/SampleStyxDx > e > (code is borrowed from ard.biesheuvel@linaro.org) >=20 > This is not a right place to put this driver. >=20 > It is added to show the concept. > It is not fully implemented. It will not be checked in. > Please do not use it directly. >=20 >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V3 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > 1) Add Remap capability (from Ard Biesheuvel) Add > EDKII_IOMMU_REMAP_ADDRESS API in IOMMU_PROTOCOL. >=20 > NOTE: The code is not fully validated yet. > The purpose is to collect feedback to decide the next step. >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V2 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D > 1) Enhance Unmap() in PciIo (From Ruiyu Ni) Maintain a local list of MapI= nfo > and match it in Unmap. >=20 > 2) CopyMem for ReadOperation in PciIo after SetAttribute (Leo Duran) Fix = a > bug in V1 that copy mem for read happen before SetAttribute, which will > break AMD SEV solution. >=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D V1 =3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D >=20 > This patch series adds IOMMU protocol and updates the consumer to > support IOMMU based DMA access in UEFI. >=20 > This patch series can support the BmDmaLib request for AMD SEV. > submitted by Duran, Leo and Brijesh Singh > . > https://lists.01.org/pipermail/edk2-devel/2017-March/008109.html, and > https://lists.01.org/pipermail/edk2-devel/2017-March/008820.html. > We can have an AMD SEV specific IOMMU driver to produce IOMMU > protocol, and clear SEV in IOMMU->SetAttribute(). >=20 > This patch series can also support Intel VTd based DMA protection, > requested by Jiewen Yao , discussed in > https://lists.01.org/pipermail/edk2-devel/2017-March/008157.html. > We can have an Intel VTd specific IOMMU driver to produce IOMMU > protocol, and update VTd engine to grant or deny access in IOMMU- > >SetAttribute(). >=20 > This patch series does not provide a full Intel VTd driver, which will be > provide in other patch in the future. >=20 > The purpose of this patch series to review if this IOMMU protocol design = can > meet all DMA access and management requirement. >=20 > Cc: Ruiyu Ni > Cc: Leo Duran > Cc: Brijesh Singh > Cc: Ard Biesheuvel > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao >=20 > Jiewen Yao (3): > MdeModulePkg/Include: Add IOMMU protocol definition. > MdeModulePkg/PciHostBridge: Add IOMMU support. > MdeModulePkg/PciBus: Add IOMMU support. >=20 > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 9 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + > MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c | 37 +++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 37 +++ > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf | 2 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridge.h | 2 + > MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 61 ++++ > MdeModulePkg/Include/Protocol/IoMmu.h | 310 > ++++++++++++++++++++ > MdeModulePkg/MdeModulePkg.dec | 3 + > 10 files changed, 463 insertions(+) > create mode 100644 MdeModulePkg/Include/Protocol/IoMmu.h >=20 > -- > 2.7.4.windows.1