From: "Duran, Leo" <leo.duran@amd.com>
To: 'Laszlo Ersek' <lersek@redhat.com>,
"edk2-devel@ml01.01.org" <edk2-devel@ml01.01.org>
Cc: "liming.gao@intel.com" <liming.gao@intel.com>,
"jeff.fan@intel.com" <jeff.fan@intel.com>,
"michael.d.kinney@intel.com" <michael.d.kinney@intel.com>
Subject: Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
Date: Mon, 31 Oct 2016 21:26:02 +0000 [thread overview]
Message-ID: <DM5PR12MB1243902D51385E268568EDE7F9AE0@DM5PR12MB1243.namprd12.prod.outlook.com> (raw)
In-Reply-To: <5002454a-9db8-531f-2383-baacc9ea35b7@redhat.com>
> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Monday, October 31, 2016 4:24 PM
> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@ml01.01.org
> Cc: liming.gao@intel.com; jeff.fan@intel.com; michael.d.kinney@intel.com
> Subject: Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to
> LocalApicLib library
>
> On 10/31/16 20:42, Leo Duran wrote:
> > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
> > 2) Remove ExtractProcessorLocation() from MpInitLib library.
> > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Leo Duran <leo.duran@amd.com>
> > ---
> > UefiCpuPkg/Include/Library/LocalApicLib.h | 20 +++
> > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 146
> +++++++++++++++++++++
> > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 146
> +++++++++++++++++++++
> > UefiCpuPkg/Library/MpInitLib/MpLib.c | 133 +------------------
> > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 126 +-----------------
> > 5 files changed, 324 insertions(+), 247 deletions(-)
>
> (1) This patch should carry a "Signed-off-by" from Mike as well -- it is my
> understanding that this v4 patch is the result of joint work (it contains new
> code from two people).
>
> I don't think it's necessary to repost the patch for this: if Mike responds with
> his S-o-b, then I believe Jeff can simply add that tag as well at commit time.
>
[Duran, Leo]
Yes, please make that happen. Thanks.
> (2) I repeated my tests as described in
> <https://lists.01.org/pipermail/edk2-devel/2016-October/003807.html>;
> the v4 patch too works fine.
>
> Tested-by: Laszlo Ersek <lersek@redhat.com>
>
[Duran, Leo]
Great, thanks.
> Thanks
> Laszlo
>
> > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h
> > b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > index cd4e613..179409e 100644
> > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h
> > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > @@ -410,6 +410,26 @@ GetApicMsiValue (
> > IN BOOLEAN LevelTriggered,
> > IN BOOLEAN AssertionLevel
> > );
> > +
> > +/**
> > + Get Package ID/Core ID/Thread ID of a processor.
> > +
> > + The algorithm assumes the target system has symmetry across
> > + physical package boundaries with respect to the number of logical
> > + processors per package, number of cores per package.
> > +
> > + @param[in] InitialApicId Initial APIC ID of the target logical processor.
> > + @param[out] Package Returns the processor package ID.
> > + @param[out] Core Returns the processor core ID.
> > + @param[out] Thread Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > + IN UINT32 InitialApicId,
> > + OUT UINT32 *Package OPTIONAL,
> > + OUT UINT32 *Core OPTIONAL,
> > + OUT UINT32 *Thread OPTIONAL
> > + );
> >
> > #endif
> >
> > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > index 8d0fb02..f32d287 100644
> > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > @@ -941,3 +941,149 @@ GetApicMsiValue (
> > }
> > return MsiData.Uint64;
> > }
> > +
> > +/**
> > + Get Package ID/Core ID/Thread ID of a processor.
> > +
> > + The algorithm assumes the target system has symmetry across
> > + physical package boundaries with respect to the number of logical
> > + processors per package, number of cores per package.
> > +
> > + @param[in] InitialApicId Initial APIC ID of the target logical processor.
> > + @param[out] Package Returns the processor package ID.
> > + @param[out] Core Returns the processor core ID.
> > + @param[out] Thread Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > + IN UINT32 InitialApicId,
> > + OUT UINT32 *Package OPTIONAL,
> > + OUT UINT32 *Core OPTIONAL,
> > + OUT UINT32 *Thread OPTIONAL
> > + )
> > +{
> > + BOOLEAN TopologyLeafSupported;
> > + UINTN ThreadBits;
> > + UINTN CoreBits;
> > + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> > + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> > + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> > + UINT32 MaxCpuIdIndex;
> > + UINT32 SubIndex;
> > + UINTN LevelType;
> > + UINT32 MaxLogicProcessorsPerPackage;
> > + UINT32 MaxCoresPerPackage;
> > +
> > + //
> > + // Check if the processor is capable of supporting more than one logical
> processor.
> > + //
> > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> > + &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT == 0) {
> > + if (Thread != NULL) {
> > + *Thread = 0;
> > + }
> > + if (Core != NULL) {
> > + *Core = 0;
> > + }
> > + if (Package != NULL) {
> > + *Package = 0;
> > + }
> > + return;
> > + }
> > +
> > + ThreadBits = 0;
> > + CoreBits = 0;
> > +
> > + //
> > + // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > + //
> > + TopologyLeafSupported = FALSE;
> > +
> > + //
> > + // Get the max index of basic CPUID // AsmCpuid(CPUID_SIGNATURE,
> > + &MaxCpuIdIndex, NULL, NULL, NULL);
> > +
> > + //
> > + // If the extended topology enumeration leaf is available, it //
> > + is the preferred mechanism for enumerating topology.
> > + //
> > + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > + AsmCpuidEx(
> > + CPUID_EXTENDED_TOPOLOGY,
> > + 0,
> > + &ExtendedTopologyEax.Uint32,
> > + &ExtendedTopologyEbx.Uint32,
> > + &ExtendedTopologyEcx.Uint32,
> > + NULL
> > + );
> > + //
> > + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > + // supported on that processor.
> > + //
> > + if (ExtendedTopologyEbx.Uint32 != 0) {
> > + TopologyLeafSupported = TRUE;
> > +
> > + //
> > + // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > + // the SMT sub-field of x2APIC ID.
> > + //
> > + LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > + ASSERT(LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > + //
> > + // Software must not assume any "level type" encoding
> > + // value to be related to any sub-leaf index, except sub-leaf 0.
> > + //
> > + SubIndex = 1;
> > + do {
> > + AsmCpuidEx(
> > + CPUID_EXTENDED_TOPOLOGY,
> > + SubIndex,
> > + &ExtendedTopologyEax.Uint32,
> > + NULL,
> > + &ExtendedTopologyEcx.Uint32,
> > + NULL
> > + );
> > + LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > + if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > + CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > + break;
> > + }
> > + SubIndex++;
> > + } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > + }
> > + }
> > +
> > + if (!TopologyLeafSupported) {
> > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32,
> NULL, NULL);
> > + MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> > + MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > + }
> > + else {
> > + //
> > + // Must be a single-core processor.
> > + //
> > + MaxCoresPerPackage = 1;
> > + }
> > +
> > + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> > +
> > + if (Thread != NULL) {
> > + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> > + }
> > + if (Core != NULL) {
> > + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > + }
> > + if (Package != NULL) {
> > + *Package = (InitialApicId >> (ThreadBits + CoreBits));
> > + }
> > +}
> > diff --git
> > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > index 4c42696..a34a272 100644
> > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > @@ -1036,3 +1036,149 @@ GetApicMsiValue (
> > }
> > return MsiData.Uint64;
> > }
> > +
> > +/**
> > + Get Package ID/Core ID/Thread ID of a processor.
> > +
> > + The algorithm assumes the target system has symmetry across
> > + physical package boundaries with respect to the number of logical
> > + processors per package, number of cores per package.
> > +
> > + @param[in] InitialApicId Initial APIC ID of the target logical processor.
> > + @param[out] Package Returns the processor package ID.
> > + @param[out] Core Returns the processor core ID.
> > + @param[out] Thread Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > + IN UINT32 InitialApicId,
> > + OUT UINT32 *Package OPTIONAL,
> > + OUT UINT32 *Core OPTIONAL,
> > + OUT UINT32 *Thread OPTIONAL
> > + )
> > +{
> > + BOOLEAN TopologyLeafSupported;
> > + UINTN ThreadBits;
> > + UINTN CoreBits;
> > + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> > + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> > + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> > + UINT32 MaxCpuIdIndex;
> > + UINT32 SubIndex;
> > + UINTN LevelType;
> > + UINT32 MaxLogicProcessorsPerPackage;
> > + UINT32 MaxCoresPerPackage;
> > +
> > + //
> > + // Check if the processor is capable of supporting more than one logical
> processor.
> > + //
> > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> > + &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT == 0) {
> > + if (Thread != NULL) {
> > + *Thread = 0;
> > + }
> > + if (Core != NULL) {
> > + *Core = 0;
> > + }
> > + if (Package != NULL) {
> > + *Package = 0;
> > + }
> > + return;
> > + }
> > +
> > + ThreadBits = 0;
> > + CoreBits = 0;
> > +
> > + //
> > + // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > + //
> > + TopologyLeafSupported = FALSE;
> > +
> > + //
> > + // Get the max index of basic CPUID // AsmCpuid(CPUID_SIGNATURE,
> > + &MaxCpuIdIndex, NULL, NULL, NULL);
> > +
> > + //
> > + // If the extended topology enumeration leaf is available, it //
> > + is the preferred mechanism for enumerating topology.
> > + //
> > + if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > + AsmCpuidEx(
> > + CPUID_EXTENDED_TOPOLOGY,
> > + 0,
> > + &ExtendedTopologyEax.Uint32,
> > + &ExtendedTopologyEbx.Uint32,
> > + &ExtendedTopologyEcx.Uint32,
> > + NULL
> > + );
> > + //
> > + // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > + // supported on that processor.
> > + //
> > + if (ExtendedTopologyEbx.Uint32 != 0) {
> > + TopologyLeafSupported = TRUE;
> > +
> > + //
> > + // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > + // the SMT sub-field of x2APIC ID.
> > + //
> > + LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > + ASSERT(LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > + ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > + //
> > + // Software must not assume any "level type" encoding
> > + // value to be related to any sub-leaf index, except sub-leaf 0.
> > + //
> > + SubIndex = 1;
> > + do {
> > + AsmCpuidEx(
> > + CPUID_EXTENDED_TOPOLOGY,
> > + SubIndex,
> > + &ExtendedTopologyEax.Uint32,
> > + NULL,
> > + &ExtendedTopologyEcx.Uint32,
> > + NULL
> > + );
> > + LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > + if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > + CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > + break;
> > + }
> > + SubIndex++;
> > + } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > + }
> > + }
> > +
> > + if (!TopologyLeafSupported) {
> > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32,
> NULL, NULL);
> > + MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > + if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> > + MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > + }
> > + else {
> > + //
> > + // Must be a single-core processor.
> > + //
> > + MaxCoresPerPackage = 1;
> > + }
> > +
> > + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> > +
> > + if (Thread != NULL) {
> > + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> > + }
> > + if (Core != NULL) {
> > + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > + }
> > + if (Package != NULL) {
> > + *Package = (InitialApicId >> (ThreadBits + CoreBits));
> > + }
> > +}
> > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > index c3fe721..e48ff6a 100644
> > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( }
> >
> > /**
> > - Get CPU Package/Core/Thread location information.
> > -
> > - @param[in] InitialApicId CPU APIC ID
> > - @param[out] Location Pointer to CPU location information
> > -**/
> > -VOID
> > -ExtractProcessorLocation (
> > - IN UINT32 InitialApicId,
> > - OUT EFI_CPU_PHYSICAL_LOCATION *Location
> > - )
> > -{
> > - BOOLEAN TopologyLeafSupported;
> > - UINTN ThreadBits;
> > - UINTN CoreBits;
> > - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> > - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> > - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> > - UINT32 MaxCpuIdIndex;
> > - UINT32 SubIndex;
> > - UINTN LevelType;
> > - UINT32 MaxLogicProcessorsPerPackage;
> > - UINT32 MaxCoresPerPackage;
> > -
> > - //
> > - // Check if the processor is capable of supporting more than one logical
> processor.
> > - //
> > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL,
> > &VersionInfoEdx.Uint32);
> > - if (VersionInfoEdx.Bits.HTT == 0) {
> > - Location->Thread = 0;
> > - Location->Core = 0;
> > - Location->Package = 0;
> > - return;
> > - }
> > -
> > - ThreadBits = 0;
> > - CoreBits = 0;
> > -
> > - //
> > - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > - //
> > -
> > - TopologyLeafSupported = FALSE;
> > - //
> > - // Get the max index of basic CPUID
> > - //
> > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > - //
> > - // If the extended topology enumeration leaf is available, it
> > - // is the preferred mechanism for enumerating topology.
> > - //
> > - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > - AsmCpuidEx (
> > - CPUID_EXTENDED_TOPOLOGY,
> > - 0,
> > - &ExtendedTopologyEax.Uint32,
> > - &ExtendedTopologyEbx.Uint32,
> > - &ExtendedTopologyEcx.Uint32,
> > - NULL
> > - );
> > - //
> > - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > - // supported on that processor.
> > - //
> > - if (ExtendedTopologyEbx.Uint32 != 0) {
> > - TopologyLeafSupported = TRUE;
> > -
> > - //
> > - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > - // the SMT sub-field of x2APIC ID.
> > - //
> > - LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > - ASSERT (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > - ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > -
> > - //
> > - // Software must not assume any "level type" encoding
> > - // value to be related to any sub-leaf index, except sub-leaf 0.
> > - //
> > - SubIndex = 1;
> > - do {
> > - AsmCpuidEx (
> > - CPUID_EXTENDED_TOPOLOGY,
> > - SubIndex,
> > - &ExtendedTopologyEax.Uint32,
> > - NULL,
> > - &ExtendedTopologyEcx.Uint32,
> > - NULL
> > - );
> > - LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > - CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > - break;
> > - }
> > - SubIndex++;
> > - } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > - }
> > - }
> > -
> > - if (!TopologyLeafSupported) {
> > - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32,
> NULL, NULL);
> > - MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> > - MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > - } else {
> > - //
> > - // Must be a single-core processor.
> > - //
> > - MaxCoresPerPackage = 1;
> > - }
> > -
> > - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > - }
> > -
> > - Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> > - Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > - Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); -}
> > -
> > -/**
> > Worker function for SwitchBSP().
> >
> > Worker function for SwitchBSP(), assigned to the AP which is
> > intended @@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo (
> > //
> > // Get processor location information
> > //
> > - ExtractProcessorLocation
> > (CpuMpData->CpuData[ProcessorNumber].ApicId,
> > &ProcessorInfoBuffer->Location);
> > + GetProcessorLocation (
> > + CpuMpData->CpuData[ProcessorNumber].ApicId,
> > + &ProcessorInfoBuffer->Location.Package,
> > + &ProcessorInfoBuffer->Location.Core,
> > + &ProcessorInfoBuffer->Location.Thread
> > + );
> >
> > if (HealthData != NULL) {
> > HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
> > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > index 40f2a17..f377a36 100644
> > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL
> mSmmCpuService = {
> > };
> >
> > /**
> > - Get Package ID/Core ID/Thread ID of a processor.
> > -
> > - APIC ID must be an initial APIC ID.
> > -
> > - The algorithm below assumes the target system has symmetry across
> > physical package boundaries
> > - with respect to the number of logical processors per package, number of
> cores per package.
> > -
> > - @param ApicId APIC ID of the target logical processor.
> > - @param Location Returns the processor location information.
> > -**/
> > -VOID
> > -SmmGetProcessorLocation (
> > - IN UINT32 ApicId,
> > - OUT EFI_CPU_PHYSICAL_LOCATION *Location
> > - )
> > -{
> > - UINTN ThreadBits;
> > - UINTN CoreBits;
> > - UINT32 RegEax;
> > - UINT32 RegEbx;
> > - UINT32 RegEcx;
> > - UINT32 RegEdx;
> > - UINT32 MaxCpuIdIndex;
> > - UINT32 SubIndex;
> > - UINTN LevelType;
> > - UINT32 MaxLogicProcessorsPerPackage;
> > - UINT32 MaxCoresPerPackage;
> > - BOOLEAN TopologyLeafSupported;
> > -
> > - ASSERT (Location != NULL);
> > -
> > - ThreadBits = 0;
> > - CoreBits = 0;
> > - TopologyLeafSupported = FALSE;
> > -
> > - //
> > - // Check if the processor is capable of supporting more than one logical
> processor.
> > - //
> > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
> > - ASSERT ((RegEdx & BIT28) != 0);
> > -
> > - //
> > - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > - //
> > -
> > - //
> > - // Get the max index of basic CPUID
> > - //
> > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > - //
> > - // If the extended topology enumeration leaf is available, it
> > - // is the preferred mechanism for enumerating topology.
> > - //
> > - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx,
> &RegEcx, NULL);
> > - //
> > - // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > - // supported on that processor.
> > - //
> > - if ((RegEbx & 0xffff) != 0) {
> > - TopologyLeafSupported = TRUE;
> > -
> > - //
> > - // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > - // the SMT sub-field of x2APIC ID.
> > - //
> > - LevelType = (RegEcx >> 8) & 0xff;
> > - ASSERT (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > - if ((RegEbx & 0xffff) > 1 ) {
> > - ThreadBits = RegEax & 0x1f;
> > - } else {
> > - //
> > - // HT is not supported
> > - //
> > - ThreadBits = 0;
> > - }
> > -
> > - //
> > - // Software must not assume any "level type" encoding
> > - // value to be related to any sub-leaf index, except sub-leaf 0.
> > - //
> > - SubIndex = 1;
> > - do {
> > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax,
> NULL, &RegEcx, NULL);
> > - LevelType = (RegEcx >> 8) & 0xff;
> > - if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > - CoreBits = (RegEax & 0x1f) - ThreadBits;
> > - break;
> > - }
> > - SubIndex++;
> > - } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > - }
> > - }
> > -
> > - if (!TopologyLeafSupported) {
> > - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
> > - MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
> > - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
> > - MaxCoresPerPackage = (RegEax >> 26) + 1;
> > - } else {
> > - //
> > - // Must be a single-core processor.
> > - //
> > - MaxCoresPerPackage = 1;
> > - }
> > -
> > - ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > - CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > - }
> > -
> > - Location->Thread = ApicId & ~((-1) << ThreadBits);
> > - Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
> > - Location->Package = (ApicId >> (ThreadBits+ CoreBits)); -}
> > -
> > -/**
> > Gets processor information on the requested processor at the instant this
> call is made.
> >
> > @param[in] This A pointer to the
> EFI_SMM_CPU_SERVICE_PROTOCOL instance.
> > @@ -280,7 +161,12 @@ SmmAddProcessor (
> > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId ==
> INVALID_APIC_ID) {
> > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
> > gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
> > - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate-
> >ProcessorInfo[Index].Location);
> > + GetProcessorLocation (
> > + (UINT32)ProcessorId,
> > + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,
> > + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core,
> > + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread
> > + );
> >
> > *ProcessorNumber = Index;
> > gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
> >
next prev parent reply other threads:[~2016-10-31 21:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-31 19:42 [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Leo Duran
2016-10-31 21:23 ` Laszlo Ersek
2016-10-31 21:26 ` Duran, Leo [this message]
2016-10-31 21:29 ` Kinney, Michael D
2016-11-01 0:48 ` Fan, Jeff
2016-11-01 2:25 ` Fan, Jeff
-- strict thread matches above, loose matches on Subject: below --
2016-10-28 17:08 Leo Duran
2016-10-28 17:10 ` Duran, Leo
2016-10-28 16:26 [PATCH] UefiCpuPkg: GetProcessorLocation() Leo Duran
2016-10-28 16:26 ` [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Leo Duran
2016-10-28 16:38 ` Laszlo Ersek
2016-10-28 16:49 ` Duran, Leo
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