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* [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
  2016-10-28 16:26 [PATCH] UefiCpuPkg: GetProcessorLocation() Leo Duran
@ 2016-10-28 16:26 ` Leo Duran
  2016-10-28 16:38   ` Laszlo Ersek
  0 siblings, 1 reply; 11+ messages in thread
From: Leo Duran @ 2016-10-28 16:26 UTC (permalink / raw)
  To: edk2-devel; +Cc: liming.gao, yonghong.zhu, Leo Duran

1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
2) Remove ExtractProcessorLocation() from MpInitLib library.
3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran  <leo.duran@amd.com>
---
 UefiCpuPkg/Include/Library/LocalApicLib.h          |  18 +++
 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 130 +++++++++++++++++++++
 .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 130 +++++++++++++++++++++
 UefiCpuPkg/Library/MpInitLib/MpLib.c               | 128 +-------------------
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 121 +------------------
 5 files changed, 280 insertions(+), 247 deletions(-)
 mode change 100644 => 100755 UefiCpuPkg/Include/Library/LocalApicLib.h
 mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
 mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
 mode change 100644 => 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c
 mode change 100644 => 100755 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c

diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
old mode 100644
new mode 100755
index cd4e613..1d5599a
--- a/UefiCpuPkg/Include/Library/LocalApicLib.h
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -21,6 +21,9 @@
 #define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.
 #define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.
 
+#include <PiPei.h>
+#include <Protocol/MpService.h>
+
 /**
   Retrieve the base address of local APIC.
 
@@ -410,6 +413,21 @@ GetApicMsiValue (
   IN BOOLEAN  LevelTriggered,
   IN BOOLEAN  AssertionLevel
   );
+
+/**
+Get Package ID/Core ID/Thread ID of a processor.
+
+The algorithm assumes the target system has symmetry across physical package boundaries
+with respect to the number of logical processors per package, number of cores per package.
+
+@param  InitialApicId  Must be the initial APIC ID of the target logical processor.
+@param  Location       Returns the processor location information.
+**/
+VOID
+GetProcessorLocation(
+  IN UINT32 InitialApicId,
+  OUT EFI_CPU_PHYSICAL_LOCATION *Location
+);
   
 #endif
 
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index 8d0fb02..2995ac3
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -941,3 +941,133 @@ GetApicMsiValue (
   }
   return MsiData.Uint64;
 }
+
+/**
+Get Package ID/Core ID/Thread ID of a processor.
+
+The algorithm assumes the target system has symmetry across physical package boundaries
+with respect to the number of logical processors per package, number of cores per package.
+
+@param  InitialApicId  Must be the initial APIC ID of the target logical processor.
+@param  Location       Returns the processor location information.
+**/
+VOID
+GetProcessorLocation(
+IN  UINT32                     InitialApicId,
+OUT EFI_CPU_PHYSICAL_LOCATION  *Location
+)
+{
+	BOOLEAN                        TopologyLeafSupported;
+	UINTN                          ThreadBits;
+	UINTN                          CoreBits;
+	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
+	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
+	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
+	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
+	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
+	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
+	UINT32                         MaxCpuIdIndex;
+	UINT32                         SubIndex;
+	UINTN                          LevelType;
+	UINT32                         MaxLogicProcessorsPerPackage;
+	UINT32                         MaxCoresPerPackage;
+
+	//
+	// Check if the processor is capable of supporting more than one logical processor.
+	//
+	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
+	if (VersionInfoEdx.Bits.HTT == 0) {
+		Location->Thread = 0;
+		Location->Core = 0;
+		Location->Package = 0;
+		return;
+	}
+
+	ThreadBits = 0;
+	CoreBits = 0;
+
+	//
+	// Assume three-level mapping of APIC ID: Package:Core:SMT.
+	//
+
+	TopologyLeafSupported = FALSE;
+	//
+	// Get the max index of basic CPUID
+	//
+	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+	//
+	// If the extended topology enumeration leaf is available, it
+	// is the preferred mechanism for enumerating topology.
+	//
+	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+		AsmCpuidEx(
+			CPUID_EXTENDED_TOPOLOGY,
+			0,
+			&ExtendedTopologyEax.Uint32,
+			&ExtendedTopologyEbx.Uint32,
+			&ExtendedTopologyEcx.Uint32,
+			NULL
+			);
+		//
+		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
+		// basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
+		// supported on that processor.
+		//
+		if (ExtendedTopologyEbx.Uint32 != 0) {
+			TopologyLeafSupported = TRUE;
+
+			//
+			// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
+			// the SMT sub-field of x2APIC ID.
+			//
+			LevelType = ExtendedTopologyEcx.Bits.LevelType;
+			ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
+			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
+
+			//
+			// Software must not assume any "level type" encoding
+			// value to be related to any sub-leaf index, except sub-leaf 0.
+			//
+			SubIndex = 1;
+			do {
+				AsmCpuidEx(
+					CPUID_EXTENDED_TOPOLOGY,
+					SubIndex,
+					&ExtendedTopologyEax.Uint32,
+					NULL,
+					&ExtendedTopologyEcx.Uint32,
+					NULL
+					);
+				LevelType = ExtendedTopologyEcx.Bits.LevelType;
+				if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
+					CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
+					break;
+				}
+				SubIndex++;
+			} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+		}
+	}
+
+	if (!TopologyLeafSupported) {
+		AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+		MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
+			AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+			MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+		}
+		else {
+			//
+			// Must be a single-core processor.
+			//
+			MaxCoresPerPackage = 1;
+		}
+
+		ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+	}
+
+	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
+	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+	Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
+}
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
old mode 100644
new mode 100755
index 4c42696..60d32d2
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -1036,3 +1036,133 @@ GetApicMsiValue (
   }
   return MsiData.Uint64;
 }
+
+/**
+Get Package ID/Core ID/Thread ID of a processor.
+
+The algorithm assumes the target system has symmetry across physical package boundaries
+with respect to the number of logical processors per package, number of cores per package.
+
+@param  InitialApicId  Must be the initial APIC ID of the target logical processor.
+@param  Location       Returns the processor location information.
+**/
+VOID
+GetProcessorLocation(
+IN  UINT32                     InitialApicId,
+OUT EFI_CPU_PHYSICAL_LOCATION  *Location
+)
+{
+	BOOLEAN                        TopologyLeafSupported;
+	UINTN                          ThreadBits;
+	UINTN                          CoreBits;
+	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
+	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
+	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
+	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
+	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
+	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
+	UINT32                         MaxCpuIdIndex;
+	UINT32                         SubIndex;
+	UINTN                          LevelType;
+	UINT32                         MaxLogicProcessorsPerPackage;
+	UINT32                         MaxCoresPerPackage;
+
+	//
+	// Check if the processor is capable of supporting more than one logical processor.
+	//
+	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
+	if (VersionInfoEdx.Bits.HTT == 0) {
+		Location->Thread = 0;
+		Location->Core = 0;
+		Location->Package = 0;
+		return;
+	}
+
+	ThreadBits = 0;
+	CoreBits = 0;
+
+	//
+	// Assume three-level mapping of APIC ID: Package:Core:SMT.
+	//
+
+	TopologyLeafSupported = FALSE;
+	//
+	// Get the max index of basic CPUID
+	//
+	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+	//
+	// If the extended topology enumeration leaf is available, it
+	// is the preferred mechanism for enumerating topology.
+	//
+	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+		AsmCpuidEx(
+			CPUID_EXTENDED_TOPOLOGY,
+			0,
+			&ExtendedTopologyEax.Uint32,
+			&ExtendedTopologyEbx.Uint32,
+			&ExtendedTopologyEcx.Uint32,
+			NULL
+			);
+		//
+		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
+		// basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
+		// supported on that processor.
+		//
+		if (ExtendedTopologyEbx.Uint32 != 0) {
+			TopologyLeafSupported = TRUE;
+
+			//
+			// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
+			// the SMT sub-field of x2APIC ID.
+			//
+			LevelType = ExtendedTopologyEcx.Bits.LevelType;
+			ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
+			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
+
+			//
+			// Software must not assume any "level type" encoding
+			// value to be related to any sub-leaf index, except sub-leaf 0.
+			//
+			SubIndex = 1;
+			do {
+				AsmCpuidEx(
+					CPUID_EXTENDED_TOPOLOGY,
+					SubIndex,
+					&ExtendedTopologyEax.Uint32,
+					NULL,
+					&ExtendedTopologyEcx.Uint32,
+					NULL
+					);
+				LevelType = ExtendedTopologyEcx.Bits.LevelType;
+				if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
+					CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
+					break;
+				}
+				SubIndex++;
+			} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+		}
+	}
+
+	if (!TopologyLeafSupported) {
+		AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+		MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
+			AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+			MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+		}
+		else {
+			//
+			// Must be a single-core processor.
+			//
+			MaxCoresPerPackage = 1;
+		}
+
+		ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+	}
+
+	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
+	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+	Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
+}
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
old mode 100644
new mode 100755
index c3fe721..902e212
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (
 }
 
 /**
-  Get CPU Package/Core/Thread location information.
-
-  @param[in]  InitialApicId     CPU APIC ID
-  @param[out] Location          Pointer to CPU location information
-**/
-VOID
-ExtractProcessorLocation (
-  IN  UINT32                     InitialApicId,
-  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
-  )
-{
-  BOOLEAN                        TopologyLeafSupported;
-  UINTN                          ThreadBits;
-  UINTN                          CoreBits;
-  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
-  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
-  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
-  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
-  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
-  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
-  UINT32                         MaxCpuIdIndex;
-  UINT32                         SubIndex;
-  UINTN                          LevelType;
-  UINT32                         MaxLogicProcessorsPerPackage;
-  UINT32                         MaxCoresPerPackage;
-
-  //
-  // Check if the processor is capable of supporting more than one logical processor.
-  //
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
-  if (VersionInfoEdx.Bits.HTT == 0) {
-    Location->Thread  = 0;
-    Location->Core    = 0;
-    Location->Package = 0;
-    return;
-  }
-
-  ThreadBits = 0;
-  CoreBits = 0;
-
-  //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
-  //
-
-  TopologyLeafSupported = FALSE;
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
-
-  //
-  // If the extended topology enumeration leaf is available, it
-  // is the preferred mechanism for enumerating topology.
-  //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
-    AsmCpuidEx (
-      CPUID_EXTENDED_TOPOLOGY,
-      0,
-      &ExtendedTopologyEax.Uint32,
-      &ExtendedTopologyEbx.Uint32,
-      &ExtendedTopologyEcx.Uint32,
-      NULL
-      );
-    //
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
-    // supported on that processor.
-    //
-    if (ExtendedTopologyEbx.Uint32 != 0) {
-      TopologyLeafSupported = TRUE;
-
-      //
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
-      // the SMT sub-field of x2APIC ID.
-      //
-      LevelType = ExtendedTopologyEcx.Bits.LevelType;
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
-      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
-
-      //
-      // Software must not assume any "level type" encoding
-      // value to be related to any sub-leaf index, except sub-leaf 0.
-      //
-      SubIndex = 1;
-      do {
-        AsmCpuidEx (
-          CPUID_EXTENDED_TOPOLOGY,
-          SubIndex,
-          &ExtendedTopologyEax.Uint32,
-          NULL,
-          &ExtendedTopologyEcx.Uint32,
-          NULL
-          );
-        LevelType = ExtendedTopologyEcx.Bits.LevelType;
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
-          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
-          break;
-        }
-        SubIndex++;
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
-    }
-  }
-
-  if (!TopologyLeafSupported) {
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
-    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
-      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
-    } else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
-    }
-
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
-  }
-
-  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
-  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
-  Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
-}
-
-/**
   Worker function for SwitchBSP().
 
   Worker function for SwitchBSP(), assigned to the AP which is intended
@@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo (
   //
   // Get processor location information
   //
-  ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
+  GetProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
 
   if (HealthData != NULL) {
     HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
old mode 100644
new mode 100755
index 40f2a17..75b5fc0
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
@@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {
 };
 
 /**
-  Get Package ID/Core ID/Thread ID of a processor.
-
-  APIC ID must be an initial APIC ID.
-
-  The algorithm below assumes the target system has symmetry across physical package boundaries
-  with respect to the number of logical processors per package, number of cores per package.
-
-  @param  ApicId    APIC ID of the target logical processor.
-  @param  Location    Returns the processor location information.
-**/
-VOID
-SmmGetProcessorLocation (
-  IN UINT32 ApicId,
-  OUT EFI_CPU_PHYSICAL_LOCATION *Location
-  )
-{
-  UINTN   ThreadBits;
-  UINTN   CoreBits;
-  UINT32  RegEax;
-  UINT32  RegEbx;
-  UINT32  RegEcx;
-  UINT32  RegEdx;
-  UINT32  MaxCpuIdIndex;
-  UINT32  SubIndex;
-  UINTN   LevelType;
-  UINT32  MaxLogicProcessorsPerPackage;
-  UINT32  MaxCoresPerPackage;
-  BOOLEAN TopologyLeafSupported;
-
-  ASSERT (Location != NULL);
-
-  ThreadBits            = 0;
-  CoreBits              = 0;
-  TopologyLeafSupported = FALSE;
-
-  //
-  // Check if the processor is capable of supporting more than one logical processor.
-  //
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
-  ASSERT ((RegEdx & BIT28) != 0);
-
-  //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
-  //
-
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
-
-  //
-  // If the extended topology enumeration leaf is available, it
-  // is the preferred mechanism for enumerating topology.
-  //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
-    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
-    //
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
-    // supported on that processor.
-    //
-    if ((RegEbx & 0xffff) != 0) {
-      TopologyLeafSupported = TRUE;
-
-      //
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
-      // the SMT sub-field of x2APIC ID.
-      //
-      LevelType = (RegEcx >> 8) & 0xff;
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
-      if ((RegEbx & 0xffff) > 1 ) {
-        ThreadBits = RegEax & 0x1f;
-      } else {
-        //
-        // HT is not supported
-        //
-        ThreadBits = 0;
-      }
-
-      //
-      // Software must not assume any "level type" encoding
-      // value to be related to any sub-leaf index, except sub-leaf 0.
-      //
-      SubIndex = 1;
-      do {
-        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);
-        LevelType = (RegEcx >> 8) & 0xff;
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
-          CoreBits = (RegEax & 0x1f) - ThreadBits;
-          break;
-        }
-        SubIndex++;
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
-    }
-  }
-
-  if (!TopologyLeafSupported) {
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
-    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
-      MaxCoresPerPackage = (RegEax >> 26) + 1;
-    } else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
-    }
-
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
-  }
-
-  Location->Thread = ApicId & ~((-1) << ThreadBits);
-  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
-  Location->Package = (ApicId >> (ThreadBits+ CoreBits));
-}
-
-/**
   Gets processor information on the requested processor at the instant this call is made.
 
   @param[in]  This                 A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@@ -280,7 +161,7 @@ SmmAddProcessor (
         gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
       gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
       gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
-      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
+      GetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
 
       *ProcessorNumber = Index;
       gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
  2016-10-28 16:26 ` [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Leo Duran
@ 2016-10-28 16:38   ` Laszlo Ersek
  2016-10-28 16:49     ` Duran, Leo
  0 siblings, 1 reply; 11+ messages in thread
From: Laszlo Ersek @ 2016-10-28 16:38 UTC (permalink / raw)
  To: Leo Duran, edk2-devel; +Cc: liming.gao

On 10/28/16 18:26, Leo Duran wrote:
> 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
> 2) Remove ExtractProcessorLocation() from MpInitLib library.
> 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran  <leo.duran@amd.com>
> ---
>  UefiCpuPkg/Include/Library/LocalApicLib.h          |  18 +++
>  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 130 +++++++++++++++++++++
>  .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 130 +++++++++++++++++++++
>  UefiCpuPkg/Library/MpInitLib/MpLib.c               | 128 +-------------------
>  UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 121 +------------------
>  5 files changed, 280 insertions(+), 247 deletions(-)
>  mode change 100644 => 100755 UefiCpuPkg/Include/Library/LocalApicLib.h
>  mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
>  mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
>  mode change 100644 => 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c
>  mode change 100644 => 100755 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c

Can you please remove the file mode changes from the patch?

Thank you,
Laszlo

> diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
> old mode 100644
> new mode 100755
> index cd4e613..1d5599a
> --- a/UefiCpuPkg/Include/Library/LocalApicLib.h
> +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
> @@ -21,6 +21,9 @@
>  #define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.
>  #define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.
>  
> +#include <PiPei.h>
> +#include <Protocol/MpService.h>
> +
>  /**
>    Retrieve the base address of local APIC.
>  
> @@ -410,6 +413,21 @@ GetApicMsiValue (
>    IN BOOLEAN  LevelTriggered,
>    IN BOOLEAN  AssertionLevel
>    );
> +
> +/**
> +Get Package ID/Core ID/Thread ID of a processor.
> +
> +The algorithm assumes the target system has symmetry across physical package boundaries
> +with respect to the number of logical processors per package, number of cores per package.
> +
> +@param  InitialApicId  Must be the initial APIC ID of the target logical processor.
> +@param  Location       Returns the processor location information.
> +**/
> +VOID
> +GetProcessorLocation(
> +  IN UINT32 InitialApicId,
> +  OUT EFI_CPU_PHYSICAL_LOCATION *Location
> +);
>    
>  #endif
>  
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> old mode 100644
> new mode 100755
> index 8d0fb02..2995ac3
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> @@ -941,3 +941,133 @@ GetApicMsiValue (
>    }
>    return MsiData.Uint64;
>  }
> +
> +/**
> +Get Package ID/Core ID/Thread ID of a processor.
> +
> +The algorithm assumes the target system has symmetry across physical package boundaries
> +with respect to the number of logical processors per package, number of cores per package.
> +
> +@param  InitialApicId  Must be the initial APIC ID of the target logical processor.
> +@param  Location       Returns the processor location information.
> +**/
> +VOID
> +GetProcessorLocation(
> +IN  UINT32                     InitialApicId,
> +OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> +)
> +{
> +	BOOLEAN                        TopologyLeafSupported;
> +	UINTN                          ThreadBits;
> +	UINTN                          CoreBits;
> +	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> +	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> +	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> +	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> +	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> +	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> +	UINT32                         MaxCpuIdIndex;
> +	UINT32                         SubIndex;
> +	UINTN                          LevelType;
> +	UINT32                         MaxLogicProcessorsPerPackage;
> +	UINT32                         MaxCoresPerPackage;
> +
> +	//
> +	// Check if the processor is capable of supporting more than one logical processor.
> +	//
> +	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> +	if (VersionInfoEdx.Bits.HTT == 0) {
> +		Location->Thread = 0;
> +		Location->Core = 0;
> +		Location->Package = 0;
> +		return;
> +	}
> +
> +	ThreadBits = 0;
> +	CoreBits = 0;
> +
> +	//
> +	// Assume three-level mapping of APIC ID: Package:Core:SMT.
> +	//
> +
> +	TopologyLeafSupported = FALSE;
> +	//
> +	// Get the max index of basic CPUID
> +	//
> +	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> +
> +	//
> +	// If the extended topology enumeration leaf is available, it
> +	// is the preferred mechanism for enumerating topology.
> +	//
> +	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> +		AsmCpuidEx(
> +			CPUID_EXTENDED_TOPOLOGY,
> +			0,
> +			&ExtendedTopologyEax.Uint32,
> +			&ExtendedTopologyEbx.Uint32,
> +			&ExtendedTopologyEcx.Uint32,
> +			NULL
> +			);
> +		//
> +		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> +		// basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> +		// supported on that processor.
> +		//
> +		if (ExtendedTopologyEbx.Uint32 != 0) {
> +			TopologyLeafSupported = TRUE;
> +
> +			//
> +			// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> +			// the SMT sub-field of x2APIC ID.
> +			//
> +			LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +			ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> +			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> +
> +			//
> +			// Software must not assume any "level type" encoding
> +			// value to be related to any sub-leaf index, except sub-leaf 0.
> +			//
> +			SubIndex = 1;
> +			do {
> +				AsmCpuidEx(
> +					CPUID_EXTENDED_TOPOLOGY,
> +					SubIndex,
> +					&ExtendedTopologyEax.Uint32,
> +					NULL,
> +					&ExtendedTopologyEcx.Uint32,
> +					NULL
> +					);
> +				LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +				if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> +					CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> +					break;
> +				}
> +				SubIndex++;
> +			} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> +		}
> +	}
> +
> +	if (!TopologyLeafSupported) {
> +		AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> +		MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> +			AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> +			MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> +		}
> +		else {
> +			//
> +			// Must be a single-core processor.
> +			//
> +			MaxCoresPerPackage = 1;
> +		}
> +
> +		ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> +		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
> +	}
> +
> +	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> +	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> +	Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
> +}
> diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> old mode 100644
> new mode 100755
> index 4c42696..60d32d2
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> @@ -1036,3 +1036,133 @@ GetApicMsiValue (
>    }
>    return MsiData.Uint64;
>  }
> +
> +/**
> +Get Package ID/Core ID/Thread ID of a processor.
> +
> +The algorithm assumes the target system has symmetry across physical package boundaries
> +with respect to the number of logical processors per package, number of cores per package.
> +
> +@param  InitialApicId  Must be the initial APIC ID of the target logical processor.
> +@param  Location       Returns the processor location information.
> +**/
> +VOID
> +GetProcessorLocation(
> +IN  UINT32                     InitialApicId,
> +OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> +)
> +{
> +	BOOLEAN                        TopologyLeafSupported;
> +	UINTN                          ThreadBits;
> +	UINTN                          CoreBits;
> +	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> +	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> +	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> +	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> +	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> +	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> +	UINT32                         MaxCpuIdIndex;
> +	UINT32                         SubIndex;
> +	UINTN                          LevelType;
> +	UINT32                         MaxLogicProcessorsPerPackage;
> +	UINT32                         MaxCoresPerPackage;
> +
> +	//
> +	// Check if the processor is capable of supporting more than one logical processor.
> +	//
> +	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> +	if (VersionInfoEdx.Bits.HTT == 0) {
> +		Location->Thread = 0;
> +		Location->Core = 0;
> +		Location->Package = 0;
> +		return;
> +	}
> +
> +	ThreadBits = 0;
> +	CoreBits = 0;
> +
> +	//
> +	// Assume three-level mapping of APIC ID: Package:Core:SMT.
> +	//
> +
> +	TopologyLeafSupported = FALSE;
> +	//
> +	// Get the max index of basic CPUID
> +	//
> +	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> +
> +	//
> +	// If the extended topology enumeration leaf is available, it
> +	// is the preferred mechanism for enumerating topology.
> +	//
> +	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> +		AsmCpuidEx(
> +			CPUID_EXTENDED_TOPOLOGY,
> +			0,
> +			&ExtendedTopologyEax.Uint32,
> +			&ExtendedTopologyEbx.Uint32,
> +			&ExtendedTopologyEcx.Uint32,
> +			NULL
> +			);
> +		//
> +		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> +		// basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> +		// supported on that processor.
> +		//
> +		if (ExtendedTopologyEbx.Uint32 != 0) {
> +			TopologyLeafSupported = TRUE;
> +
> +			//
> +			// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> +			// the SMT sub-field of x2APIC ID.
> +			//
> +			LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +			ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> +			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> +
> +			//
> +			// Software must not assume any "level type" encoding
> +			// value to be related to any sub-leaf index, except sub-leaf 0.
> +			//
> +			SubIndex = 1;
> +			do {
> +				AsmCpuidEx(
> +					CPUID_EXTENDED_TOPOLOGY,
> +					SubIndex,
> +					&ExtendedTopologyEax.Uint32,
> +					NULL,
> +					&ExtendedTopologyEcx.Uint32,
> +					NULL
> +					);
> +				LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +				if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> +					CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> +					break;
> +				}
> +				SubIndex++;
> +			} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> +		}
> +	}
> +
> +	if (!TopologyLeafSupported) {
> +		AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> +		MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> +			AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> +			MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> +		}
> +		else {
> +			//
> +			// Must be a single-core processor.
> +			//
> +			MaxCoresPerPackage = 1;
> +		}
> +
> +		ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> +		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
> +	}
> +
> +	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> +	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> +	Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
> +}
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> old mode 100644
> new mode 100755
> index c3fe721..902e212
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (
>  }
>  
>  /**
> -  Get CPU Package/Core/Thread location information.
> -
> -  @param[in]  InitialApicId     CPU APIC ID
> -  @param[out] Location          Pointer to CPU location information
> -**/
> -VOID
> -ExtractProcessorLocation (
> -  IN  UINT32                     InitialApicId,
> -  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> -  )
> -{
> -  BOOLEAN                        TopologyLeafSupported;
> -  UINTN                          ThreadBits;
> -  UINTN                          CoreBits;
> -  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> -  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> -  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> -  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> -  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> -  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> -  UINT32                         MaxCpuIdIndex;
> -  UINT32                         SubIndex;
> -  UINTN                          LevelType;
> -  UINT32                         MaxLogicProcessorsPerPackage;
> -  UINT32                         MaxCoresPerPackage;
> -
> -  //
> -  // Check if the processor is capable of supporting more than one logical processor.
> -  //
> -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> -  if (VersionInfoEdx.Bits.HTT == 0) {
> -    Location->Thread  = 0;
> -    Location->Core    = 0;
> -    Location->Package = 0;
> -    return;
> -  }
> -
> -  ThreadBits = 0;
> -  CoreBits = 0;
> -
> -  //
> -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> -  //
> -
> -  TopologyLeafSupported = FALSE;
> -  //
> -  // Get the max index of basic CPUID
> -  //
> -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> -
> -  //
> -  // If the extended topology enumeration leaf is available, it
> -  // is the preferred mechanism for enumerating topology.
> -  //
> -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> -    AsmCpuidEx (
> -      CPUID_EXTENDED_TOPOLOGY,
> -      0,
> -      &ExtendedTopologyEax.Uint32,
> -      &ExtendedTopologyEbx.Uint32,
> -      &ExtendedTopologyEcx.Uint32,
> -      NULL
> -      );
> -    //
> -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> -    // supported on that processor.
> -    //
> -    if (ExtendedTopologyEbx.Uint32 != 0) {
> -      TopologyLeafSupported = TRUE;
> -
> -      //
> -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> -      // the SMT sub-field of x2APIC ID.
> -      //
> -      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> -      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> -      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> -
> -      //
> -      // Software must not assume any "level type" encoding
> -      // value to be related to any sub-leaf index, except sub-leaf 0.
> -      //
> -      SubIndex = 1;
> -      do {
> -        AsmCpuidEx (
> -          CPUID_EXTENDED_TOPOLOGY,
> -          SubIndex,
> -          &ExtendedTopologyEax.Uint32,
> -          NULL,
> -          &ExtendedTopologyEcx.Uint32,
> -          NULL
> -          );
> -        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> -          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> -          break;
> -        }
> -        SubIndex++;
> -      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> -    }
> -  }
> -
> -  if (!TopologyLeafSupported) {
> -    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> -    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> -      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> -    } else {
> -      //
> -      // Must be a single-core processor.
> -      //
> -      MaxCoresPerPackage = 1;
> -    }
> -
> -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> -  }
> -
> -  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> -  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> -  Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
> -}
> -
> -/**
>    Worker function for SwitchBSP().
>  
>    Worker function for SwitchBSP(), assigned to the AP which is intended
> @@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo (
>    //
>    // Get processor location information
>    //
> -  ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
> +  GetProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
>  
>    if (HealthData != NULL) {
>      HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> old mode 100644
> new mode 100755
> index 40f2a17..75b5fc0
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {
>  };
>  
>  /**
> -  Get Package ID/Core ID/Thread ID of a processor.
> -
> -  APIC ID must be an initial APIC ID.
> -
> -  The algorithm below assumes the target system has symmetry across physical package boundaries
> -  with respect to the number of logical processors per package, number of cores per package.
> -
> -  @param  ApicId    APIC ID of the target logical processor.
> -  @param  Location    Returns the processor location information.
> -**/
> -VOID
> -SmmGetProcessorLocation (
> -  IN UINT32 ApicId,
> -  OUT EFI_CPU_PHYSICAL_LOCATION *Location
> -  )
> -{
> -  UINTN   ThreadBits;
> -  UINTN   CoreBits;
> -  UINT32  RegEax;
> -  UINT32  RegEbx;
> -  UINT32  RegEcx;
> -  UINT32  RegEdx;
> -  UINT32  MaxCpuIdIndex;
> -  UINT32  SubIndex;
> -  UINTN   LevelType;
> -  UINT32  MaxLogicProcessorsPerPackage;
> -  UINT32  MaxCoresPerPackage;
> -  BOOLEAN TopologyLeafSupported;
> -
> -  ASSERT (Location != NULL);
> -
> -  ThreadBits            = 0;
> -  CoreBits              = 0;
> -  TopologyLeafSupported = FALSE;
> -
> -  //
> -  // Check if the processor is capable of supporting more than one logical processor.
> -  //
> -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
> -  ASSERT ((RegEdx & BIT28) != 0);
> -
> -  //
> -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> -  //
> -
> -  //
> -  // Get the max index of basic CPUID
> -  //
> -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> -
> -  //
> -  // If the extended topology enumeration leaf is available, it
> -  // is the preferred mechanism for enumerating topology.
> -  //
> -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> -    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
> -    //
> -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> -    // supported on that processor.
> -    //
> -    if ((RegEbx & 0xffff) != 0) {
> -      TopologyLeafSupported = TRUE;
> -
> -      //
> -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> -      // the SMT sub-field of x2APIC ID.
> -      //
> -      LevelType = (RegEcx >> 8) & 0xff;
> -      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> -      if ((RegEbx & 0xffff) > 1 ) {
> -        ThreadBits = RegEax & 0x1f;
> -      } else {
> -        //
> -        // HT is not supported
> -        //
> -        ThreadBits = 0;
> -      }
> -
> -      //
> -      // Software must not assume any "level type" encoding
> -      // value to be related to any sub-leaf index, except sub-leaf 0.
> -      //
> -      SubIndex = 1;
> -      do {
> -        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);
> -        LevelType = (RegEcx >> 8) & 0xff;
> -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> -          CoreBits = (RegEax & 0x1f) - ThreadBits;
> -          break;
> -        }
> -        SubIndex++;
> -      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> -    }
> -  }
> -
> -  if (!TopologyLeafSupported) {
> -    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
> -    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
> -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
> -      MaxCoresPerPackage = (RegEax >> 26) + 1;
> -    } else {
> -      //
> -      // Must be a single-core processor.
> -      //
> -      MaxCoresPerPackage = 1;
> -    }
> -
> -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> -  }
> -
> -  Location->Thread = ApicId & ~((-1) << ThreadBits);
> -  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
> -  Location->Package = (ApicId >> (ThreadBits+ CoreBits));
> -}
> -
> -/**
>    Gets processor information on the requested processor at the instant this call is made.
>  
>    @param[in]  This                 A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
> @@ -280,7 +161,7 @@ SmmAddProcessor (
>          gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
>        gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
>        gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
> -      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
> +      GetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
>  
>        *ProcessorNumber = Index;
>        gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
> 



^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
  2016-10-28 16:38   ` Laszlo Ersek
@ 2016-10-28 16:49     ` Duran, Leo
  0 siblings, 0 replies; 11+ messages in thread
From: Duran, Leo @ 2016-10-28 16:49 UTC (permalink / raw)
  To: 'Laszlo Ersek', edk2-devel@ml01.01.org; +Cc: liming.gao@intel.com

Reply below.

> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Friday, October 28, 2016 11:38 AM
> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@ml01.01.org
> Cc: liming.gao@intel.com
> Subject: Re: [edk2] [PATCH] UefiCpuPkg: Move GetProcessorLocation() to
> LocalApicLib library
> 
> On 10/28/16 18:26, Leo Duran wrote:
> > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
> > 2) Remove ExtractProcessorLocation() from MpInitLib library.
> > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Leo Duran  <leo.duran@amd.com>
> > ---
> >  UefiCpuPkg/Include/Library/LocalApicLib.h          |  18 +++
> >  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 130
> +++++++++++++++++++++
> >  .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 130
> +++++++++++++++++++++
> >  UefiCpuPkg/Library/MpInitLib/MpLib.c               | 128 +-------------------
> >  UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 121 +------------------
> >  5 files changed, 280 insertions(+), 247 deletions(-)  mode change
> > 100644 => 100755 UefiCpuPkg/Include/Library/LocalApicLib.h
> >  mode change 100644 => 100755
> > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> >  mode change 100644 => 100755
> > UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> >  mode change 100644 => 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c
> >  mode change 100644 => 100755
> UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> 
> Can you please remove the file mode changes from the patch?
[Duran, Leo] Sure thing... I'll resend it.

> 
> Thank you,
> Laszlo
> 
> > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h
> > b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > old mode 100644
> > new mode 100755
> > index cd4e613..1d5599a
> > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h
> > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > @@ -21,6 +21,9 @@
> >  #define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.
> >  #define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.
> >
> > +#include <PiPei.h>
> > +#include <Protocol/MpService.h>
> > +
> >  /**
> >    Retrieve the base address of local APIC.
> >
> > @@ -410,6 +413,21 @@ GetApicMsiValue (
> >    IN BOOLEAN  LevelTriggered,
> >    IN BOOLEAN  AssertionLevel
> >    );
> > +
> > +/**
> > +Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +The algorithm assumes the target system has symmetry across physical
> > +package boundaries with respect to the number of logical processors per
> package, number of cores per package.
> > +
> > +@param  InitialApicId  Must be the initial APIC ID of the target logical
> processor.
> > +@param  Location       Returns the processor location information.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN UINT32 InitialApicId,
> > +  OUT EFI_CPU_PHYSICAL_LOCATION *Location );
> >
> >  #endif
> >
> > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > old mode 100644
> > new mode 100755
> > index 8d0fb02..2995ac3
> > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > @@ -941,3 +941,133 @@ GetApicMsiValue (
> >    }
> >    return MsiData.Uint64;
> >  }
> > +
> > +/**
> > +Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +The algorithm assumes the target system has symmetry across physical
> > +package boundaries with respect to the number of logical processors per
> package, number of cores per package.
> > +
> > +@param  InitialApicId  Must be the initial APIC ID of the target logical
> processor.
> > +@param  Location       Returns the processor location information.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +IN  UINT32                     InitialApicId,
> > +OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> > +)
> > +{
> > +	BOOLEAN                        TopologyLeafSupported;
> > +	UINTN                          ThreadBits;
> > +	UINTN                          CoreBits;
> > +	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> > +	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> > +	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> > +	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> > +	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> > +	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> > +	UINT32                         MaxCpuIdIndex;
> > +	UINT32                         SubIndex;
> > +	UINTN                          LevelType;
> > +	UINT32                         MaxLogicProcessorsPerPackage;
> > +	UINT32                         MaxCoresPerPackage;
> > +
> > +	//
> > +	// Check if the processor is capable of supporting more than one
> logical processor.
> > +	//
> > +	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> > +	if (VersionInfoEdx.Bits.HTT == 0) {
> > +		Location->Thread = 0;
> > +		Location->Core = 0;
> > +		Location->Package = 0;
> > +		return;
> > +	}
> > +
> > +	ThreadBits = 0;
> > +	CoreBits = 0;
> > +
> > +	//
> > +	// Assume three-level mapping of APIC ID: Package:Core:SMT.
> > +	//
> > +
> > +	TopologyLeafSupported = FALSE;
> > +	//
> > +	// Get the max index of basic CPUID
> > +	//
> > +	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL,
> NULL);
> > +
> > +	//
> > +	// If the extended topology enumeration leaf is available, it
> > +	// is the preferred mechanism for enumerating topology.
> > +	//
> > +	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > +		AsmCpuidEx(
> > +			CPUID_EXTENDED_TOPOLOGY,
> > +			0,
> > +			&ExtendedTopologyEax.Uint32,
> > +			&ExtendedTopologyEbx.Uint32,
> > +			&ExtendedTopologyEcx.Uint32,
> > +			NULL
> > +			);
> > +		//
> > +		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and
> maximum input value for
> > +		// basic CPUID information is greater than 0BH, then
> CPUID.0BH leaf is not
> > +		// supported on that processor.
> > +		//
> > +		if (ExtendedTopologyEbx.Uint32 != 0) {
> > +			TopologyLeafSupported = TRUE;
> > +
> > +			//
> > +			// Sub-leaf index 0 (ECX= 0 as input) provides
> enumeration parameters to extract
> > +			// the SMT sub-field of x2APIC ID.
> > +			//
> > +			LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +			ASSERT(LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > +			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > +			//
> > +			// Software must not assume any "level type"
> encoding
> > +			// value to be related to any sub-leaf index, except
> sub-leaf 0.
> > +			//
> > +			SubIndex = 1;
> > +			do {
> > +				AsmCpuidEx(
> > +					CPUID_EXTENDED_TOPOLOGY,
> > +					SubIndex,
> > +					&ExtendedTopologyEax.Uint32,
> > +					NULL,
> > +					&ExtendedTopologyEcx.Uint32,
> > +					NULL
> > +					);
> > +				LevelType =
> ExtendedTopologyEcx.Bits.LevelType;
> > +				if (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > +					CoreBits =
> ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > +					break;
> > +				}
> > +				SubIndex++;
> > +			} while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > +		}
> > +	}
> > +
> > +	if (!TopologyLeafSupported) {
> > +		AsmCpuid(CPUID_VERSION_INFO, NULL,
> &VersionInfoEbx.Uint32, NULL, NULL);
> > +		MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > +			AsmCpuidEx(CPUID_CACHE_PARAMS, 0,
> &CacheParamsEax.Uint32, NULL, NULL, NULL);
> > +			MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > +		}
> > +		else {
> > +			//
> > +			// Must be a single-core processor.
> > +			//
> > +			MaxCoresPerPackage = 1;
> > +		}
> > +
> > +		ThreadBits =
> (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > +		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) +
> 1);
> > +	}
> > +
> > +	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> > +	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > +	Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); }
> > diff --git
> > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > old mode 100644
> > new mode 100755
> > index 4c42696..60d32d2
> > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > @@ -1036,3 +1036,133 @@ GetApicMsiValue (
> >    }
> >    return MsiData.Uint64;
> >  }
> > +
> > +/**
> > +Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +The algorithm assumes the target system has symmetry across physical
> > +package boundaries with respect to the number of logical processors per
> package, number of cores per package.
> > +
> > +@param  InitialApicId  Must be the initial APIC ID of the target logical
> processor.
> > +@param  Location       Returns the processor location information.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +IN  UINT32                     InitialApicId,
> > +OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> > +)
> > +{
> > +	BOOLEAN                        TopologyLeafSupported;
> > +	UINTN                          ThreadBits;
> > +	UINTN                          CoreBits;
> > +	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> > +	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> > +	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> > +	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> > +	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> > +	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> > +	UINT32                         MaxCpuIdIndex;
> > +	UINT32                         SubIndex;
> > +	UINTN                          LevelType;
> > +	UINT32                         MaxLogicProcessorsPerPackage;
> > +	UINT32                         MaxCoresPerPackage;
> > +
> > +	//
> > +	// Check if the processor is capable of supporting more than one
> logical processor.
> > +	//
> > +	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> > +	if (VersionInfoEdx.Bits.HTT == 0) {
> > +		Location->Thread = 0;
> > +		Location->Core = 0;
> > +		Location->Package = 0;
> > +		return;
> > +	}
> > +
> > +	ThreadBits = 0;
> > +	CoreBits = 0;
> > +
> > +	//
> > +	// Assume three-level mapping of APIC ID: Package:Core:SMT.
> > +	//
> > +
> > +	TopologyLeafSupported = FALSE;
> > +	//
> > +	// Get the max index of basic CPUID
> > +	//
> > +	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL,
> NULL);
> > +
> > +	//
> > +	// If the extended topology enumeration leaf is available, it
> > +	// is the preferred mechanism for enumerating topology.
> > +	//
> > +	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > +		AsmCpuidEx(
> > +			CPUID_EXTENDED_TOPOLOGY,
> > +			0,
> > +			&ExtendedTopologyEax.Uint32,
> > +			&ExtendedTopologyEbx.Uint32,
> > +			&ExtendedTopologyEcx.Uint32,
> > +			NULL
> > +			);
> > +		//
> > +		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and
> maximum input value for
> > +		// basic CPUID information is greater than 0BH, then
> CPUID.0BH leaf is not
> > +		// supported on that processor.
> > +		//
> > +		if (ExtendedTopologyEbx.Uint32 != 0) {
> > +			TopologyLeafSupported = TRUE;
> > +
> > +			//
> > +			// Sub-leaf index 0 (ECX= 0 as input) provides
> enumeration parameters to extract
> > +			// the SMT sub-field of x2APIC ID.
> > +			//
> > +			LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +			ASSERT(LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > +			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > +			//
> > +			// Software must not assume any "level type"
> encoding
> > +			// value to be related to any sub-leaf index, except
> sub-leaf 0.
> > +			//
> > +			SubIndex = 1;
> > +			do {
> > +				AsmCpuidEx(
> > +					CPUID_EXTENDED_TOPOLOGY,
> > +					SubIndex,
> > +					&ExtendedTopologyEax.Uint32,
> > +					NULL,
> > +					&ExtendedTopologyEcx.Uint32,
> > +					NULL
> > +					);
> > +				LevelType =
> ExtendedTopologyEcx.Bits.LevelType;
> > +				if (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > +					CoreBits =
> ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > +					break;
> > +				}
> > +				SubIndex++;
> > +			} while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > +		}
> > +	}
> > +
> > +	if (!TopologyLeafSupported) {
> > +		AsmCpuid(CPUID_VERSION_INFO, NULL,
> &VersionInfoEbx.Uint32, NULL, NULL);
> > +		MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > +			AsmCpuidEx(CPUID_CACHE_PARAMS, 0,
> &CacheParamsEax.Uint32, NULL, NULL, NULL);
> > +			MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > +		}
> > +		else {
> > +			//
> > +			// Must be a single-core processor.
> > +			//
> > +			MaxCoresPerPackage = 1;
> > +		}
> > +
> > +		ThreadBits =
> (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > +		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) +
> 1);
> > +	}
> > +
> > +	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> > +	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > +	Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); }
> > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > old mode 100644
> > new mode 100755
> > index c3fe721..902e212
> > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (  }
> >
> >  /**
> > -  Get CPU Package/Core/Thread location information.
> > -
> > -  @param[in]  InitialApicId     CPU APIC ID
> > -  @param[out] Location          Pointer to CPU location information
> > -**/
> > -VOID
> > -ExtractProcessorLocation (
> > -  IN  UINT32                     InitialApicId,
> > -  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> > -  )
> > -{
> > -  BOOLEAN                        TopologyLeafSupported;
> > -  UINTN                          ThreadBits;
> > -  UINTN                          CoreBits;
> > -  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> > -  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> > -  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> > -  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> > -  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> > -  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> > -  UINT32                         MaxCpuIdIndex;
> > -  UINT32                         SubIndex;
> > -  UINTN                          LevelType;
> > -  UINT32                         MaxLogicProcessorsPerPackage;
> > -  UINT32                         MaxCoresPerPackage;
> > -
> > -  //
> > -  // Check if the processor is capable of supporting more than one logical
> processor.
> > -  //
> > -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL,
> > &VersionInfoEdx.Uint32);
> > -  if (VersionInfoEdx.Bits.HTT == 0) {
> > -    Location->Thread  = 0;
> > -    Location->Core    = 0;
> > -    Location->Package = 0;
> > -    return;
> > -  }
> > -
> > -  ThreadBits = 0;
> > -  CoreBits = 0;
> > -
> > -  //
> > -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > -  //
> > -
> > -  TopologyLeafSupported = FALSE;
> > -  //
> > -  // Get the max index of basic CPUID
> > -  //
> > -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > -  //
> > -  // If the extended topology enumeration leaf is available, it
> > -  // is the preferred mechanism for enumerating topology.
> > -  //
> > -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > -    AsmCpuidEx (
> > -      CPUID_EXTENDED_TOPOLOGY,
> > -      0,
> > -      &ExtendedTopologyEax.Uint32,
> > -      &ExtendedTopologyEbx.Uint32,
> > -      &ExtendedTopologyEcx.Uint32,
> > -      NULL
> > -      );
> > -    //
> > -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > -    // supported on that processor.
> > -    //
> > -    if (ExtendedTopologyEbx.Uint32 != 0) {
> > -      TopologyLeafSupported = TRUE;
> > -
> > -      //
> > -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > -      // the SMT sub-field of x2APIC ID.
> > -      //
> > -      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > -      ASSERT (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > -      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > -
> > -      //
> > -      // Software must not assume any "level type" encoding
> > -      // value to be related to any sub-leaf index, except sub-leaf 0.
> > -      //
> > -      SubIndex = 1;
> > -      do {
> > -        AsmCpuidEx (
> > -          CPUID_EXTENDED_TOPOLOGY,
> > -          SubIndex,
> > -          &ExtendedTopologyEax.Uint32,
> > -          NULL,
> > -          &ExtendedTopologyEcx.Uint32,
> > -          NULL
> > -          );
> > -        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > -          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > -          break;
> > -        }
> > -        SubIndex++;
> > -      } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > -    }
> > -  }
> > -
> > -  if (!TopologyLeafSupported) {
> > -    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32,
> NULL, NULL);
> > -    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> > -      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > -    } else {
> > -      //
> > -      // Must be a single-core processor.
> > -      //
> > -      MaxCoresPerPackage = 1;
> > -    }
> > -
> > -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > -  }
> > -
> > -  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > -  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > -  Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); -}
> > -
> > -/**
> >    Worker function for SwitchBSP().
> >
> >    Worker function for SwitchBSP(), assigned to the AP which is
> > intended @@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo (
> >    //
> >    // Get processor location information
> >    //
> > -  ExtractProcessorLocation
> > (CpuMpData->CpuData[ProcessorNumber].ApicId,
> > &ProcessorInfoBuffer->Location);
> > +  GetProcessorLocation (CpuMpData-
> >CpuData[ProcessorNumber].ApicId,
> > + &ProcessorInfoBuffer->Location);
> >
> >    if (HealthData != NULL) {
> >      HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
> > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > old mode 100644
> > new mode 100755
> > index 40f2a17..75b5fc0
> > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL
> mSmmCpuService = {
> > };
> >
> >  /**
> > -  Get Package ID/Core ID/Thread ID of a processor.
> > -
> > -  APIC ID must be an initial APIC ID.
> > -
> > -  The algorithm below assumes the target system has symmetry across
> > physical package boundaries
> > -  with respect to the number of logical processors per package, number of
> cores per package.
> > -
> > -  @param  ApicId    APIC ID of the target logical processor.
> > -  @param  Location    Returns the processor location information.
> > -**/
> > -VOID
> > -SmmGetProcessorLocation (
> > -  IN UINT32 ApicId,
> > -  OUT EFI_CPU_PHYSICAL_LOCATION *Location
> > -  )
> > -{
> > -  UINTN   ThreadBits;
> > -  UINTN   CoreBits;
> > -  UINT32  RegEax;
> > -  UINT32  RegEbx;
> > -  UINT32  RegEcx;
> > -  UINT32  RegEdx;
> > -  UINT32  MaxCpuIdIndex;
> > -  UINT32  SubIndex;
> > -  UINTN   LevelType;
> > -  UINT32  MaxLogicProcessorsPerPackage;
> > -  UINT32  MaxCoresPerPackage;
> > -  BOOLEAN TopologyLeafSupported;
> > -
> > -  ASSERT (Location != NULL);
> > -
> > -  ThreadBits            = 0;
> > -  CoreBits              = 0;
> > -  TopologyLeafSupported = FALSE;
> > -
> > -  //
> > -  // Check if the processor is capable of supporting more than one logical
> processor.
> > -  //
> > -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
> > -  ASSERT ((RegEdx & BIT28) != 0);
> > -
> > -  //
> > -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > -  //
> > -
> > -  //
> > -  // Get the max index of basic CPUID
> > -  //
> > -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > -  //
> > -  // If the extended topology enumeration leaf is available, it
> > -  // is the preferred mechanism for enumerating topology.
> > -  //
> > -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > -    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx,
> &RegEcx, NULL);
> > -    //
> > -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > -    // supported on that processor.
> > -    //
> > -    if ((RegEbx & 0xffff) != 0) {
> > -      TopologyLeafSupported = TRUE;
> > -
> > -      //
> > -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > -      // the SMT sub-field of x2APIC ID.
> > -      //
> > -      LevelType = (RegEcx >> 8) & 0xff;
> > -      ASSERT (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > -      if ((RegEbx & 0xffff) > 1 ) {
> > -        ThreadBits = RegEax & 0x1f;
> > -      } else {
> > -        //
> > -        // HT is not supported
> > -        //
> > -        ThreadBits = 0;
> > -      }
> > -
> > -      //
> > -      // Software must not assume any "level type" encoding
> > -      // value to be related to any sub-leaf index, except sub-leaf 0.
> > -      //
> > -      SubIndex = 1;
> > -      do {
> > -        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax,
> NULL, &RegEcx, NULL);
> > -        LevelType = (RegEcx >> 8) & 0xff;
> > -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > -          CoreBits = (RegEax & 0x1f) - ThreadBits;
> > -          break;
> > -        }
> > -        SubIndex++;
> > -      } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > -    }
> > -  }
> > -
> > -  if (!TopologyLeafSupported) {
> > -    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
> > -    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
> > -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
> > -      MaxCoresPerPackage = (RegEax >> 26) + 1;
> > -    } else {
> > -      //
> > -      // Must be a single-core processor.
> > -      //
> > -      MaxCoresPerPackage = 1;
> > -    }
> > -
> > -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > -  }
> > -
> > -  Location->Thread = ApicId & ~((-1) << ThreadBits);
> > -  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
> > -  Location->Package = (ApicId >> (ThreadBits+ CoreBits)); -}
> > -
> > -/**
> >    Gets processor information on the requested processor at the instant this
> call is made.
> >
> >    @param[in]  This                 A pointer to the
> EFI_SMM_CPU_SERVICE_PROTOCOL instance.
> > @@ -280,7 +161,7 @@ SmmAddProcessor (
> >          gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId ==
> INVALID_APIC_ID) {
> >        gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
> >        gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
> > -      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate-
> >ProcessorInfo[Index].Location);
> > +      GetProcessorLocation ((UINT32)ProcessorId,
> > + &gSmmCpuPrivate->ProcessorInfo[Index].Location);
> >
> >        *ProcessorNumber = Index;
> >        gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
> >



^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
@ 2016-10-28 17:08 Leo Duran
  2016-10-28 17:10 ` Duran, Leo
  0 siblings, 1 reply; 11+ messages in thread
From: Leo Duran @ 2016-10-28 17:08 UTC (permalink / raw)
  To: edk2-devel; +Cc: liming.gao, lersek, jeff.fan, michael.d.kinney, Leo Duran

1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
2) Remove ExtractProcessorLocation() from MpInitLib library.
3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran  <leo.duran@amd.com>
---
 Maintainers.txt                                    | 240 ---------------------
 UefiCpuPkg/Include/Library/LocalApicLib.h          |  18 ++
 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 130 +++++++++++
 .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 130 +++++++++++
 UefiCpuPkg/Library/MpInitLib/MpLib.c               | 128 +----------
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 121 +----------
 6 files changed, 280 insertions(+), 487 deletions(-)
 delete mode 100644 Maintainers.txt
 mode change 100644 => 100755 UefiCpuPkg/Include/Library/LocalApicLib.h
 mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
 mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
 mode change 100644 => 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c
 mode change 100644 => 100755 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c

diff --git a/Maintainers.txt b/Maintainers.txt
deleted file mode 100644
index 94d3380..0000000
--- a/Maintainers.txt
+++ /dev/null
@@ -1,240 +0,0 @@
-EDK II Maintainers
-==================
-
-This file provides information about the primary maintainers for
-EDK II.
-
-In general, you should not privately email the maintainer. You should
-email the edk2-devel list, but you can also Cc the maintainer.
-
-Descriptions of section entries:
-
-  L: Mailing list that is relevant to this area (default is edk2-devel)
-     Patches and questions should be sent to the email list.
-  M: Cc address for patches and questions (ie, the package maintainer)
-  W: Web-page with status/info
-  T: SCM tree type and location.  Type is one of: git, svn.
-  S: Status, one of the following:
-     Supported:  Someone is actually paid to look after this.
-     Maintained: Someone actually looks after it.
-     Odd Fixes:  It has a maintainer but they don't have time to do
-                 much other than throw the odd patch in. See below.
-     Orphan:     No current maintainer [but maybe you could take the
-                 role as you write your new code].
-     Obsolete:   Old code. Something tagged obsolete generally means
-                 it has been replaced by a better system and you
-                 should be using that.
-
-EDK II
-------
-W: http://www.tianocore.org/edk2/
-L: https://lists.sourceforge.net/lists/listinfo/edk2-devel
-T: git - https://github.com/tianocore/edk2.git
-T: git (mirror) - https://bitbucket.org/tianocore/edk2.git
-T: git (mirror) - http://git.code.sf.net/p/tianocore/edk2
-T: svn (read-only, deprecated) - https://svn.code.sf.net/p/edk2/code/trunk/edk2
-
-Responsible Disclosure, Reporting Security Issues
--------------------------------------------------
-W: https://github.com/tianocore/tianocore.github.io/wiki/Security
-
-EDK II Releases:
-----------------
-UDK2014
-W: http://www.tianocore.org/udk2014/
-S: Supported
-
-EDK II Packages:
-----------------
-AppPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/AppPkg
-M: Daryl McDaniel <edk2-lists@mc2research.org>
-M: Jaben Carsey <jaben.carsey@intel.com>
-
-ArmPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/ArmPkg
-M: Leif Lindholm <leif.lindholm@linaro.org>
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-
-ArmPlatformPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/ArmPlatformPkg
-M: Leif Lindholm <leif.lindholm@linaro.org>
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-
-ArmVirtPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/ArmVirtPkg
-M: Laszlo Ersek <lersek@redhat.com>
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-
-BaseTools
-W: https://github.com/tianocore/tianocore.github.io/wiki/BaseTools
-M: Yonghong Zhu <yonghong.zhu@intel.com>
-M: Liming Gao <liming.gao@intel.com>
-
-BeagleBoardPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/BeagleBoardPkg
-M: Leif Lindholm <leif.lindholm@linaro.org>
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-
-CorebootModulePkg, CorebootPayloadPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/Coreboot_UEFI_payload
-M: Maurice Ma <maurice.ma@intel.com>
-M: Prince Agyeman <prince.agyeman@intel.com>
-S: Maintained
-
-CryptoPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/CryptoPkg
-M: Qin Long <qin.long@intel.com>
-M: Ting Ye <ting.ye@intel.com>
-
-DuetPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/DuetPkg
-M: Ruiyu Ni <ruiyu.ni@intel.com>
-
-EdkCompatibilityPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/EdkCompatibilityPkg
-M: Liming Gao <liming.gao@intel.com>
-
-EdkShellPkg, EdkShellBinPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/EdkShellPkg
-M: Ruiyu Ni <ruiyu.ni@intel.com>
-T: svn - https://svn.code.sf.net/p/efi-shell/code/trunk/Shell/
-S: Obsolete (Use ShellPkg & ShellBinPkg instead)
-
-EmbeddedPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/EmbeddedPkg
-M: Leif Lindholm <leif.lindholm@linaro.org>
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-
-EmulatorPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/EmulatorPkg
-M: Jordan Justen <jordan.l.justen@intel.com>
-M: Andrew Fish <afish@apple.com>
-S: Maintained
-
-FatPkg, FatBinPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/Edk2-fat-driver
-M: Ruiyu Ni <ruiyu.ni@intel.com>
-T: svn - https://svn.code.sf.net/p/edk2-fatdriver2/code/trunk/EnhancedFat
-T: git - https://github.com/tianocore/edk2-FatPkg.git
-
-IntelFrameworkModulePkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFrameworkModulePkg
-M: Jeff Fan <jeff.fan@intel.com>
-
-IntelFrameworkPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFrameworkPkg
-M: Michael D Kinney <michael.d.kinney@intel.com>
-M: Jeff Fan <jeff.fan@intel.com>
-
-IntelFsp2Pkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg
-M: Jiewen Yao <jiewen.yao@intel.com>
-M: Giri P Mudusuru <giri.p.mudusuru@intel.com>
-
-IntelFsp2WrapperPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPkg
-M: Jiewen Yao <jiewen.yao@intel.com>
-M: Giri P Mudusuru <giri.p.mudusuru@intel.com>
-
-IntelFspPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg
-M: Jiewen Yao <jiewen.yao@intel.com>
-
-IntelFspWrapperPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspWrapperPkg
-M: Jiewen Yao <jiewen.yao@intel.com>
-
-IntelSiliconPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/IntelSiliconPkg
-M: Jiewen Yao <jiewen.yao@intel.com>
-M: Giri P Mudusuru <giri.p.mudusuru@intel.com>
-
-MdeModulePkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/MdeModulePkg
-M: Feng Tian <feng.tian@intel.com>
-M: Star Zeng <star.zeng@intel.com>
-
-MdePkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/MdePkg
-M: Michael D Kinney <michael.d.kinney@intel.com>
-M: Liming Gao <liming.gao@intel.com>
-
-NetworkPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/NetworkPkg
-M: Siyuan Fu <siyuan.fu@intel.com>
-M: Jiaxin Wu <jiaxin.wu@intel.com>
-
-Nt32Pkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/Nt32Pkg
-M: Ruiyu Ni <ruiyu.ni@intel.com>
-
-Omap35xxPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/Omap35xxPkg
-M: Leif Lindholm <leif.lindholm@linaro.org>
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
-
-OptionRomPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/OptionRomPkg
-M: Ruiyu Ni <ruiyu.ni@intel.com>
-
-OvmfPkg
-W: http://www.tianocore.org/ovmf/
-M: Jordan Justen <jordan.l.justen@intel.com>
-M: Laszlo Ersek <lersek@redhat.com>
-S: Maintained
-
-PcAtChipsetPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg
-M: Ruiyu Ni <ruiyu.ni@intel.com>
-
-PerformancePkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/PerformancePkg
-M: Daryl McDaniel <edk2-lists@mc2research.org>
-M: Jaben Carsey <jaben.carsey@intel.com>
-
-QuarkPlatformPkg, QuarkSocPkg
-M: Michael D Kinney <michael.d.kinney@intel.com>
-M: Kelly Steele <kelly.steele@intel.com>
-
-SecurityPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg
-M: Chao Zhang <chao.b.zhang@intel.com>
-
-ShellBinPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/ShellPkg
-M: Jaben Carsey <jaben.carsey@intel.com>      (Ia32/X64)
-M: Ruiyu Ni <ruiyu.ni@intel.com>          (Ia32/X64)
-M: Leif Lindholm <leif.lindholm@linaro.org>   (ARM/AArch64)
-M: Ard Biesheuvel <ard.biesheuvel@linaro.org> (ARM/AArch64)
-
-ShellPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/ShellPkg
-M: Jaben Carsey <jaben.carsey@intel.com>
-M: Ruiyu Ni <ruiyu.ni@intel.com>
-
-SourceLevelDebugPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/SourceLevelDebugPkg
-M: Jeff Fan <jeff.fan@intel.com>
-M: Hao Wu <hao.a.wu@intel.com>
-
-StdLib, StdLibPrivateInternalFiles
-W: https://github.com/tianocore/tianocore.github.io/wiki/StdLib
-M: Daryl McDaniel <edk2-lists@mc2research.org>
-M: Jaben Carsey <jaben.carsey@intel.com>
-
-UefiCpuPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/UefiCpuPkg
-M: Jeff Fan <jeff.fan@intel.com>
-
-UnixPkg
-W: https://github.com/tianocore/tianocore.github.io/wiki/UnixPkg
-S: Obsolete (Use EmulatorPkg instead)
-
-Vlv2DeviceRefCodePkg
-M: David Wei <david.wei@intel.com>
-M: Mang Guo <mang.guo@intel.com>
-
-Vlv2TbltDevicePkg
-M: David Wei <david.wei@intel.com>
-M: Mang Guo <mang.guo@intel.com>
diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
old mode 100644
new mode 100755
index cd4e613..4abf64c
--- a/UefiCpuPkg/Include/Library/LocalApicLib.h
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -21,6 +21,9 @@
 #define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.
 #define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.
 
+#include <PiPei.h>
+#include <Protocol/MpService.h>
+
 /**
   Retrieve the base address of local APIC.
 
@@ -410,6 +413,21 @@ GetApicMsiValue (
   IN BOOLEAN  LevelTriggered,
   IN BOOLEAN  AssertionLevel
   );
+
+/**
+Get Package ID/Core ID/Thread ID of a processor.
+
+The algorithm assumes the target system has symmetry across physical package boundaries
+with respect to the number of logical processors per package, number of cores per package.
+
+@param  InitialApicId  Must be the initial APIC ID of the target logical processor.
+@param  Location       Returns the processor location information.
+**/
+VOID
+GetProcessorLocation(
+  IN UINT32 InitialApicId,
+  OUT EFI_CPU_PHYSICAL_LOCATION *Location
+);
   
 #endif
 
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index 8d0fb02..219f99f
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -941,3 +941,133 @@ GetApicMsiValue (
   }
   return MsiData.Uint64;
 }
+
+/**
+Get Package ID/Core ID/Thread ID of a processor.
+
+The algorithm assumes the target system has symmetry across physical package boundaries
+with respect to the number of logical processors per package, number of cores per package.
+
+@param  InitialApicId  Must be the initial APIC ID of the target logical processor.
+@param  Location       Returns the processor location information.
+**/
+VOID
+GetProcessorLocation(
+IN  UINT32                     InitialApicId,
+OUT EFI_CPU_PHYSICAL_LOCATION  *Location
+)
+{
+	BOOLEAN                        TopologyLeafSupported;
+	UINTN                          ThreadBits;
+	UINTN                          CoreBits;
+	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
+	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
+	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
+	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
+	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
+	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
+	UINT32                         MaxCpuIdIndex;
+	UINT32                         SubIndex;
+	UINTN                          LevelType;
+	UINT32                         MaxLogicProcessorsPerPackage;
+	UINT32                         MaxCoresPerPackage;
+
+	//
+	// Check if the processor is capable of supporting more than one logical processor.
+	//
+	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
+	if (VersionInfoEdx.Bits.HTT == 0) {
+		Location->Thread = 0;
+		Location->Core = 0;
+		Location->Package = 0;
+		return;
+	}
+
+	ThreadBits = 0;
+	CoreBits = 0;
+
+	//
+	// Assume three-level mapping of APIC ID: Package:Core:SMT.
+	//
+
+	TopologyLeafSupported = FALSE;
+	//
+	// Get the max index of basic CPUID
+	//
+	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+	//
+	// If the extended topology enumeration leaf is available, it
+	// is the preferred mechanism for enumerating topology.
+	//
+	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+		AsmCpuidEx(
+			CPUID_EXTENDED_TOPOLOGY,
+			0,
+			&ExtendedTopologyEax.Uint32,
+			&ExtendedTopologyEbx.Uint32,
+			&ExtendedTopologyEcx.Uint32,
+			NULL
+			);
+		//
+		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
+		// basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
+		// supported on that processor.
+		//
+		if (ExtendedTopologyEbx.Uint32 != 0) {
+			TopologyLeafSupported = TRUE;
+
+			//
+			// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
+			// the SMT sub-field of x2APIC ID.
+			//
+			LevelType = ExtendedTopologyEcx.Bits.LevelType;
+			ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
+			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
+
+			//
+			// Software must not assume any "level type" encoding
+			// value to be related to any sub-leaf index, except sub-leaf 0.
+			//
+			SubIndex = 1;
+			do {
+				AsmCpuidEx(
+					CPUID_EXTENDED_TOPOLOGY,
+					SubIndex,
+					&ExtendedTopologyEax.Uint32,
+					NULL,
+					&ExtendedTopologyEcx.Uint32,
+					NULL
+					);
+				LevelType = ExtendedTopologyEcx.Bits.LevelType;
+				if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
+					CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
+					break;
+				}
+				SubIndex++;
+			} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+		}
+	}
+
+	if (!TopologyLeafSupported) {
+		AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+		MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
+			AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+			MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+		}
+		else {
+			//
+			// Must be a single-core processor.
+			//
+			MaxCoresPerPackage = 1;
+		}
+
+		ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+	}
+
+	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
+	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+	Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
+}
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
old mode 100644
new mode 100755
index 4c42696..16395a3
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -1036,3 +1036,133 @@ GetApicMsiValue (
   }
   return MsiData.Uint64;
 }
+
+/**
+Get Package ID/Core ID/Thread ID of a processor.
+
+The algorithm assumes the target system has symmetry across physical package boundaries
+with respect to the number of logical processors per package, number of cores per package.
+
+@param  InitialApicId  Must be the initial APIC ID of the target logical processor.
+@param  Location       Returns the processor location information.
+**/
+VOID
+GetProcessorLocation(
+IN  UINT32                     InitialApicId,
+OUT EFI_CPU_PHYSICAL_LOCATION  *Location
+)
+{
+	BOOLEAN                        TopologyLeafSupported;
+	UINTN                          ThreadBits;
+	UINTN                          CoreBits;
+	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
+	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
+	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
+	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
+	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
+	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
+	UINT32                         MaxCpuIdIndex;
+	UINT32                         SubIndex;
+	UINTN                          LevelType;
+	UINT32                         MaxLogicProcessorsPerPackage;
+	UINT32                         MaxCoresPerPackage;
+
+	//
+	// Check if the processor is capable of supporting more than one logical processor.
+	//
+	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
+	if (VersionInfoEdx.Bits.HTT == 0) {
+		Location->Thread = 0;
+		Location->Core = 0;
+		Location->Package = 0;
+		return;
+	}
+
+	ThreadBits = 0;
+	CoreBits = 0;
+
+	//
+	// Assume three-level mapping of APIC ID: Package:Core:SMT.
+	//
+
+	TopologyLeafSupported = FALSE;
+	//
+	// Get the max index of basic CPUID
+	//
+	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+	//
+	// If the extended topology enumeration leaf is available, it
+	// is the preferred mechanism for enumerating topology.
+	//
+	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+		AsmCpuidEx(
+			CPUID_EXTENDED_TOPOLOGY,
+			0,
+			&ExtendedTopologyEax.Uint32,
+			&ExtendedTopologyEbx.Uint32,
+			&ExtendedTopologyEcx.Uint32,
+			NULL
+			);
+		//
+		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
+		// basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
+		// supported on that processor.
+		//
+		if (ExtendedTopologyEbx.Uint32 != 0) {
+			TopologyLeafSupported = TRUE;
+
+			//
+			// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
+			// the SMT sub-field of x2APIC ID.
+			//
+			LevelType = ExtendedTopologyEcx.Bits.LevelType;
+			ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
+			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
+
+			//
+			// Software must not assume any "level type" encoding
+			// value to be related to any sub-leaf index, except sub-leaf 0.
+			//
+			SubIndex = 1;
+			do {
+				AsmCpuidEx(
+					CPUID_EXTENDED_TOPOLOGY,
+					SubIndex,
+					&ExtendedTopologyEax.Uint32,
+					NULL,
+					&ExtendedTopologyEcx.Uint32,
+					NULL
+					);
+				LevelType = ExtendedTopologyEcx.Bits.LevelType;
+				if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
+					CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
+					break;
+				}
+				SubIndex++;
+			} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+		}
+	}
+
+	if (!TopologyLeafSupported) {
+		AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+		MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
+			AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+			MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+		}
+		else {
+			//
+			// Must be a single-core processor.
+			//
+			MaxCoresPerPackage = 1;
+		}
+
+		ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+	}
+
+	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
+	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+	Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
+}
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
old mode 100644
new mode 100755
index c3fe721..f3380bb
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (
 }
 
 /**
-  Get CPU Package/Core/Thread location information.
-
-  @param[in]  InitialApicId     CPU APIC ID
-  @param[out] Location          Pointer to CPU location information
-**/
-VOID
-ExtractProcessorLocation (
-  IN  UINT32                     InitialApicId,
-  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
-  )
-{
-  BOOLEAN                        TopologyLeafSupported;
-  UINTN                          ThreadBits;
-  UINTN                          CoreBits;
-  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
-  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
-  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
-  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
-  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
-  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
-  UINT32                         MaxCpuIdIndex;
-  UINT32                         SubIndex;
-  UINTN                          LevelType;
-  UINT32                         MaxLogicProcessorsPerPackage;
-  UINT32                         MaxCoresPerPackage;
-
-  //
-  // Check if the processor is capable of supporting more than one logical processor.
-  //
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
-  if (VersionInfoEdx.Bits.HTT == 0) {
-    Location->Thread  = 0;
-    Location->Core    = 0;
-    Location->Package = 0;
-    return;
-  }
-
-  ThreadBits = 0;
-  CoreBits = 0;
-
-  //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
-  //
-
-  TopologyLeafSupported = FALSE;
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
-
-  //
-  // If the extended topology enumeration leaf is available, it
-  // is the preferred mechanism for enumerating topology.
-  //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
-    AsmCpuidEx (
-      CPUID_EXTENDED_TOPOLOGY,
-      0,
-      &ExtendedTopologyEax.Uint32,
-      &ExtendedTopologyEbx.Uint32,
-      &ExtendedTopologyEcx.Uint32,
-      NULL
-      );
-    //
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
-    // supported on that processor.
-    //
-    if (ExtendedTopologyEbx.Uint32 != 0) {
-      TopologyLeafSupported = TRUE;
-
-      //
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
-      // the SMT sub-field of x2APIC ID.
-      //
-      LevelType = ExtendedTopologyEcx.Bits.LevelType;
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
-      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
-
-      //
-      // Software must not assume any "level type" encoding
-      // value to be related to any sub-leaf index, except sub-leaf 0.
-      //
-      SubIndex = 1;
-      do {
-        AsmCpuidEx (
-          CPUID_EXTENDED_TOPOLOGY,
-          SubIndex,
-          &ExtendedTopologyEax.Uint32,
-          NULL,
-          &ExtendedTopologyEcx.Uint32,
-          NULL
-          );
-        LevelType = ExtendedTopologyEcx.Bits.LevelType;
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
-          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
-          break;
-        }
-        SubIndex++;
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
-    }
-  }
-
-  if (!TopologyLeafSupported) {
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
-    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
-      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
-    } else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
-    }
-
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
-  }
-
-  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
-  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
-  Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
-}
-
-/**
   Worker function for SwitchBSP().
 
   Worker function for SwitchBSP(), assigned to the AP which is intended
@@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo (
   //
   // Get processor location information
   //
-  ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
+  GetProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
 
   if (HealthData != NULL) {
     HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
old mode 100644
new mode 100755
index 40f2a17..67cd0a0
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
@@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {
 };
 
 /**
-  Get Package ID/Core ID/Thread ID of a processor.
-
-  APIC ID must be an initial APIC ID.
-
-  The algorithm below assumes the target system has symmetry across physical package boundaries
-  with respect to the number of logical processors per package, number of cores per package.
-
-  @param  ApicId    APIC ID of the target logical processor.
-  @param  Location    Returns the processor location information.
-**/
-VOID
-SmmGetProcessorLocation (
-  IN UINT32 ApicId,
-  OUT EFI_CPU_PHYSICAL_LOCATION *Location
-  )
-{
-  UINTN   ThreadBits;
-  UINTN   CoreBits;
-  UINT32  RegEax;
-  UINT32  RegEbx;
-  UINT32  RegEcx;
-  UINT32  RegEdx;
-  UINT32  MaxCpuIdIndex;
-  UINT32  SubIndex;
-  UINTN   LevelType;
-  UINT32  MaxLogicProcessorsPerPackage;
-  UINT32  MaxCoresPerPackage;
-  BOOLEAN TopologyLeafSupported;
-
-  ASSERT (Location != NULL);
-
-  ThreadBits            = 0;
-  CoreBits              = 0;
-  TopologyLeafSupported = FALSE;
-
-  //
-  // Check if the processor is capable of supporting more than one logical processor.
-  //
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
-  ASSERT ((RegEdx & BIT28) != 0);
-
-  //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
-  //
-
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
-
-  //
-  // If the extended topology enumeration leaf is available, it
-  // is the preferred mechanism for enumerating topology.
-  //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
-    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
-    //
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
-    // supported on that processor.
-    //
-    if ((RegEbx & 0xffff) != 0) {
-      TopologyLeafSupported = TRUE;
-
-      //
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
-      // the SMT sub-field of x2APIC ID.
-      //
-      LevelType = (RegEcx >> 8) & 0xff;
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
-      if ((RegEbx & 0xffff) > 1 ) {
-        ThreadBits = RegEax & 0x1f;
-      } else {
-        //
-        // HT is not supported
-        //
-        ThreadBits = 0;
-      }
-
-      //
-      // Software must not assume any "level type" encoding
-      // value to be related to any sub-leaf index, except sub-leaf 0.
-      //
-      SubIndex = 1;
-      do {
-        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);
-        LevelType = (RegEcx >> 8) & 0xff;
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
-          CoreBits = (RegEax & 0x1f) - ThreadBits;
-          break;
-        }
-        SubIndex++;
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
-    }
-  }
-
-  if (!TopologyLeafSupported) {
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
-    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
-      MaxCoresPerPackage = (RegEax >> 26) + 1;
-    } else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
-    }
-
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
-  }
-
-  Location->Thread = ApicId & ~((-1) << ThreadBits);
-  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
-  Location->Package = (ApicId >> (ThreadBits+ CoreBits));
-}
-
-/**
   Gets processor information on the requested processor at the instant this call is made.
 
   @param[in]  This                 A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@@ -280,7 +161,7 @@ SmmAddProcessor (
         gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
       gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
       gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
-      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
+      GetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
 
       *ProcessorNumber = Index;
       gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
  2016-10-28 17:08 Leo Duran
@ 2016-10-28 17:10 ` Duran, Leo
  0 siblings, 0 replies; 11+ messages in thread
From: Duran, Leo @ 2016-10-28 17:10 UTC (permalink / raw)
  To: edk2-devel@lists.01.org
  Cc: liming.gao@intel.com, lersek@redhat.com, jeff.fan@intel.com,
	michael.d.kinney@intel.com

Sorry, the file mode looks wrong again.... I will fix this.
Leo.

> -----Original Message-----
> From: Duran, Leo
> Sent: Friday, October 28, 2016 12:08 PM
> To: edk2-devel@lists.01.org
> Cc: liming.gao@intel.com; lersek@redhat.com; jeff.fan@intel.com;
> michael.d.kinney@intel.com; Duran, Leo <leo.duran@amd.com>
> Subject: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib
> library
> 
> 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
> 2) Remove ExtractProcessorLocation() from MpInitLib library.
> 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran  <leo.duran@amd.com>
> ---
>  Maintainers.txt                                    | 240 ---------------------
>  UefiCpuPkg/Include/Library/LocalApicLib.h          |  18 ++
>  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 130 +++++++++++
>  .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 130 +++++++++++
>  UefiCpuPkg/Library/MpInitLib/MpLib.c               | 128 +----------
>  UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 121 +----------
>  6 files changed, 280 insertions(+), 487 deletions(-)  delete mode 100644
> Maintainers.txt  mode change 100644 => 100755
> UefiCpuPkg/Include/Library/LocalApicLib.h
>  mode change 100644 => 100755
> UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
>  mode change 100644 => 100755
> UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
>  mode change 100644 => 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c
>  mode change 100644 => 100755
> UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> 
> diff --git a/Maintainers.txt b/Maintainers.txt deleted file mode 100644 index
> 94d3380..0000000
> --- a/Maintainers.txt
> +++ /dev/null
> @@ -1,240 +0,0 @@
> -EDK II Maintainers
> -==================
> -
> -This file provides information about the primary maintainers for -EDK II.
> -
> -In general, you should not privately email the maintainer. You should -email
> the edk2-devel list, but you can also Cc the maintainer.
> -
> -Descriptions of section entries:
> -
> -  L: Mailing list that is relevant to this area (default is edk2-devel)
> -     Patches and questions should be sent to the email list.
> -  M: Cc address for patches and questions (ie, the package maintainer)
> -  W: Web-page with status/info
> -  T: SCM tree type and location.  Type is one of: git, svn.
> -  S: Status, one of the following:
> -     Supported:  Someone is actually paid to look after this.
> -     Maintained: Someone actually looks after it.
> -     Odd Fixes:  It has a maintainer but they don't have time to do
> -                 much other than throw the odd patch in. See below.
> -     Orphan:     No current maintainer [but maybe you could take the
> -                 role as you write your new code].
> -     Obsolete:   Old code. Something tagged obsolete generally means
> -                 it has been replaced by a better system and you
> -                 should be using that.
> -
> -EDK II
> -------
> -W: http://www.tianocore.org/edk2/
> -L: https://lists.sourceforge.net/lists/listinfo/edk2-devel
> -T: git - https://github.com/tianocore/edk2.git
> -T: git (mirror) - https://bitbucket.org/tianocore/edk2.git
> -T: git (mirror) - http://git.code.sf.net/p/tianocore/edk2
> -T: svn (read-only, deprecated) -
> https://svn.code.sf.net/p/edk2/code/trunk/edk2
> -
> -Responsible Disclosure, Reporting Security Issues
> --------------------------------------------------
> -W: https://github.com/tianocore/tianocore.github.io/wiki/Security
> -
> -EDK II Releases:
> -----------------
> -UDK2014
> -W: http://www.tianocore.org/udk2014/
> -S: Supported
> -
> -EDK II Packages:
> -----------------
> -AppPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/AppPkg
> -M: Daryl McDaniel <edk2-lists@mc2research.org>
> -M: Jaben Carsey <jaben.carsey@intel.com>
> -
> -ArmPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/ArmPkg
> -M: Leif Lindholm <leif.lindholm@linaro.org>
> -M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> -
> -ArmPlatformPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/ArmPlatformPkg
> -M: Leif Lindholm <leif.lindholm@linaro.org>
> -M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> -
> -ArmVirtPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/ArmVirtPkg
> -M: Laszlo Ersek <lersek@redhat.com>
> -M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> -
> -BaseTools
> -W: https://github.com/tianocore/tianocore.github.io/wiki/BaseTools
> -M: Yonghong Zhu <yonghong.zhu@intel.com>
> -M: Liming Gao <liming.gao@intel.com>
> -
> -BeagleBoardPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/BeagleBoardPkg
> -M: Leif Lindholm <leif.lindholm@linaro.org>
> -M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> -
> -CorebootModulePkg, CorebootPayloadPkg
> -W:
> https://github.com/tianocore/tianocore.github.io/wiki/Coreboot_UEFI_payl
> oad
> -M: Maurice Ma <maurice.ma@intel.com>
> -M: Prince Agyeman <prince.agyeman@intel.com>
> -S: Maintained
> -
> -CryptoPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/CryptoPkg
> -M: Qin Long <qin.long@intel.com>
> -M: Ting Ye <ting.ye@intel.com>
> -
> -DuetPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/DuetPkg
> -M: Ruiyu Ni <ruiyu.ni@intel.com>
> -
> -EdkCompatibilityPkg
> -W:
> https://github.com/tianocore/tianocore.github.io/wiki/EdkCompatibilityPkg
> -M: Liming Gao <liming.gao@intel.com>
> -
> -EdkShellPkg, EdkShellBinPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/EdkShellPkg
> -M: Ruiyu Ni <ruiyu.ni@intel.com>
> -T: svn - https://svn.code.sf.net/p/efi-shell/code/trunk/Shell/
> -S: Obsolete (Use ShellPkg & ShellBinPkg instead)
> -
> -EmbeddedPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/EmbeddedPkg
> -M: Leif Lindholm <leif.lindholm@linaro.org>
> -M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> -
> -EmulatorPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/EmulatorPkg
> -M: Jordan Justen <jordan.l.justen@intel.com>
> -M: Andrew Fish <afish@apple.com>
> -S: Maintained
> -
> -FatPkg, FatBinPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/Edk2-fat-driver
> -M: Ruiyu Ni <ruiyu.ni@intel.com>
> -T: svn - https://svn.code.sf.net/p/edk2-fatdriver2/code/trunk/EnhancedFat
> -T: git - https://github.com/tianocore/edk2-FatPkg.git
> -
> -IntelFrameworkModulePkg
> -W:
> https://github.com/tianocore/tianocore.github.io/wiki/IntelFrameworkMod
> ulePkg
> -M: Jeff Fan <jeff.fan@intel.com>
> -
> -IntelFrameworkPkg
> -W:
> https://github.com/tianocore/tianocore.github.io/wiki/IntelFrameworkPkg
> -M: Michael D Kinney <michael.d.kinney@intel.com>
> -M: Jeff Fan <jeff.fan@intel.com>
> -
> -IntelFsp2Pkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg
> -M: Jiewen Yao <jiewen.yao@intel.com>
> -M: Giri P Mudusuru <giri.p.mudusuru@intel.com>
> -
> -IntelFsp2WrapperPkg
> -W:
> https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPk
> g
> -M: Jiewen Yao <jiewen.yao@intel.com>
> -M: Giri P Mudusuru <giri.p.mudusuru@intel.com>
> -
> -IntelFspPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg
> -M: Jiewen Yao <jiewen.yao@intel.com>
> -
> -IntelFspWrapperPkg
> -W:
> https://github.com/tianocore/tianocore.github.io/wiki/IntelFspWrapperPkg
> -M: Jiewen Yao <jiewen.yao@intel.com>
> -
> -IntelSiliconPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/IntelSiliconPkg
> -M: Jiewen Yao <jiewen.yao@intel.com>
> -M: Giri P Mudusuru <giri.p.mudusuru@intel.com>
> -
> -MdeModulePkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/MdeModulePkg
> -M: Feng Tian <feng.tian@intel.com>
> -M: Star Zeng <star.zeng@intel.com>
> -
> -MdePkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/MdePkg
> -M: Michael D Kinney <michael.d.kinney@intel.com>
> -M: Liming Gao <liming.gao@intel.com>
> -
> -NetworkPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/NetworkPkg
> -M: Siyuan Fu <siyuan.fu@intel.com>
> -M: Jiaxin Wu <jiaxin.wu@intel.com>
> -
> -Nt32Pkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/Nt32Pkg
> -M: Ruiyu Ni <ruiyu.ni@intel.com>
> -
> -Omap35xxPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/Omap35xxPkg
> -M: Leif Lindholm <leif.lindholm@linaro.org>
> -M: Ard Biesheuvel <ard.biesheuvel@linaro.org>
> -
> -OptionRomPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/OptionRomPkg
> -M: Ruiyu Ni <ruiyu.ni@intel.com>
> -
> -OvmfPkg
> -W: http://www.tianocore.org/ovmf/
> -M: Jordan Justen <jordan.l.justen@intel.com>
> -M: Laszlo Ersek <lersek@redhat.com>
> -S: Maintained
> -
> -PcAtChipsetPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg
> -M: Ruiyu Ni <ruiyu.ni@intel.com>
> -
> -PerformancePkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/PerformancePkg
> -M: Daryl McDaniel <edk2-lists@mc2research.org>
> -M: Jaben Carsey <jaben.carsey@intel.com>
> -
> -QuarkPlatformPkg, QuarkSocPkg
> -M: Michael D Kinney <michael.d.kinney@intel.com>
> -M: Kelly Steele <kelly.steele@intel.com>
> -
> -SecurityPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg
> -M: Chao Zhang <chao.b.zhang@intel.com>
> -
> -ShellBinPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/ShellPkg
> -M: Jaben Carsey <jaben.carsey@intel.com>      (Ia32/X64)
> -M: Ruiyu Ni <ruiyu.ni@intel.com>          (Ia32/X64)
> -M: Leif Lindholm <leif.lindholm@linaro.org>   (ARM/AArch64)
> -M: Ard Biesheuvel <ard.biesheuvel@linaro.org> (ARM/AArch64)
> -
> -ShellPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/ShellPkg
> -M: Jaben Carsey <jaben.carsey@intel.com>
> -M: Ruiyu Ni <ruiyu.ni@intel.com>
> -
> -SourceLevelDebugPkg
> -W:
> https://github.com/tianocore/tianocore.github.io/wiki/SourceLevelDebugPk
> g
> -M: Jeff Fan <jeff.fan@intel.com>
> -M: Hao Wu <hao.a.wu@intel.com>
> -
> -StdLib, StdLibPrivateInternalFiles
> -W: https://github.com/tianocore/tianocore.github.io/wiki/StdLib
> -M: Daryl McDaniel <edk2-lists@mc2research.org>
> -M: Jaben Carsey <jaben.carsey@intel.com>
> -
> -UefiCpuPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/UefiCpuPkg
> -M: Jeff Fan <jeff.fan@intel.com>
> -
> -UnixPkg
> -W: https://github.com/tianocore/tianocore.github.io/wiki/UnixPkg
> -S: Obsolete (Use EmulatorPkg instead)
> -
> -Vlv2DeviceRefCodePkg
> -M: David Wei <david.wei@intel.com>
> -M: Mang Guo <mang.guo@intel.com>
> -
> -Vlv2TbltDevicePkg
> -M: David Wei <david.wei@intel.com>
> -M: Mang Guo <mang.guo@intel.com>
> diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h
> b/UefiCpuPkg/Include/Library/LocalApicLib.h
> old mode 100644
> new mode 100755
> index cd4e613..4abf64c
> --- a/UefiCpuPkg/Include/Library/LocalApicLib.h
> +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
> @@ -21,6 +21,9 @@
>  #define LOCAL_APIC_MODE_XAPIC   0x1  ///< xAPIC mode.
>  #define LOCAL_APIC_MODE_X2APIC  0x2  ///< x2APIC mode.
> 
> +#include <PiPei.h>
> +#include <Protocol/MpService.h>
> +
>  /**
>    Retrieve the base address of local APIC.
> 
> @@ -410,6 +413,21 @@ GetApicMsiValue (
>    IN BOOLEAN  LevelTriggered,
>    IN BOOLEAN  AssertionLevel
>    );
> +
> +/**
> +Get Package ID/Core ID/Thread ID of a processor.
> +
> +The algorithm assumes the target system has symmetry across physical
> +package boundaries with respect to the number of logical processors per
> package, number of cores per package.
> +
> +@param  InitialApicId  Must be the initial APIC ID of the target logical
> processor.
> +@param  Location       Returns the processor location information.
> +**/
> +VOID
> +GetProcessorLocation(
> +  IN UINT32 InitialApicId,
> +  OUT EFI_CPU_PHYSICAL_LOCATION *Location );
> 
>  #endif
> 
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> old mode 100644
> new mode 100755
> index 8d0fb02..219f99f
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> @@ -941,3 +941,133 @@ GetApicMsiValue (
>    }
>    return MsiData.Uint64;
>  }
> +
> +/**
> +Get Package ID/Core ID/Thread ID of a processor.
> +
> +The algorithm assumes the target system has symmetry across physical
> +package boundaries with respect to the number of logical processors per
> package, number of cores per package.
> +
> +@param  InitialApicId  Must be the initial APIC ID of the target logical
> processor.
> +@param  Location       Returns the processor location information.
> +**/
> +VOID
> +GetProcessorLocation(
> +IN  UINT32                     InitialApicId,
> +OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> +)
> +{
> +	BOOLEAN                        TopologyLeafSupported;
> +	UINTN                          ThreadBits;
> +	UINTN                          CoreBits;
> +	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> +	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> +	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> +	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> +	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> +	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> +	UINT32                         MaxCpuIdIndex;
> +	UINT32                         SubIndex;
> +	UINTN                          LevelType;
> +	UINT32                         MaxLogicProcessorsPerPackage;
> +	UINT32                         MaxCoresPerPackage;
> +
> +	//
> +	// Check if the processor is capable of supporting more than one
> logical processor.
> +	//
> +	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> +	if (VersionInfoEdx.Bits.HTT == 0) {
> +		Location->Thread = 0;
> +		Location->Core = 0;
> +		Location->Package = 0;
> +		return;
> +	}
> +
> +	ThreadBits = 0;
> +	CoreBits = 0;
> +
> +	//
> +	// Assume three-level mapping of APIC ID: Package:Core:SMT.
> +	//
> +
> +	TopologyLeafSupported = FALSE;
> +	//
> +	// Get the max index of basic CPUID
> +	//
> +	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL,
> NULL);
> +
> +	//
> +	// If the extended topology enumeration leaf is available, it
> +	// is the preferred mechanism for enumerating topology.
> +	//
> +	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> +		AsmCpuidEx(
> +			CPUID_EXTENDED_TOPOLOGY,
> +			0,
> +			&ExtendedTopologyEax.Uint32,
> +			&ExtendedTopologyEbx.Uint32,
> +			&ExtendedTopologyEcx.Uint32,
> +			NULL
> +			);
> +		//
> +		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and
> maximum input value for
> +		// basic CPUID information is greater than 0BH, then
> CPUID.0BH leaf is not
> +		// supported on that processor.
> +		//
> +		if (ExtendedTopologyEbx.Uint32 != 0) {
> +			TopologyLeafSupported = TRUE;
> +
> +			//
> +			// Sub-leaf index 0 (ECX= 0 as input) provides
> enumeration parameters to extract
> +			// the SMT sub-field of x2APIC ID.
> +			//
> +			LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +			ASSERT(LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> +			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> +
> +			//
> +			// Software must not assume any "level type"
> encoding
> +			// value to be related to any sub-leaf index, except
> sub-leaf 0.
> +			//
> +			SubIndex = 1;
> +			do {
> +				AsmCpuidEx(
> +					CPUID_EXTENDED_TOPOLOGY,
> +					SubIndex,
> +					&ExtendedTopologyEax.Uint32,
> +					NULL,
> +					&ExtendedTopologyEcx.Uint32,
> +					NULL
> +					);
> +				LevelType =
> ExtendedTopologyEcx.Bits.LevelType;
> +				if (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> +					CoreBits =
> ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> +					break;
> +				}
> +				SubIndex++;
> +			} while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> +		}
> +	}
> +
> +	if (!TopologyLeafSupported) {
> +		AsmCpuid(CPUID_VERSION_INFO, NULL,
> &VersionInfoEbx.Uint32, NULL, NULL);
> +		MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> +			AsmCpuidEx(CPUID_CACHE_PARAMS, 0,
> &CacheParamsEax.Uint32, NULL, NULL, NULL);
> +			MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> +		}
> +		else {
> +			//
> +			// Must be a single-core processor.
> +			//
> +			MaxCoresPerPackage = 1;
> +		}
> +
> +		ThreadBits =
> (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> +		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) +
> 1);
> +	}
> +
> +	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> +	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> +	Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); }
> diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> old mode 100644
> new mode 100755
> index 4c42696..16395a3
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> @@ -1036,3 +1036,133 @@ GetApicMsiValue (
>    }
>    return MsiData.Uint64;
>  }
> +
> +/**
> +Get Package ID/Core ID/Thread ID of a processor.
> +
> +The algorithm assumes the target system has symmetry across physical
> +package boundaries with respect to the number of logical processors per
> package, number of cores per package.
> +
> +@param  InitialApicId  Must be the initial APIC ID of the target logical
> processor.
> +@param  Location       Returns the processor location information.
> +**/
> +VOID
> +GetProcessorLocation(
> +IN  UINT32                     InitialApicId,
> +OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> +)
> +{
> +	BOOLEAN                        TopologyLeafSupported;
> +	UINTN                          ThreadBits;
> +	UINTN                          CoreBits;
> +	CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> +	CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> +	CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> +	CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> +	CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> +	CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> +	UINT32                         MaxCpuIdIndex;
> +	UINT32                         SubIndex;
> +	UINTN                          LevelType;
> +	UINT32                         MaxLogicProcessorsPerPackage;
> +	UINT32                         MaxCoresPerPackage;
> +
> +	//
> +	// Check if the processor is capable of supporting more than one
> logical processor.
> +	//
> +	AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> +	if (VersionInfoEdx.Bits.HTT == 0) {
> +		Location->Thread = 0;
> +		Location->Core = 0;
> +		Location->Package = 0;
> +		return;
> +	}
> +
> +	ThreadBits = 0;
> +	CoreBits = 0;
> +
> +	//
> +	// Assume three-level mapping of APIC ID: Package:Core:SMT.
> +	//
> +
> +	TopologyLeafSupported = FALSE;
> +	//
> +	// Get the max index of basic CPUID
> +	//
> +	AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL,
> NULL);
> +
> +	//
> +	// If the extended topology enumeration leaf is available, it
> +	// is the preferred mechanism for enumerating topology.
> +	//
> +	if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> +		AsmCpuidEx(
> +			CPUID_EXTENDED_TOPOLOGY,
> +			0,
> +			&ExtendedTopologyEax.Uint32,
> +			&ExtendedTopologyEbx.Uint32,
> +			&ExtendedTopologyEcx.Uint32,
> +			NULL
> +			);
> +		//
> +		// If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and
> maximum input value for
> +		// basic CPUID information is greater than 0BH, then
> CPUID.0BH leaf is not
> +		// supported on that processor.
> +		//
> +		if (ExtendedTopologyEbx.Uint32 != 0) {
> +			TopologyLeafSupported = TRUE;
> +
> +			//
> +			// Sub-leaf index 0 (ECX= 0 as input) provides
> enumeration parameters to extract
> +			// the SMT sub-field of x2APIC ID.
> +			//
> +			LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +			ASSERT(LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> +			ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> +
> +			//
> +			// Software must not assume any "level type"
> encoding
> +			// value to be related to any sub-leaf index, except
> sub-leaf 0.
> +			//
> +			SubIndex = 1;
> +			do {
> +				AsmCpuidEx(
> +					CPUID_EXTENDED_TOPOLOGY,
> +					SubIndex,
> +					&ExtendedTopologyEax.Uint32,
> +					NULL,
> +					&ExtendedTopologyEcx.Uint32,
> +					NULL
> +					);
> +				LevelType =
> ExtendedTopologyEcx.Bits.LevelType;
> +				if (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> +					CoreBits =
> ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> +					break;
> +				}
> +				SubIndex++;
> +			} while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> +		}
> +	}
> +
> +	if (!TopologyLeafSupported) {
> +		AsmCpuid(CPUID_VERSION_INFO, NULL,
> &VersionInfoEbx.Uint32, NULL, NULL);
> +		MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +		if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> +			AsmCpuidEx(CPUID_CACHE_PARAMS, 0,
> &CacheParamsEax.Uint32, NULL, NULL, NULL);
> +			MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> +		}
> +		else {
> +			//
> +			// Must be a single-core processor.
> +			//
> +			MaxCoresPerPackage = 1;
> +		}
> +
> +		ThreadBits =
> (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> +		CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) +
> 1);
> +	}
> +
> +	Location->Thread = InitialApicId & ((1 << ThreadBits) - 1);
> +	Location->Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> +	Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); }
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> old mode 100644
> new mode 100755
> index c3fe721..f3380bb
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (  }
> 
>  /**
> -  Get CPU Package/Core/Thread location information.
> -
> -  @param[in]  InitialApicId     CPU APIC ID
> -  @param[out] Location          Pointer to CPU location information
> -**/
> -VOID
> -ExtractProcessorLocation (
> -  IN  UINT32                     InitialApicId,
> -  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> -  )
> -{
> -  BOOLEAN                        TopologyLeafSupported;
> -  UINTN                          ThreadBits;
> -  UINTN                          CoreBits;
> -  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> -  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> -  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> -  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> -  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> -  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> -  UINT32                         MaxCpuIdIndex;
> -  UINT32                         SubIndex;
> -  UINTN                          LevelType;
> -  UINT32                         MaxLogicProcessorsPerPackage;
> -  UINT32                         MaxCoresPerPackage;
> -
> -  //
> -  // Check if the processor is capable of supporting more than one logical
> processor.
> -  //
> -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> -  if (VersionInfoEdx.Bits.HTT == 0) {
> -    Location->Thread  = 0;
> -    Location->Core    = 0;
> -    Location->Package = 0;
> -    return;
> -  }
> -
> -  ThreadBits = 0;
> -  CoreBits = 0;
> -
> -  //
> -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> -  //
> -
> -  TopologyLeafSupported = FALSE;
> -  //
> -  // Get the max index of basic CPUID
> -  //
> -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> -
> -  //
> -  // If the extended topology enumeration leaf is available, it
> -  // is the preferred mechanism for enumerating topology.
> -  //
> -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> -    AsmCpuidEx (
> -      CPUID_EXTENDED_TOPOLOGY,
> -      0,
> -      &ExtendedTopologyEax.Uint32,
> -      &ExtendedTopologyEbx.Uint32,
> -      &ExtendedTopologyEcx.Uint32,
> -      NULL
> -      );
> -    //
> -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> -    // supported on that processor.
> -    //
> -    if (ExtendedTopologyEbx.Uint32 != 0) {
> -      TopologyLeafSupported = TRUE;
> -
> -      //
> -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> -      // the SMT sub-field of x2APIC ID.
> -      //
> -      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> -      ASSERT (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> -      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> -
> -      //
> -      // Software must not assume any "level type" encoding
> -      // value to be related to any sub-leaf index, except sub-leaf 0.
> -      //
> -      SubIndex = 1;
> -      do {
> -        AsmCpuidEx (
> -          CPUID_EXTENDED_TOPOLOGY,
> -          SubIndex,
> -          &ExtendedTopologyEax.Uint32,
> -          NULL,
> -          &ExtendedTopologyEcx.Uint32,
> -          NULL
> -          );
> -        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> -          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> -          break;
> -        }
> -        SubIndex++;
> -      } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> -    }
> -  }
> -
> -  if (!TopologyLeafSupported) {
> -    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> NULL);
> -    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> -      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> -    } else {
> -      //
> -      // Must be a single-core processor.
> -      //
> -      MaxCoresPerPackage = 1;
> -    }
> -
> -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> -  }
> -
> -  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> -  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> -  Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); -}
> -
> -/**
>    Worker function for SwitchBSP().
> 
>    Worker function for SwitchBSP(), assigned to the AP which is intended @@
> -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo (
>    //
>    // Get processor location information
>    //
> -  ExtractProcessorLocation (CpuMpData-
> >CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
> +  GetProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId,
> + &ProcessorInfoBuffer->Location);
> 
>    if (HealthData != NULL) {
>      HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> old mode 100644
> new mode 100755
> index 40f2a17..67cd0a0
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL
> mSmmCpuService = {  };
> 
>  /**
> -  Get Package ID/Core ID/Thread ID of a processor.
> -
> -  APIC ID must be an initial APIC ID.
> -
> -  The algorithm below assumes the target system has symmetry across
> physical package boundaries
> -  with respect to the number of logical processors per package, number of
> cores per package.
> -
> -  @param  ApicId    APIC ID of the target logical processor.
> -  @param  Location    Returns the processor location information.
> -**/
> -VOID
> -SmmGetProcessorLocation (
> -  IN UINT32 ApicId,
> -  OUT EFI_CPU_PHYSICAL_LOCATION *Location
> -  )
> -{
> -  UINTN   ThreadBits;
> -  UINTN   CoreBits;
> -  UINT32  RegEax;
> -  UINT32  RegEbx;
> -  UINT32  RegEcx;
> -  UINT32  RegEdx;
> -  UINT32  MaxCpuIdIndex;
> -  UINT32  SubIndex;
> -  UINTN   LevelType;
> -  UINT32  MaxLogicProcessorsPerPackage;
> -  UINT32  MaxCoresPerPackage;
> -  BOOLEAN TopologyLeafSupported;
> -
> -  ASSERT (Location != NULL);
> -
> -  ThreadBits            = 0;
> -  CoreBits              = 0;
> -  TopologyLeafSupported = FALSE;
> -
> -  //
> -  // Check if the processor is capable of supporting more than one logical
> processor.
> -  //
> -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
> -  ASSERT ((RegEdx & BIT28) != 0);
> -
> -  //
> -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> -  //
> -
> -  //
> -  // Get the max index of basic CPUID
> -  //
> -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> -
> -  //
> -  // If the extended topology enumeration leaf is available, it
> -  // is the preferred mechanism for enumerating topology.
> -  //
> -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> -    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx,
> &RegEcx, NULL);
> -    //
> -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> -    // supported on that processor.
> -    //
> -    if ((RegEbx & 0xffff) != 0) {
> -      TopologyLeafSupported = TRUE;
> -
> -      //
> -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> -      // the SMT sub-field of x2APIC ID.
> -      //
> -      LevelType = (RegEcx >> 8) & 0xff;
> -      ASSERT (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> -      if ((RegEbx & 0xffff) > 1 ) {
> -        ThreadBits = RegEax & 0x1f;
> -      } else {
> -        //
> -        // HT is not supported
> -        //
> -        ThreadBits = 0;
> -      }
> -
> -      //
> -      // Software must not assume any "level type" encoding
> -      // value to be related to any sub-leaf index, except sub-leaf 0.
> -      //
> -      SubIndex = 1;
> -      do {
> -        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL,
> &RegEcx, NULL);
> -        LevelType = (RegEcx >> 8) & 0xff;
> -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> -          CoreBits = (RegEax & 0x1f) - ThreadBits;
> -          break;
> -        }
> -        SubIndex++;
> -      } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> -    }
> -  }
> -
> -  if (!TopologyLeafSupported) {
> -    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
> -    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
> -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
> -      MaxCoresPerPackage = (RegEax >> 26) + 1;
> -    } else {
> -      //
> -      // Must be a single-core processor.
> -      //
> -      MaxCoresPerPackage = 1;
> -    }
> -
> -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> -  }
> -
> -  Location->Thread = ApicId & ~((-1) << ThreadBits);
> -  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
> -  Location->Package = (ApicId >> (ThreadBits+ CoreBits)); -}
> -
> -/**
>    Gets processor information on the requested processor at the instant this
> call is made.
> 
>    @param[in]  This                 A pointer to the
> EFI_SMM_CPU_SERVICE_PROTOCOL instance.
> @@ -280,7 +161,7 @@ SmmAddProcessor (
>          gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId ==
> INVALID_APIC_ID) {
>        gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
>        gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
> -      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate-
> >ProcessorInfo[Index].Location);
> +      GetProcessorLocation ((UINT32)ProcessorId,
> + &gSmmCpuPrivate->ProcessorInfo[Index].Location);
> 
>        *ProcessorNumber = Index;
>        gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
> --
> 1.9.1



^ permalink raw reply	[flat|nested] 11+ messages in thread

* [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
@ 2016-10-31 19:42 Leo Duran
  2016-10-31 21:23 ` Laszlo Ersek
  2016-11-01  2:25 ` Fan, Jeff
  0 siblings, 2 replies; 11+ messages in thread
From: Leo Duran @ 2016-10-31 19:42 UTC (permalink / raw)
  To: edk2-devel; +Cc: liming.gao, lersek, jeff.fan, michael.d.kinney, Leo Duran

1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
2) Remove ExtractProcessorLocation() from MpInitLib library.
3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran  <leo.duran@amd.com>
---
 UefiCpuPkg/Include/Library/LocalApicLib.h          |  20 +++
 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 146 +++++++++++++++++++++
 .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 146 +++++++++++++++++++++
 UefiCpuPkg/Library/MpInitLib/MpLib.c               | 133 +------------------
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 126 +-----------------
 5 files changed, 324 insertions(+), 247 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
index cd4e613..179409e 100644
--- a/UefiCpuPkg/Include/Library/LocalApicLib.h
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -410,6 +410,26 @@ GetApicMsiValue (
   IN BOOLEAN  LevelTriggered,
   IN BOOLEAN  AssertionLevel
   );
+
+/**
+  Get Package ID/Core ID/Thread ID of a processor.
+
+  The algorithm assumes the target system has symmetry across physical
+  package  boundaries with respect to the number of logical processors
+  per package,  number of cores per package.
+
+  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
+  @param[out]  Package       Returns the processor package ID.
+  @param[out]  Core          Returns the processor core ID.
+  @param[out]  Thread        Returns the processor thread ID.
+**/
+VOID
+GetProcessorLocation(
+  IN  UINT32  InitialApicId,
+  OUT UINT32  *Package  OPTIONAL,
+  OUT UINT32  *Core    OPTIONAL,
+  OUT UINT32  *Thread  OPTIONAL
+  );
   
 #endif
 
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 8d0fb02..f32d287 100644
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -941,3 +941,149 @@ GetApicMsiValue (
   }
   return MsiData.Uint64;
 }
+
+/**
+  Get Package ID/Core ID/Thread ID of a processor.
+
+  The algorithm assumes the target system has symmetry across physical
+  package  boundaries with respect to the number of logical processors
+  per package,  number of cores per package.
+
+  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
+  @param[out]  Package       Returns the processor package ID.
+  @param[out]  Core          Returns the processor core ID.
+  @param[out]  Thread        Returns the processor thread ID.
+**/
+VOID
+GetProcessorLocation(
+  IN  UINT32  InitialApicId,
+  OUT UINT32  *Package  OPTIONAL,
+  OUT UINT32  *Core    OPTIONAL,
+  OUT UINT32  *Thread  OPTIONAL
+  )
+{
+  BOOLEAN                       TopologyLeafSupported;
+  UINTN                         ThreadBits;
+  UINTN                         CoreBits;
+  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
+  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
+  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
+  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
+  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
+  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
+  UINT32                        MaxCpuIdIndex;
+  UINT32                        SubIndex;
+  UINTN                         LevelType;
+  UINT32                        MaxLogicProcessorsPerPackage;
+  UINT32                        MaxCoresPerPackage;
+
+  //
+  // Check if the processor is capable of supporting more than one logical processor.
+  //
+  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
+  if (VersionInfoEdx.Bits.HTT == 0) {
+    if (Thread != NULL) {
+      *Thread  = 0;
+    }
+    if (Core != NULL) {
+      *Core    = 0;
+    }
+    if (Package != NULL) {
+      *Package = 0;
+    }
+    return;
+  }
+
+  ThreadBits = 0;
+  CoreBits = 0;
+
+  //
+  // Assume three-level mapping of APIC ID: Package:Core:SMT.
+  //
+  TopologyLeafSupported = FALSE;
+
+  //
+  // Get the max index of basic CPUID
+  //
+  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+  //
+  // If the extended topology enumeration leaf is available, it
+  // is the preferred mechanism for enumerating topology.
+  //
+  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+    AsmCpuidEx(
+      CPUID_EXTENDED_TOPOLOGY,
+      0,
+      &ExtendedTopologyEax.Uint32,
+      &ExtendedTopologyEbx.Uint32,
+      &ExtendedTopologyEcx.Uint32,
+      NULL
+      );
+    //
+    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
+    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
+    // supported on that processor.
+    //
+    if (ExtendedTopologyEbx.Uint32 != 0) {
+      TopologyLeafSupported = TRUE;
+
+      //
+      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
+      // the SMT sub-field of x2APIC ID.
+      //
+      LevelType = ExtendedTopologyEcx.Bits.LevelType;
+      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
+      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
+
+      //
+      // Software must not assume any "level type" encoding
+      // value to be related to any sub-leaf index, except sub-leaf 0.
+      //
+      SubIndex = 1;
+      do {
+        AsmCpuidEx(
+          CPUID_EXTENDED_TOPOLOGY,
+          SubIndex,
+          &ExtendedTopologyEax.Uint32,
+          NULL,
+          &ExtendedTopologyEcx.Uint32,
+          NULL
+          );
+        LevelType = ExtendedTopologyEcx.Bits.LevelType;
+        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
+          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
+          break;
+        }
+        SubIndex++;
+      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+    }
+  }
+
+  if (!TopologyLeafSupported) {
+    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
+      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+    }
+    else {
+      //
+      // Must be a single-core processor.
+      //
+      MaxCoresPerPackage = 1;
+    }
+
+    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
+
+  if (Thread != NULL) {
+    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
+  }
+  if (Core != NULL) {
+    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+  }
+  if (Package != NULL) {
+    *Package = (InitialApicId >> (ThreadBits + CoreBits));
+  }
+}
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 4c42696..a34a272 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -1036,3 +1036,149 @@ GetApicMsiValue (
   }
   return MsiData.Uint64;
 }
+
+/**
+  Get Package ID/Core ID/Thread ID of a processor.
+
+  The algorithm assumes the target system has symmetry across physical
+  package  boundaries with respect to the number of logical processors
+  per package,  number of cores per package.
+
+  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
+  @param[out]  Package       Returns the processor package ID.
+  @param[out]  Core          Returns the processor core ID.
+  @param[out]  Thread        Returns the processor thread ID.
+**/
+VOID
+GetProcessorLocation(
+  IN  UINT32  InitialApicId,
+  OUT UINT32  *Package  OPTIONAL,
+  OUT UINT32  *Core    OPTIONAL,
+  OUT UINT32  *Thread  OPTIONAL
+  )
+{
+  BOOLEAN                       TopologyLeafSupported;
+  UINTN                         ThreadBits;
+  UINTN                         CoreBits;
+  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
+  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
+  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
+  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
+  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
+  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
+  UINT32                        MaxCpuIdIndex;
+  UINT32                        SubIndex;
+  UINTN                         LevelType;
+  UINT32                        MaxLogicProcessorsPerPackage;
+  UINT32                        MaxCoresPerPackage;
+
+  //
+  // Check if the processor is capable of supporting more than one logical processor.
+  //
+  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
+  if (VersionInfoEdx.Bits.HTT == 0) {
+    if (Thread != NULL) {
+      *Thread  = 0;
+    }
+    if (Core != NULL) {
+      *Core    = 0;
+    }
+    if (Package != NULL) {
+      *Package = 0;
+    }
+    return;
+  }
+
+  ThreadBits = 0;
+  CoreBits = 0;
+
+  //
+  // Assume three-level mapping of APIC ID: Package:Core:SMT.
+  //
+  TopologyLeafSupported = FALSE;
+
+  //
+  // Get the max index of basic CPUID
+  //
+  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+  //
+  // If the extended topology enumeration leaf is available, it
+  // is the preferred mechanism for enumerating topology.
+  //
+  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+    AsmCpuidEx(
+      CPUID_EXTENDED_TOPOLOGY,
+      0,
+      &ExtendedTopologyEax.Uint32,
+      &ExtendedTopologyEbx.Uint32,
+      &ExtendedTopologyEcx.Uint32,
+      NULL
+      );
+    //
+    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
+    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
+    // supported on that processor.
+    //
+    if (ExtendedTopologyEbx.Uint32 != 0) {
+      TopologyLeafSupported = TRUE;
+
+      //
+      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
+      // the SMT sub-field of x2APIC ID.
+      //
+      LevelType = ExtendedTopologyEcx.Bits.LevelType;
+      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
+      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
+
+      //
+      // Software must not assume any "level type" encoding
+      // value to be related to any sub-leaf index, except sub-leaf 0.
+      //
+      SubIndex = 1;
+      do {
+        AsmCpuidEx(
+          CPUID_EXTENDED_TOPOLOGY,
+          SubIndex,
+          &ExtendedTopologyEax.Uint32,
+          NULL,
+          &ExtendedTopologyEcx.Uint32,
+          NULL
+          );
+        LevelType = ExtendedTopologyEcx.Bits.LevelType;
+        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
+          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
+          break;
+        }
+        SubIndex++;
+      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+    }
+  }
+
+  if (!TopologyLeafSupported) {
+    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
+      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+    }
+    else {
+      //
+      // Must be a single-core processor.
+      //
+      MaxCoresPerPackage = 1;
+    }
+
+    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
+
+  if (Thread != NULL) {
+    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
+  }
+  if (Core != NULL) {
+    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+  }
+  if (Package != NULL) {
+    *Package = (InitialApicId >> (ThreadBits + CoreBits));
+  }
+}
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index c3fe721..e48ff6a 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (
 }
 
 /**
-  Get CPU Package/Core/Thread location information.
-
-  @param[in]  InitialApicId     CPU APIC ID
-  @param[out] Location          Pointer to CPU location information
-**/
-VOID
-ExtractProcessorLocation (
-  IN  UINT32                     InitialApicId,
-  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
-  )
-{
-  BOOLEAN                        TopologyLeafSupported;
-  UINTN                          ThreadBits;
-  UINTN                          CoreBits;
-  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
-  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
-  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
-  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
-  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
-  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
-  UINT32                         MaxCpuIdIndex;
-  UINT32                         SubIndex;
-  UINTN                          LevelType;
-  UINT32                         MaxLogicProcessorsPerPackage;
-  UINT32                         MaxCoresPerPackage;
-
-  //
-  // Check if the processor is capable of supporting more than one logical processor.
-  //
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
-  if (VersionInfoEdx.Bits.HTT == 0) {
-    Location->Thread  = 0;
-    Location->Core    = 0;
-    Location->Package = 0;
-    return;
-  }
-
-  ThreadBits = 0;
-  CoreBits = 0;
-
-  //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
-  //
-
-  TopologyLeafSupported = FALSE;
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
-
-  //
-  // If the extended topology enumeration leaf is available, it
-  // is the preferred mechanism for enumerating topology.
-  //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
-    AsmCpuidEx (
-      CPUID_EXTENDED_TOPOLOGY,
-      0,
-      &ExtendedTopologyEax.Uint32,
-      &ExtendedTopologyEbx.Uint32,
-      &ExtendedTopologyEcx.Uint32,
-      NULL
-      );
-    //
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
-    // supported on that processor.
-    //
-    if (ExtendedTopologyEbx.Uint32 != 0) {
-      TopologyLeafSupported = TRUE;
-
-      //
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
-      // the SMT sub-field of x2APIC ID.
-      //
-      LevelType = ExtendedTopologyEcx.Bits.LevelType;
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
-      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
-
-      //
-      // Software must not assume any "level type" encoding
-      // value to be related to any sub-leaf index, except sub-leaf 0.
-      //
-      SubIndex = 1;
-      do {
-        AsmCpuidEx (
-          CPUID_EXTENDED_TOPOLOGY,
-          SubIndex,
-          &ExtendedTopologyEax.Uint32,
-          NULL,
-          &ExtendedTopologyEcx.Uint32,
-          NULL
-          );
-        LevelType = ExtendedTopologyEcx.Bits.LevelType;
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
-          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
-          break;
-        }
-        SubIndex++;
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
-    }
-  }
-
-  if (!TopologyLeafSupported) {
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
-    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
-      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
-    } else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
-    }
-
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
-  }
-
-  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
-  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
-  Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
-}
-
-/**
   Worker function for SwitchBSP().
 
   Worker function for SwitchBSP(), assigned to the AP which is intended
@@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo (
   //
   // Get processor location information
   //
-  ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
+  GetProcessorLocation (
+    CpuMpData->CpuData[ProcessorNumber].ApicId,
+    &ProcessorInfoBuffer->Location.Package,
+    &ProcessorInfoBuffer->Location.Core,
+    &ProcessorInfoBuffer->Location.Thread
+    );
 
   if (HealthData != NULL) {
     HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
index 40f2a17..f377a36 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
@@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {
 };
 
 /**
-  Get Package ID/Core ID/Thread ID of a processor.
-
-  APIC ID must be an initial APIC ID.
-
-  The algorithm below assumes the target system has symmetry across physical package boundaries
-  with respect to the number of logical processors per package, number of cores per package.
-
-  @param  ApicId    APIC ID of the target logical processor.
-  @param  Location    Returns the processor location information.
-**/
-VOID
-SmmGetProcessorLocation (
-  IN UINT32 ApicId,
-  OUT EFI_CPU_PHYSICAL_LOCATION *Location
-  )
-{
-  UINTN   ThreadBits;
-  UINTN   CoreBits;
-  UINT32  RegEax;
-  UINT32  RegEbx;
-  UINT32  RegEcx;
-  UINT32  RegEdx;
-  UINT32  MaxCpuIdIndex;
-  UINT32  SubIndex;
-  UINTN   LevelType;
-  UINT32  MaxLogicProcessorsPerPackage;
-  UINT32  MaxCoresPerPackage;
-  BOOLEAN TopologyLeafSupported;
-
-  ASSERT (Location != NULL);
-
-  ThreadBits            = 0;
-  CoreBits              = 0;
-  TopologyLeafSupported = FALSE;
-
-  //
-  // Check if the processor is capable of supporting more than one logical processor.
-  //
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
-  ASSERT ((RegEdx & BIT28) != 0);
-
-  //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
-  //
-
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
-
-  //
-  // If the extended topology enumeration leaf is available, it
-  // is the preferred mechanism for enumerating topology.
-  //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
-    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
-    //
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
-    // supported on that processor.
-    //
-    if ((RegEbx & 0xffff) != 0) {
-      TopologyLeafSupported = TRUE;
-
-      //
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
-      // the SMT sub-field of x2APIC ID.
-      //
-      LevelType = (RegEcx >> 8) & 0xff;
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
-      if ((RegEbx & 0xffff) > 1 ) {
-        ThreadBits = RegEax & 0x1f;
-      } else {
-        //
-        // HT is not supported
-        //
-        ThreadBits = 0;
-      }
-
-      //
-      // Software must not assume any "level type" encoding
-      // value to be related to any sub-leaf index, except sub-leaf 0.
-      //
-      SubIndex = 1;
-      do {
-        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);
-        LevelType = (RegEcx >> 8) & 0xff;
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
-          CoreBits = (RegEax & 0x1f) - ThreadBits;
-          break;
-        }
-        SubIndex++;
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
-    }
-  }
-
-  if (!TopologyLeafSupported) {
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
-    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
-      MaxCoresPerPackage = (RegEax >> 26) + 1;
-    } else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
-    }
-
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
-  }
-
-  Location->Thread = ApicId & ~((-1) << ThreadBits);
-  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
-  Location->Package = (ApicId >> (ThreadBits+ CoreBits));
-}
-
-/**
   Gets processor information on the requested processor at the instant this call is made.
 
   @param[in]  This                 A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@@ -280,7 +161,12 @@ SmmAddProcessor (
         gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
       gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
       gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
-      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
+      GetProcessorLocation (
+        (UINT32)ProcessorId,
+        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,
+        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core,
+        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread
+        );
 
       *ProcessorNumber = Index;
       gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
-- 
1.9.1



^ permalink raw reply related	[flat|nested] 11+ messages in thread

* Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
  2016-10-31 19:42 [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Leo Duran
@ 2016-10-31 21:23 ` Laszlo Ersek
  2016-10-31 21:26   ` Duran, Leo
  2016-10-31 21:29   ` Kinney, Michael D
  2016-11-01  2:25 ` Fan, Jeff
  1 sibling, 2 replies; 11+ messages in thread
From: Laszlo Ersek @ 2016-10-31 21:23 UTC (permalink / raw)
  To: Leo Duran, edk2-devel; +Cc: liming.gao, jeff.fan, michael.d.kinney

On 10/31/16 20:42, Leo Duran wrote:
> 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
> 2) Remove ExtractProcessorLocation() from MpInitLib library.
> 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran  <leo.duran@amd.com>
> ---
>  UefiCpuPkg/Include/Library/LocalApicLib.h          |  20 +++
>  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 146 +++++++++++++++++++++
>  .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 146 +++++++++++++++++++++
>  UefiCpuPkg/Library/MpInitLib/MpLib.c               | 133 +------------------
>  UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 126 +-----------------
>  5 files changed, 324 insertions(+), 247 deletions(-)

(1) This patch should carry a "Signed-off-by" from Mike as well -- it is
my understanding that this v4 patch is the result of joint work (it
contains new code from two people).

I don't think it's necessary to repost the patch for this: if Mike
responds with his S-o-b, then I believe Jeff can simply add that tag as
well at commit time.

(2) I repeated my tests as described in
<https://lists.01.org/pipermail/edk2-devel/2016-October/003807.html>;
the v4 patch too works fine.

Tested-by: Laszlo Ersek <lersek@redhat.com>

Thanks
Laszlo

> diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
> index cd4e613..179409e 100644
> --- a/UefiCpuPkg/Include/Library/LocalApicLib.h
> +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
> @@ -410,6 +410,26 @@ GetApicMsiValue (
>    IN BOOLEAN  LevelTriggered,
>    IN BOOLEAN  AssertionLevel
>    );
> +
> +/**
> +  Get Package ID/Core ID/Thread ID of a processor.
> +
> +  The algorithm assumes the target system has symmetry across physical
> +  package  boundaries with respect to the number of logical processors
> +  per package,  number of cores per package.
> +
> +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> +  @param[out]  Package       Returns the processor package ID.
> +  @param[out]  Core          Returns the processor core ID.
> +  @param[out]  Thread        Returns the processor thread ID.
> +**/
> +VOID
> +GetProcessorLocation(
> +  IN  UINT32  InitialApicId,
> +  OUT UINT32  *Package  OPTIONAL,
> +  OUT UINT32  *Core    OPTIONAL,
> +  OUT UINT32  *Thread  OPTIONAL
> +  );
>    
>  #endif
>  
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> index 8d0fb02..f32d287 100644
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> @@ -941,3 +941,149 @@ GetApicMsiValue (
>    }
>    return MsiData.Uint64;
>  }
> +
> +/**
> +  Get Package ID/Core ID/Thread ID of a processor.
> +
> +  The algorithm assumes the target system has symmetry across physical
> +  package  boundaries with respect to the number of logical processors
> +  per package,  number of cores per package.
> +
> +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> +  @param[out]  Package       Returns the processor package ID.
> +  @param[out]  Core          Returns the processor core ID.
> +  @param[out]  Thread        Returns the processor thread ID.
> +**/
> +VOID
> +GetProcessorLocation(
> +  IN  UINT32  InitialApicId,
> +  OUT UINT32  *Package  OPTIONAL,
> +  OUT UINT32  *Core    OPTIONAL,
> +  OUT UINT32  *Thread  OPTIONAL
> +  )
> +{
> +  BOOLEAN                       TopologyLeafSupported;
> +  UINTN                         ThreadBits;
> +  UINTN                         CoreBits;
> +  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
> +  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
> +  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
> +  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
> +  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
> +  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
> +  UINT32                        MaxCpuIdIndex;
> +  UINT32                        SubIndex;
> +  UINTN                         LevelType;
> +  UINT32                        MaxLogicProcessorsPerPackage;
> +  UINT32                        MaxCoresPerPackage;
> +
> +  //
> +  // Check if the processor is capable of supporting more than one logical processor.
> +  //
> +  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> +  if (VersionInfoEdx.Bits.HTT == 0) {
> +    if (Thread != NULL) {
> +      *Thread  = 0;
> +    }
> +    if (Core != NULL) {
> +      *Core    = 0;
> +    }
> +    if (Package != NULL) {
> +      *Package = 0;
> +    }
> +    return;
> +  }
> +
> +  ThreadBits = 0;
> +  CoreBits = 0;
> +
> +  //
> +  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> +  //
> +  TopologyLeafSupported = FALSE;
> +
> +  //
> +  // Get the max index of basic CPUID
> +  //
> +  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> +
> +  //
> +  // If the extended topology enumeration leaf is available, it
> +  // is the preferred mechanism for enumerating topology.
> +  //
> +  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> +    AsmCpuidEx(
> +      CPUID_EXTENDED_TOPOLOGY,
> +      0,
> +      &ExtendedTopologyEax.Uint32,
> +      &ExtendedTopologyEbx.Uint32,
> +      &ExtendedTopologyEcx.Uint32,
> +      NULL
> +      );
> +    //
> +    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> +    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> +    // supported on that processor.
> +    //
> +    if (ExtendedTopologyEbx.Uint32 != 0) {
> +      TopologyLeafSupported = TRUE;
> +
> +      //
> +      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> +      // the SMT sub-field of x2APIC ID.
> +      //
> +      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> +      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> +
> +      //
> +      // Software must not assume any "level type" encoding
> +      // value to be related to any sub-leaf index, except sub-leaf 0.
> +      //
> +      SubIndex = 1;
> +      do {
> +        AsmCpuidEx(
> +          CPUID_EXTENDED_TOPOLOGY,
> +          SubIndex,
> +          &ExtendedTopologyEax.Uint32,
> +          NULL,
> +          &ExtendedTopologyEcx.Uint32,
> +          NULL
> +          );
> +        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> +          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> +          break;
> +        }
> +        SubIndex++;
> +      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> +    }
> +  }
> +
> +  if (!TopologyLeafSupported) {
> +    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> +    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> +      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> +      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> +    }
> +    else {
> +      //
> +      // Must be a single-core processor.
> +      //
> +      MaxCoresPerPackage = 1;
> +    }
> +
> +    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> +    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
> +
> +  if (Thread != NULL) {
> +    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> +  }
> +  if (Core != NULL) {
> +    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> +  }
> +  if (Package != NULL) {
> +    *Package = (InitialApicId >> (ThreadBits + CoreBits));
> +  }
> +}
> diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> index 4c42696..a34a272 100644
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> @@ -1036,3 +1036,149 @@ GetApicMsiValue (
>    }
>    return MsiData.Uint64;
>  }
> +
> +/**
> +  Get Package ID/Core ID/Thread ID of a processor.
> +
> +  The algorithm assumes the target system has symmetry across physical
> +  package  boundaries with respect to the number of logical processors
> +  per package,  number of cores per package.
> +
> +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> +  @param[out]  Package       Returns the processor package ID.
> +  @param[out]  Core          Returns the processor core ID.
> +  @param[out]  Thread        Returns the processor thread ID.
> +**/
> +VOID
> +GetProcessorLocation(
> +  IN  UINT32  InitialApicId,
> +  OUT UINT32  *Package  OPTIONAL,
> +  OUT UINT32  *Core    OPTIONAL,
> +  OUT UINT32  *Thread  OPTIONAL
> +  )
> +{
> +  BOOLEAN                       TopologyLeafSupported;
> +  UINTN                         ThreadBits;
> +  UINTN                         CoreBits;
> +  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
> +  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
> +  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
> +  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
> +  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
> +  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
> +  UINT32                        MaxCpuIdIndex;
> +  UINT32                        SubIndex;
> +  UINTN                         LevelType;
> +  UINT32                        MaxLogicProcessorsPerPackage;
> +  UINT32                        MaxCoresPerPackage;
> +
> +  //
> +  // Check if the processor is capable of supporting more than one logical processor.
> +  //
> +  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> +  if (VersionInfoEdx.Bits.HTT == 0) {
> +    if (Thread != NULL) {
> +      *Thread  = 0;
> +    }
> +    if (Core != NULL) {
> +      *Core    = 0;
> +    }
> +    if (Package != NULL) {
> +      *Package = 0;
> +    }
> +    return;
> +  }
> +
> +  ThreadBits = 0;
> +  CoreBits = 0;
> +
> +  //
> +  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> +  //
> +  TopologyLeafSupported = FALSE;
> +
> +  //
> +  // Get the max index of basic CPUID
> +  //
> +  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> +
> +  //
> +  // If the extended topology enumeration leaf is available, it
> +  // is the preferred mechanism for enumerating topology.
> +  //
> +  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> +    AsmCpuidEx(
> +      CPUID_EXTENDED_TOPOLOGY,
> +      0,
> +      &ExtendedTopologyEax.Uint32,
> +      &ExtendedTopologyEbx.Uint32,
> +      &ExtendedTopologyEcx.Uint32,
> +      NULL
> +      );
> +    //
> +    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> +    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> +    // supported on that processor.
> +    //
> +    if (ExtendedTopologyEbx.Uint32 != 0) {
> +      TopologyLeafSupported = TRUE;
> +
> +      //
> +      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> +      // the SMT sub-field of x2APIC ID.
> +      //
> +      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> +      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> +
> +      //
> +      // Software must not assume any "level type" encoding
> +      // value to be related to any sub-leaf index, except sub-leaf 0.
> +      //
> +      SubIndex = 1;
> +      do {
> +        AsmCpuidEx(
> +          CPUID_EXTENDED_TOPOLOGY,
> +          SubIndex,
> +          &ExtendedTopologyEax.Uint32,
> +          NULL,
> +          &ExtendedTopologyEcx.Uint32,
> +          NULL
> +          );
> +        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> +        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> +          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> +          break;
> +        }
> +        SubIndex++;
> +      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> +    }
> +  }
> +
> +  if (!TopologyLeafSupported) {
> +    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> +    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> +      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> +      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> +    }
> +    else {
> +      //
> +      // Must be a single-core processor.
> +      //
> +      MaxCoresPerPackage = 1;
> +    }
> +
> +    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> +    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
> +
> +  if (Thread != NULL) {
> +    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> +  }
> +  if (Core != NULL) {
> +    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> +  }
> +  if (Package != NULL) {
> +    *Package = (InitialApicId >> (ThreadBits + CoreBits));
> +  }
> +}
> diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> index c3fe721..e48ff6a 100644
> --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (
>  }
>  
>  /**
> -  Get CPU Package/Core/Thread location information.
> -
> -  @param[in]  InitialApicId     CPU APIC ID
> -  @param[out] Location          Pointer to CPU location information
> -**/
> -VOID
> -ExtractProcessorLocation (
> -  IN  UINT32                     InitialApicId,
> -  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> -  )
> -{
> -  BOOLEAN                        TopologyLeafSupported;
> -  UINTN                          ThreadBits;
> -  UINTN                          CoreBits;
> -  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> -  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> -  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> -  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> -  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> -  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> -  UINT32                         MaxCpuIdIndex;
> -  UINT32                         SubIndex;
> -  UINTN                          LevelType;
> -  UINT32                         MaxLogicProcessorsPerPackage;
> -  UINT32                         MaxCoresPerPackage;
> -
> -  //
> -  // Check if the processor is capable of supporting more than one logical processor.
> -  //
> -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> -  if (VersionInfoEdx.Bits.HTT == 0) {
> -    Location->Thread  = 0;
> -    Location->Core    = 0;
> -    Location->Package = 0;
> -    return;
> -  }
> -
> -  ThreadBits = 0;
> -  CoreBits = 0;
> -
> -  //
> -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> -  //
> -
> -  TopologyLeafSupported = FALSE;
> -  //
> -  // Get the max index of basic CPUID
> -  //
> -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> -
> -  //
> -  // If the extended topology enumeration leaf is available, it
> -  // is the preferred mechanism for enumerating topology.
> -  //
> -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> -    AsmCpuidEx (
> -      CPUID_EXTENDED_TOPOLOGY,
> -      0,
> -      &ExtendedTopologyEax.Uint32,
> -      &ExtendedTopologyEbx.Uint32,
> -      &ExtendedTopologyEcx.Uint32,
> -      NULL
> -      );
> -    //
> -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> -    // supported on that processor.
> -    //
> -    if (ExtendedTopologyEbx.Uint32 != 0) {
> -      TopologyLeafSupported = TRUE;
> -
> -      //
> -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> -      // the SMT sub-field of x2APIC ID.
> -      //
> -      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> -      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> -      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> -
> -      //
> -      // Software must not assume any "level type" encoding
> -      // value to be related to any sub-leaf index, except sub-leaf 0.
> -      //
> -      SubIndex = 1;
> -      do {
> -        AsmCpuidEx (
> -          CPUID_EXTENDED_TOPOLOGY,
> -          SubIndex,
> -          &ExtendedTopologyEax.Uint32,
> -          NULL,
> -          &ExtendedTopologyEcx.Uint32,
> -          NULL
> -          );
> -        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> -          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> -          break;
> -        }
> -        SubIndex++;
> -      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> -    }
> -  }
> -
> -  if (!TopologyLeafSupported) {
> -    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> -    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> -      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> -    } else {
> -      //
> -      // Must be a single-core processor.
> -      //
> -      MaxCoresPerPackage = 1;
> -    }
> -
> -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> -  }
> -
> -  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> -  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> -  Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
> -}
> -
> -/**
>    Worker function for SwitchBSP().
>  
>    Worker function for SwitchBSP(), assigned to the AP which is intended
> @@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo (
>    //
>    // Get processor location information
>    //
> -  ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
> +  GetProcessorLocation (
> +    CpuMpData->CpuData[ProcessorNumber].ApicId,
> +    &ProcessorInfoBuffer->Location.Package,
> +    &ProcessorInfoBuffer->Location.Core,
> +    &ProcessorInfoBuffer->Location.Thread
> +    );
>  
>    if (HealthData != NULL) {
>      HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> index 40f2a17..f377a36 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {
>  };
>  
>  /**
> -  Get Package ID/Core ID/Thread ID of a processor.
> -
> -  APIC ID must be an initial APIC ID.
> -
> -  The algorithm below assumes the target system has symmetry across physical package boundaries
> -  with respect to the number of logical processors per package, number of cores per package.
> -
> -  @param  ApicId    APIC ID of the target logical processor.
> -  @param  Location    Returns the processor location information.
> -**/
> -VOID
> -SmmGetProcessorLocation (
> -  IN UINT32 ApicId,
> -  OUT EFI_CPU_PHYSICAL_LOCATION *Location
> -  )
> -{
> -  UINTN   ThreadBits;
> -  UINTN   CoreBits;
> -  UINT32  RegEax;
> -  UINT32  RegEbx;
> -  UINT32  RegEcx;
> -  UINT32  RegEdx;
> -  UINT32  MaxCpuIdIndex;
> -  UINT32  SubIndex;
> -  UINTN   LevelType;
> -  UINT32  MaxLogicProcessorsPerPackage;
> -  UINT32  MaxCoresPerPackage;
> -  BOOLEAN TopologyLeafSupported;
> -
> -  ASSERT (Location != NULL);
> -
> -  ThreadBits            = 0;
> -  CoreBits              = 0;
> -  TopologyLeafSupported = FALSE;
> -
> -  //
> -  // Check if the processor is capable of supporting more than one logical processor.
> -  //
> -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
> -  ASSERT ((RegEdx & BIT28) != 0);
> -
> -  //
> -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> -  //
> -
> -  //
> -  // Get the max index of basic CPUID
> -  //
> -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> -
> -  //
> -  // If the extended topology enumeration leaf is available, it
> -  // is the preferred mechanism for enumerating topology.
> -  //
> -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> -    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
> -    //
> -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> -    // supported on that processor.
> -    //
> -    if ((RegEbx & 0xffff) != 0) {
> -      TopologyLeafSupported = TRUE;
> -
> -      //
> -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
> -      // the SMT sub-field of x2APIC ID.
> -      //
> -      LevelType = (RegEcx >> 8) & 0xff;
> -      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> -      if ((RegEbx & 0xffff) > 1 ) {
> -        ThreadBits = RegEax & 0x1f;
> -      } else {
> -        //
> -        // HT is not supported
> -        //
> -        ThreadBits = 0;
> -      }
> -
> -      //
> -      // Software must not assume any "level type" encoding
> -      // value to be related to any sub-leaf index, except sub-leaf 0.
> -      //
> -      SubIndex = 1;
> -      do {
> -        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);
> -        LevelType = (RegEcx >> 8) & 0xff;
> -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> -          CoreBits = (RegEax & 0x1f) - ThreadBits;
> -          break;
> -        }
> -        SubIndex++;
> -      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> -    }
> -  }
> -
> -  if (!TopologyLeafSupported) {
> -    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
> -    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
> -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
> -      MaxCoresPerPackage = (RegEax >> 26) + 1;
> -    } else {
> -      //
> -      // Must be a single-core processor.
> -      //
> -      MaxCoresPerPackage = 1;
> -    }
> -
> -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
> -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> -  }
> -
> -  Location->Thread = ApicId & ~((-1) << ThreadBits);
> -  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
> -  Location->Package = (ApicId >> (ThreadBits+ CoreBits));
> -}
> -
> -/**
>    Gets processor information on the requested processor at the instant this call is made.
>  
>    @param[in]  This                 A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
> @@ -280,7 +161,12 @@ SmmAddProcessor (
>          gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
>        gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
>        gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
> -      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
> +      GetProcessorLocation (
> +        (UINT32)ProcessorId,
> +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,
> +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core,
> +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread
> +        );
>  
>        *ProcessorNumber = Index;
>        gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
> 



^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
  2016-10-31 21:23 ` Laszlo Ersek
@ 2016-10-31 21:26   ` Duran, Leo
  2016-10-31 21:29   ` Kinney, Michael D
  1 sibling, 0 replies; 11+ messages in thread
From: Duran, Leo @ 2016-10-31 21:26 UTC (permalink / raw)
  To: 'Laszlo Ersek', edk2-devel@ml01.01.org
  Cc: liming.gao@intel.com, jeff.fan@intel.com,
	michael.d.kinney@intel.com



> -----Original Message-----
> From: Laszlo Ersek [mailto:lersek@redhat.com]
> Sent: Monday, October 31, 2016 4:24 PM
> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@ml01.01.org
> Cc: liming.gao@intel.com; jeff.fan@intel.com; michael.d.kinney@intel.com
> Subject: Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to
> LocalApicLib library
> 
> On 10/31/16 20:42, Leo Duran wrote:
> > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
> > 2) Remove ExtractProcessorLocation() from MpInitLib library.
> > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Leo Duran  <leo.duran@amd.com>
> > ---
> >  UefiCpuPkg/Include/Library/LocalApicLib.h          |  20 +++
> >  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 146
> +++++++++++++++++++++
> >  .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 146
> +++++++++++++++++++++
> >  UefiCpuPkg/Library/MpInitLib/MpLib.c               | 133 +------------------
> >  UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 126 +-----------------
> >  5 files changed, 324 insertions(+), 247 deletions(-)
> 
> (1) This patch should carry a "Signed-off-by" from Mike as well -- it is my
> understanding that this v4 patch is the result of joint work (it contains new
> code from two people).
> 
> I don't think it's necessary to repost the patch for this: if Mike responds with
> his S-o-b, then I believe Jeff can simply add that tag as well at commit time.
> 
[Duran, Leo] 
Yes, please make that happen. Thanks.

> (2) I repeated my tests as described in
> <https://lists.01.org/pipermail/edk2-devel/2016-October/003807.html>;
> the v4 patch too works fine.
> 
> Tested-by: Laszlo Ersek <lersek@redhat.com>
> 
[Duran, Leo] 
Great, thanks.

> Thanks
> Laszlo
> 
> > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h
> > b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > index cd4e613..179409e 100644
> > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h
> > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > @@ -410,6 +410,26 @@ GetApicMsiValue (
> >    IN BOOLEAN  LevelTriggered,
> >    IN BOOLEAN  AssertionLevel
> >    );
> > +
> > +/**
> > +  Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +  The algorithm assumes the target system has symmetry across
> > + physical  package  boundaries with respect to the number of logical
> > + processors  per package,  number of cores per package.
> > +
> > +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> > +  @param[out]  Package       Returns the processor package ID.
> > +  @param[out]  Core          Returns the processor core ID.
> > +  @param[out]  Thread        Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN  UINT32  InitialApicId,
> > +  OUT UINT32  *Package  OPTIONAL,
> > +  OUT UINT32  *Core    OPTIONAL,
> > +  OUT UINT32  *Thread  OPTIONAL
> > +  );
> >
> >  #endif
> >
> > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > index 8d0fb02..f32d287 100644
> > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > @@ -941,3 +941,149 @@ GetApicMsiValue (
> >    }
> >    return MsiData.Uint64;
> >  }
> > +
> > +/**
> > +  Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +  The algorithm assumes the target system has symmetry across
> > + physical  package  boundaries with respect to the number of logical
> > + processors  per package,  number of cores per package.
> > +
> > +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> > +  @param[out]  Package       Returns the processor package ID.
> > +  @param[out]  Core          Returns the processor core ID.
> > +  @param[out]  Thread        Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN  UINT32  InitialApicId,
> > +  OUT UINT32  *Package  OPTIONAL,
> > +  OUT UINT32  *Core    OPTIONAL,
> > +  OUT UINT32  *Thread  OPTIONAL
> > +  )
> > +{
> > +  BOOLEAN                       TopologyLeafSupported;
> > +  UINTN                         ThreadBits;
> > +  UINTN                         CoreBits;
> > +  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
> > +  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
> > +  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
> > +  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
> > +  UINT32                        MaxCpuIdIndex;
> > +  UINT32                        SubIndex;
> > +  UINTN                         LevelType;
> > +  UINT32                        MaxLogicProcessorsPerPackage;
> > +  UINT32                        MaxCoresPerPackage;
> > +
> > +  //
> > +  // Check if the processor is capable of supporting more than one logical
> processor.
> > +  //
> > +  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> > + &VersionInfoEdx.Uint32);  if (VersionInfoEdx.Bits.HTT == 0) {
> > +    if (Thread != NULL) {
> > +      *Thread  = 0;
> > +    }
> > +    if (Core != NULL) {
> > +      *Core    = 0;
> > +    }
> > +    if (Package != NULL) {
> > +      *Package = 0;
> > +    }
> > +    return;
> > +  }
> > +
> > +  ThreadBits = 0;
> > +  CoreBits = 0;
> > +
> > +  //
> > +  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > +  //
> > +  TopologyLeafSupported = FALSE;
> > +
> > +  //
> > +  // Get the max index of basic CPUID  //  AsmCpuid(CPUID_SIGNATURE,
> > + &MaxCpuIdIndex, NULL, NULL, NULL);
> > +
> > +  //
> > +  // If the extended topology enumeration leaf is available, it  //
> > + is the preferred mechanism for enumerating topology.
> > +  //
> > +  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > +    AsmCpuidEx(
> > +      CPUID_EXTENDED_TOPOLOGY,
> > +      0,
> > +      &ExtendedTopologyEax.Uint32,
> > +      &ExtendedTopologyEbx.Uint32,
> > +      &ExtendedTopologyEcx.Uint32,
> > +      NULL
> > +      );
> > +    //
> > +    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > +    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > +    // supported on that processor.
> > +    //
> > +    if (ExtendedTopologyEbx.Uint32 != 0) {
> > +      TopologyLeafSupported = TRUE;
> > +
> > +      //
> > +      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > +      // the SMT sub-field of x2APIC ID.
> > +      //
> > +      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +      ASSERT(LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > +      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > +      //
> > +      // Software must not assume any "level type" encoding
> > +      // value to be related to any sub-leaf index, except sub-leaf 0.
> > +      //
> > +      SubIndex = 1;
> > +      do {
> > +        AsmCpuidEx(
> > +          CPUID_EXTENDED_TOPOLOGY,
> > +          SubIndex,
> > +          &ExtendedTopologyEax.Uint32,
> > +          NULL,
> > +          &ExtendedTopologyEcx.Uint32,
> > +          NULL
> > +          );
> > +        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > +          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > +          break;
> > +        }
> > +        SubIndex++;
> > +      } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > +    }
> > +  }
> > +
> > +  if (!TopologyLeafSupported) {
> > +    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32,
> NULL, NULL);
> > +    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > +      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> > +      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > +    }
> > +    else {
> > +      //
> > +      // Must be a single-core processor.
> > +      //
> > +      MaxCoresPerPackage = 1;
> > +    }
> > +
> > +    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > +    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
> > +
> > +  if (Thread != NULL) {
> > +    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > +  }
> > +  if (Core != NULL) {
> > +    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > +  }
> > +  if (Package != NULL) {
> > +    *Package = (InitialApicId >> (ThreadBits + CoreBits));
> > +  }
> > +}
> > diff --git
> > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > index 4c42696..a34a272 100644
> > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > @@ -1036,3 +1036,149 @@ GetApicMsiValue (
> >    }
> >    return MsiData.Uint64;
> >  }
> > +
> > +/**
> > +  Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +  The algorithm assumes the target system has symmetry across
> > + physical  package  boundaries with respect to the number of logical
> > + processors  per package,  number of cores per package.
> > +
> > +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> > +  @param[out]  Package       Returns the processor package ID.
> > +  @param[out]  Core          Returns the processor core ID.
> > +  @param[out]  Thread        Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN  UINT32  InitialApicId,
> > +  OUT UINT32  *Package  OPTIONAL,
> > +  OUT UINT32  *Core    OPTIONAL,
> > +  OUT UINT32  *Thread  OPTIONAL
> > +  )
> > +{
> > +  BOOLEAN                       TopologyLeafSupported;
> > +  UINTN                         ThreadBits;
> > +  UINTN                         CoreBits;
> > +  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
> > +  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
> > +  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
> > +  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
> > +  UINT32                        MaxCpuIdIndex;
> > +  UINT32                        SubIndex;
> > +  UINTN                         LevelType;
> > +  UINT32                        MaxLogicProcessorsPerPackage;
> > +  UINT32                        MaxCoresPerPackage;
> > +
> > +  //
> > +  // Check if the processor is capable of supporting more than one logical
> processor.
> > +  //
> > +  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> > + &VersionInfoEdx.Uint32);  if (VersionInfoEdx.Bits.HTT == 0) {
> > +    if (Thread != NULL) {
> > +      *Thread  = 0;
> > +    }
> > +    if (Core != NULL) {
> > +      *Core    = 0;
> > +    }
> > +    if (Package != NULL) {
> > +      *Package = 0;
> > +    }
> > +    return;
> > +  }
> > +
> > +  ThreadBits = 0;
> > +  CoreBits = 0;
> > +
> > +  //
> > +  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > +  //
> > +  TopologyLeafSupported = FALSE;
> > +
> > +  //
> > +  // Get the max index of basic CPUID  //  AsmCpuid(CPUID_SIGNATURE,
> > + &MaxCpuIdIndex, NULL, NULL, NULL);
> > +
> > +  //
> > +  // If the extended topology enumeration leaf is available, it  //
> > + is the preferred mechanism for enumerating topology.
> > +  //
> > +  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > +    AsmCpuidEx(
> > +      CPUID_EXTENDED_TOPOLOGY,
> > +      0,
> > +      &ExtendedTopologyEax.Uint32,
> > +      &ExtendedTopologyEbx.Uint32,
> > +      &ExtendedTopologyEcx.Uint32,
> > +      NULL
> > +      );
> > +    //
> > +    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > +    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > +    // supported on that processor.
> > +    //
> > +    if (ExtendedTopologyEbx.Uint32 != 0) {
> > +      TopologyLeafSupported = TRUE;
> > +
> > +      //
> > +      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > +      // the SMT sub-field of x2APIC ID.
> > +      //
> > +      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +      ASSERT(LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > +      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > +      //
> > +      // Software must not assume any "level type" encoding
> > +      // value to be related to any sub-leaf index, except sub-leaf 0.
> > +      //
> > +      SubIndex = 1;
> > +      do {
> > +        AsmCpuidEx(
> > +          CPUID_EXTENDED_TOPOLOGY,
> > +          SubIndex,
> > +          &ExtendedTopologyEax.Uint32,
> > +          NULL,
> > +          &ExtendedTopologyEcx.Uint32,
> > +          NULL
> > +          );
> > +        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > +          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > +          break;
> > +        }
> > +        SubIndex++;
> > +      } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > +    }
> > +  }
> > +
> > +  if (!TopologyLeafSupported) {
> > +    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32,
> NULL, NULL);
> > +    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > +      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> > +      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > +    }
> > +    else {
> > +      //
> > +      // Must be a single-core processor.
> > +      //
> > +      MaxCoresPerPackage = 1;
> > +    }
> > +
> > +    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > +    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
> > +
> > +  if (Thread != NULL) {
> > +    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > +  }
> > +  if (Core != NULL) {
> > +    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > +  }
> > +  if (Package != NULL) {
> > +    *Package = (InitialApicId >> (ThreadBits + CoreBits));
> > +  }
> > +}
> > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > index c3fe721..e48ff6a 100644
> > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (  }
> >
> >  /**
> > -  Get CPU Package/Core/Thread location information.
> > -
> > -  @param[in]  InitialApicId     CPU APIC ID
> > -  @param[out] Location          Pointer to CPU location information
> > -**/
> > -VOID
> > -ExtractProcessorLocation (
> > -  IN  UINT32                     InitialApicId,
> > -  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> > -  )
> > -{
> > -  BOOLEAN                        TopologyLeafSupported;
> > -  UINTN                          ThreadBits;
> > -  UINTN                          CoreBits;
> > -  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> > -  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> > -  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> > -  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> > -  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> > -  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> > -  UINT32                         MaxCpuIdIndex;
> > -  UINT32                         SubIndex;
> > -  UINTN                          LevelType;
> > -  UINT32                         MaxLogicProcessorsPerPackage;
> > -  UINT32                         MaxCoresPerPackage;
> > -
> > -  //
> > -  // Check if the processor is capable of supporting more than one logical
> processor.
> > -  //
> > -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL,
> > &VersionInfoEdx.Uint32);
> > -  if (VersionInfoEdx.Bits.HTT == 0) {
> > -    Location->Thread  = 0;
> > -    Location->Core    = 0;
> > -    Location->Package = 0;
> > -    return;
> > -  }
> > -
> > -  ThreadBits = 0;
> > -  CoreBits = 0;
> > -
> > -  //
> > -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > -  //
> > -
> > -  TopologyLeafSupported = FALSE;
> > -  //
> > -  // Get the max index of basic CPUID
> > -  //
> > -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > -  //
> > -  // If the extended topology enumeration leaf is available, it
> > -  // is the preferred mechanism for enumerating topology.
> > -  //
> > -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > -    AsmCpuidEx (
> > -      CPUID_EXTENDED_TOPOLOGY,
> > -      0,
> > -      &ExtendedTopologyEax.Uint32,
> > -      &ExtendedTopologyEbx.Uint32,
> > -      &ExtendedTopologyEcx.Uint32,
> > -      NULL
> > -      );
> > -    //
> > -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > -    // supported on that processor.
> > -    //
> > -    if (ExtendedTopologyEbx.Uint32 != 0) {
> > -      TopologyLeafSupported = TRUE;
> > -
> > -      //
> > -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > -      // the SMT sub-field of x2APIC ID.
> > -      //
> > -      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > -      ASSERT (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > -      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > -
> > -      //
> > -      // Software must not assume any "level type" encoding
> > -      // value to be related to any sub-leaf index, except sub-leaf 0.
> > -      //
> > -      SubIndex = 1;
> > -      do {
> > -        AsmCpuidEx (
> > -          CPUID_EXTENDED_TOPOLOGY,
> > -          SubIndex,
> > -          &ExtendedTopologyEax.Uint32,
> > -          NULL,
> > -          &ExtendedTopologyEcx.Uint32,
> > -          NULL
> > -          );
> > -        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > -          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > -          break;
> > -        }
> > -        SubIndex++;
> > -      } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > -    }
> > -  }
> > -
> > -  if (!TopologyLeafSupported) {
> > -    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32,
> NULL, NULL);
> > -    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> > -      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > -    } else {
> > -      //
> > -      // Must be a single-core processor.
> > -      //
> > -      MaxCoresPerPackage = 1;
> > -    }
> > -
> > -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > -  }
> > -
> > -  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > -  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > -  Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); -}
> > -
> > -/**
> >    Worker function for SwitchBSP().
> >
> >    Worker function for SwitchBSP(), assigned to the AP which is
> > intended @@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo (
> >    //
> >    // Get processor location information
> >    //
> > -  ExtractProcessorLocation
> > (CpuMpData->CpuData[ProcessorNumber].ApicId,
> > &ProcessorInfoBuffer->Location);
> > +  GetProcessorLocation (
> > +    CpuMpData->CpuData[ProcessorNumber].ApicId,
> > +    &ProcessorInfoBuffer->Location.Package,
> > +    &ProcessorInfoBuffer->Location.Core,
> > +    &ProcessorInfoBuffer->Location.Thread
> > +    );
> >
> >    if (HealthData != NULL) {
> >      HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
> > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > index 40f2a17..f377a36 100644
> > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL
> mSmmCpuService = {
> > };
> >
> >  /**
> > -  Get Package ID/Core ID/Thread ID of a processor.
> > -
> > -  APIC ID must be an initial APIC ID.
> > -
> > -  The algorithm below assumes the target system has symmetry across
> > physical package boundaries
> > -  with respect to the number of logical processors per package, number of
> cores per package.
> > -
> > -  @param  ApicId    APIC ID of the target logical processor.
> > -  @param  Location    Returns the processor location information.
> > -**/
> > -VOID
> > -SmmGetProcessorLocation (
> > -  IN UINT32 ApicId,
> > -  OUT EFI_CPU_PHYSICAL_LOCATION *Location
> > -  )
> > -{
> > -  UINTN   ThreadBits;
> > -  UINTN   CoreBits;
> > -  UINT32  RegEax;
> > -  UINT32  RegEbx;
> > -  UINT32  RegEcx;
> > -  UINT32  RegEdx;
> > -  UINT32  MaxCpuIdIndex;
> > -  UINT32  SubIndex;
> > -  UINTN   LevelType;
> > -  UINT32  MaxLogicProcessorsPerPackage;
> > -  UINT32  MaxCoresPerPackage;
> > -  BOOLEAN TopologyLeafSupported;
> > -
> > -  ASSERT (Location != NULL);
> > -
> > -  ThreadBits            = 0;
> > -  CoreBits              = 0;
> > -  TopologyLeafSupported = FALSE;
> > -
> > -  //
> > -  // Check if the processor is capable of supporting more than one logical
> processor.
> > -  //
> > -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
> > -  ASSERT ((RegEdx & BIT28) != 0);
> > -
> > -  //
> > -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > -  //
> > -
> > -  //
> > -  // Get the max index of basic CPUID
> > -  //
> > -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > -  //
> > -  // If the extended topology enumeration leaf is available, it
> > -  // is the preferred mechanism for enumerating topology.
> > -  //
> > -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > -    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx,
> &RegEcx, NULL);
> > -    //
> > -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input
> value for
> > -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is
> not
> > -    // supported on that processor.
> > -    //
> > -    if ((RegEbx & 0xffff) != 0) {
> > -      TopologyLeafSupported = TRUE;
> > -
> > -      //
> > -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters
> to extract
> > -      // the SMT sub-field of x2APIC ID.
> > -      //
> > -      LevelType = (RegEcx >> 8) & 0xff;
> > -      ASSERT (LevelType ==
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > -      if ((RegEbx & 0xffff) > 1 ) {
> > -        ThreadBits = RegEax & 0x1f;
> > -      } else {
> > -        //
> > -        // HT is not supported
> > -        //
> > -        ThreadBits = 0;
> > -      }
> > -
> > -      //
> > -      // Software must not assume any "level type" encoding
> > -      // value to be related to any sub-leaf index, except sub-leaf 0.
> > -      //
> > -      SubIndex = 1;
> > -      do {
> > -        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax,
> NULL, &RegEcx, NULL);
> > -        LevelType = (RegEcx >> 8) & 0xff;
> > -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > -          CoreBits = (RegEax & 0x1f) - ThreadBits;
> > -          break;
> > -        }
> > -        SubIndex++;
> > -      } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > -    }
> > -  }
> > -
> > -  if (!TopologyLeafSupported) {
> > -    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
> > -    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
> > -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
> > -      MaxCoresPerPackage = (RegEax >> 26) + 1;
> > -    } else {
> > -      //
> > -      // Must be a single-core processor.
> > -      //
> > -      MaxCoresPerPackage = 1;
> > -    }
> > -
> > -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > -  }
> > -
> > -  Location->Thread = ApicId & ~((-1) << ThreadBits);
> > -  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
> > -  Location->Package = (ApicId >> (ThreadBits+ CoreBits)); -}
> > -
> > -/**
> >    Gets processor information on the requested processor at the instant this
> call is made.
> >
> >    @param[in]  This                 A pointer to the
> EFI_SMM_CPU_SERVICE_PROTOCOL instance.
> > @@ -280,7 +161,12 @@ SmmAddProcessor (
> >          gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId ==
> INVALID_APIC_ID) {
> >        gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
> >        gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
> > -      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate-
> >ProcessorInfo[Index].Location);
> > +      GetProcessorLocation (
> > +        (UINT32)ProcessorId,
> > +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,
> > +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core,
> > +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread
> > +        );
> >
> >        *ProcessorNumber = Index;
> >        gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
> >



^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
  2016-10-31 21:23 ` Laszlo Ersek
  2016-10-31 21:26   ` Duran, Leo
@ 2016-10-31 21:29   ` Kinney, Michael D
  2016-11-01  0:48     ` Fan, Jeff
  1 sibling, 1 reply; 11+ messages in thread
From: Kinney, Michael D @ 2016-10-31 21:29 UTC (permalink / raw)
  To: Laszlo Ersek, Leo Duran, edk2-devel@ml01.01.org, Fan, Jeff,
	Kinney, Michael D
  Cc: Gao, Liming

Laszlo,

Thanks for the feedback and the additional testing.

Here is my Signed-off-by for this patch:

  Contributed-under: TianoCore Contribution Agreement 1.0
  Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com >

Jeff Fan can add my Signed-off-by and his rb and push the patch.

Mike

> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Laszlo Ersek
> Sent: Monday, October 31, 2016 2:24 PM
> To: Leo Duran <leo.duran@amd.com>; edk2-devel@ml01.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Fan, Jeff <jeff.fan@intel.com>;
> Gao, Liming <liming.gao@intel.com>
> Subject: Re: [edk2] [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib
> library
> 
> On 10/31/16 20:42, Leo Duran wrote:
> > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
> > 2) Remove ExtractProcessorLocation() from MpInitLib library.
> > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Leo Duran  <leo.duran@amd.com>
> > ---
> >  UefiCpuPkg/Include/Library/LocalApicLib.h          |  20 +++
> >  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 146 +++++++++++++++++++++
> >  .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 146 +++++++++++++++++++++
> >  UefiCpuPkg/Library/MpInitLib/MpLib.c               | 133 +------------------
> >  UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 126 +-----------------
> >  5 files changed, 324 insertions(+), 247 deletions(-)
> 
> (1) This patch should carry a "Signed-off-by" from Mike as well -- it is
> my understanding that this v4 patch is the result of joint work (it
> contains new code from two people).
> 
> I don't think it's necessary to repost the patch for this: if Mike
> responds with his S-o-b, then I believe Jeff can simply add that tag as
> well at commit time.
> 
> (2) I repeated my tests as described in
> <https://lists.01.org/pipermail/edk2-devel/2016-October/003807.html>;
> the v4 patch too works fine.
> 
> Tested-by: Laszlo Ersek <lersek@redhat.com>
> 
> Thanks
> Laszlo
> 
> > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h
> b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > index cd4e613..179409e 100644
> > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h
> > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > @@ -410,6 +410,26 @@ GetApicMsiValue (
> >    IN BOOLEAN  LevelTriggered,
> >    IN BOOLEAN  AssertionLevel
> >    );
> > +
> > +/**
> > +  Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +  The algorithm assumes the target system has symmetry across physical
> > +  package  boundaries with respect to the number of logical processors
> > +  per package,  number of cores per package.
> > +
> > +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> > +  @param[out]  Package       Returns the processor package ID.
> > +  @param[out]  Core          Returns the processor core ID.
> > +  @param[out]  Thread        Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN  UINT32  InitialApicId,
> > +  OUT UINT32  *Package  OPTIONAL,
> > +  OUT UINT32  *Core    OPTIONAL,
> > +  OUT UINT32  *Thread  OPTIONAL
> > +  );
> >
> >  #endif
> >
> > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > index 8d0fb02..f32d287 100644
> > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > @@ -941,3 +941,149 @@ GetApicMsiValue (
> >    }
> >    return MsiData.Uint64;
> >  }
> > +
> > +/**
> > +  Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +  The algorithm assumes the target system has symmetry across physical
> > +  package  boundaries with respect to the number of logical processors
> > +  per package,  number of cores per package.
> > +
> > +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> > +  @param[out]  Package       Returns the processor package ID.
> > +  @param[out]  Core          Returns the processor core ID.
> > +  @param[out]  Thread        Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN  UINT32  InitialApicId,
> > +  OUT UINT32  *Package  OPTIONAL,
> > +  OUT UINT32  *Core    OPTIONAL,
> > +  OUT UINT32  *Thread  OPTIONAL
> > +  )
> > +{
> > +  BOOLEAN                       TopologyLeafSupported;
> > +  UINTN                         ThreadBits;
> > +  UINTN                         CoreBits;
> > +  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
> > +  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
> > +  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
> > +  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
> > +  UINT32                        MaxCpuIdIndex;
> > +  UINT32                        SubIndex;
> > +  UINTN                         LevelType;
> > +  UINT32                        MaxLogicProcessorsPerPackage;
> > +  UINT32                        MaxCoresPerPackage;
> > +
> > +  //
> > +  // Check if the processor is capable of supporting more than one logical
> processor.
> > +  //
> > +  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> > +  if (VersionInfoEdx.Bits.HTT == 0) {
> > +    if (Thread != NULL) {
> > +      *Thread  = 0;
> > +    }
> > +    if (Core != NULL) {
> > +      *Core    = 0;
> > +    }
> > +    if (Package != NULL) {
> > +      *Package = 0;
> > +    }
> > +    return;
> > +  }
> > +
> > +  ThreadBits = 0;
> > +  CoreBits = 0;
> > +
> > +  //
> > +  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > +  //
> > +  TopologyLeafSupported = FALSE;
> > +
> > +  //
> > +  // Get the max index of basic CPUID
> > +  //
> > +  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > +
> > +  //
> > +  // If the extended topology enumeration leaf is available, it
> > +  // is the preferred mechanism for enumerating topology.
> > +  //
> > +  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > +    AsmCpuidEx(
> > +      CPUID_EXTENDED_TOPOLOGY,
> > +      0,
> > +      &ExtendedTopologyEax.Uint32,
> > +      &ExtendedTopologyEbx.Uint32,
> > +      &ExtendedTopologyEcx.Uint32,
> > +      NULL
> > +      );
> > +    //
> > +    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> > +    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> > +    // supported on that processor.
> > +    //
> > +    if (ExtendedTopologyEbx.Uint32 != 0) {
> > +      TopologyLeafSupported = TRUE;
> > +
> > +      //
> > +      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> > +      // the SMT sub-field of x2APIC ID.
> > +      //
> > +      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > +      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > +      //
> > +      // Software must not assume any "level type" encoding
> > +      // value to be related to any sub-leaf index, except sub-leaf 0.
> > +      //
> > +      SubIndex = 1;
> > +      do {
> > +        AsmCpuidEx(
> > +          CPUID_EXTENDED_TOPOLOGY,
> > +          SubIndex,
> > +          &ExtendedTopologyEax.Uint32,
> > +          NULL,
> > +          &ExtendedTopologyEcx.Uint32,
> > +          NULL
> > +          );
> > +        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > +          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > +          break;
> > +        }
> > +        SubIndex++;
> > +      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > +    }
> > +  }
> > +
> > +  if (!TopologyLeafSupported) {
> > +    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> > +    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > +      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> > +      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > +    }
> > +    else {
> > +      //
> > +      // Must be a single-core processor.
> > +      //
> > +      MaxCoresPerPackage = 1;
> > +    }
> > +
> > +    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > +    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
> > +
> > +  if (Thread != NULL) {
> > +    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > +  }
> > +  if (Core != NULL) {
> > +    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > +  }
> > +  if (Package != NULL) {
> > +    *Package = (InitialApicId >> (ThreadBits + CoreBits));
> > +  }
> > +}
> > diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > index 4c42696..a34a272 100644
> > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > @@ -1036,3 +1036,149 @@ GetApicMsiValue (
> >    }
> >    return MsiData.Uint64;
> >  }
> > +
> > +/**
> > +  Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +  The algorithm assumes the target system has symmetry across physical
> > +  package  boundaries with respect to the number of logical processors
> > +  per package,  number of cores per package.
> > +
> > +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> > +  @param[out]  Package       Returns the processor package ID.
> > +  @param[out]  Core          Returns the processor core ID.
> > +  @param[out]  Thread        Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN  UINT32  InitialApicId,
> > +  OUT UINT32  *Package  OPTIONAL,
> > +  OUT UINT32  *Core    OPTIONAL,
> > +  OUT UINT32  *Thread  OPTIONAL
> > +  )
> > +{
> > +  BOOLEAN                       TopologyLeafSupported;
> > +  UINTN                         ThreadBits;
> > +  UINTN                         CoreBits;
> > +  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
> > +  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
> > +  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
> > +  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
> > +  UINT32                        MaxCpuIdIndex;
> > +  UINT32                        SubIndex;
> > +  UINTN                         LevelType;
> > +  UINT32                        MaxLogicProcessorsPerPackage;
> > +  UINT32                        MaxCoresPerPackage;
> > +
> > +  //
> > +  // Check if the processor is capable of supporting more than one logical
> processor.
> > +  //
> > +  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> > +  if (VersionInfoEdx.Bits.HTT == 0) {
> > +    if (Thread != NULL) {
> > +      *Thread  = 0;
> > +    }
> > +    if (Core != NULL) {
> > +      *Core    = 0;
> > +    }
> > +    if (Package != NULL) {
> > +      *Package = 0;
> > +    }
> > +    return;
> > +  }
> > +
> > +  ThreadBits = 0;
> > +  CoreBits = 0;
> > +
> > +  //
> > +  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > +  //
> > +  TopologyLeafSupported = FALSE;
> > +
> > +  //
> > +  // Get the max index of basic CPUID
> > +  //
> > +  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > +
> > +  //
> > +  // If the extended topology enumeration leaf is available, it
> > +  // is the preferred mechanism for enumerating topology.
> > +  //
> > +  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > +    AsmCpuidEx(
> > +      CPUID_EXTENDED_TOPOLOGY,
> > +      0,
> > +      &ExtendedTopologyEax.Uint32,
> > +      &ExtendedTopologyEbx.Uint32,
> > +      &ExtendedTopologyEcx.Uint32,
> > +      NULL
> > +      );
> > +    //
> > +    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> > +    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> > +    // supported on that processor.
> > +    //
> > +    if (ExtendedTopologyEbx.Uint32 != 0) {
> > +      TopologyLeafSupported = TRUE;
> > +
> > +      //
> > +      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> > +      // the SMT sub-field of x2APIC ID.
> > +      //
> > +      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > +      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > +      //
> > +      // Software must not assume any "level type" encoding
> > +      // value to be related to any sub-leaf index, except sub-leaf 0.
> > +      //
> > +      SubIndex = 1;
> > +      do {
> > +        AsmCpuidEx(
> > +          CPUID_EXTENDED_TOPOLOGY,
> > +          SubIndex,
> > +          &ExtendedTopologyEax.Uint32,
> > +          NULL,
> > +          &ExtendedTopologyEcx.Uint32,
> > +          NULL
> > +          );
> > +        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > +          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > +          break;
> > +        }
> > +        SubIndex++;
> > +      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > +    }
> > +  }
> > +
> > +  if (!TopologyLeafSupported) {
> > +    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> > +    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > +      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> > +      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > +    }
> > +    else {
> > +      //
> > +      // Must be a single-core processor.
> > +      //
> > +      MaxCoresPerPackage = 1;
> > +    }
> > +
> > +    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > +    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
> > +
> > +  if (Thread != NULL) {
> > +    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > +  }
> > +  if (Core != NULL) {
> > +    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > +  }
> > +  if (Package != NULL) {
> > +    *Package = (InitialApicId >> (ThreadBits + CoreBits));
> > +  }
> > +}
> > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > index c3fe721..e48ff6a 100644
> > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (
> >  }
> >
> >  /**
> > -  Get CPU Package/Core/Thread location information.
> > -
> > -  @param[in]  InitialApicId     CPU APIC ID
> > -  @param[out] Location          Pointer to CPU location information
> > -**/
> > -VOID
> > -ExtractProcessorLocation (
> > -  IN  UINT32                     InitialApicId,
> > -  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> > -  )
> > -{
> > -  BOOLEAN                        TopologyLeafSupported;
> > -  UINTN                          ThreadBits;
> > -  UINTN                          CoreBits;
> > -  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> > -  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> > -  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> > -  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> > -  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> > -  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> > -  UINT32                         MaxCpuIdIndex;
> > -  UINT32                         SubIndex;
> > -  UINTN                          LevelType;
> > -  UINT32                         MaxLogicProcessorsPerPackage;
> > -  UINT32                         MaxCoresPerPackage;
> > -
> > -  //
> > -  // Check if the processor is capable of supporting more than one logical
> processor.
> > -  //
> > -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
> > -  if (VersionInfoEdx.Bits.HTT == 0) {
> > -    Location->Thread  = 0;
> > -    Location->Core    = 0;
> > -    Location->Package = 0;
> > -    return;
> > -  }
> > -
> > -  ThreadBits = 0;
> > -  CoreBits = 0;
> > -
> > -  //
> > -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > -  //
> > -
> > -  TopologyLeafSupported = FALSE;
> > -  //
> > -  // Get the max index of basic CPUID
> > -  //
> > -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > -  //
> > -  // If the extended topology enumeration leaf is available, it
> > -  // is the preferred mechanism for enumerating topology.
> > -  //
> > -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > -    AsmCpuidEx (
> > -      CPUID_EXTENDED_TOPOLOGY,
> > -      0,
> > -      &ExtendedTopologyEax.Uint32,
> > -      &ExtendedTopologyEbx.Uint32,
> > -      &ExtendedTopologyEcx.Uint32,
> > -      NULL
> > -      );
> > -    //
> > -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> > -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> > -    // supported on that processor.
> > -    //
> > -    if (ExtendedTopologyEbx.Uint32 != 0) {
> > -      TopologyLeafSupported = TRUE;
> > -
> > -      //
> > -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> > -      // the SMT sub-field of x2APIC ID.
> > -      //
> > -      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > -      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > -      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > -
> > -      //
> > -      // Software must not assume any "level type" encoding
> > -      // value to be related to any sub-leaf index, except sub-leaf 0.
> > -      //
> > -      SubIndex = 1;
> > -      do {
> > -        AsmCpuidEx (
> > -          CPUID_EXTENDED_TOPOLOGY,
> > -          SubIndex,
> > -          &ExtendedTopologyEax.Uint32,
> > -          NULL,
> > -          &ExtendedTopologyEcx.Uint32,
> > -          NULL
> > -          );
> > -        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > -          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > -          break;
> > -        }
> > -        SubIndex++;
> > -      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > -    }
> > -  }
> > -
> > -  if (!TopologyLeafSupported) {
> > -    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> > -    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> > -      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > -    } else {
> > -      //
> > -      // Must be a single-core processor.
> > -      //
> > -      MaxCoresPerPackage = 1;
> > -    }
> > -
> > -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > -  }
> > -
> > -  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > -  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > -  Location->Package = (InitialApicId >> (ThreadBits + CoreBits));
> > -}
> > -
> > -/**
> >    Worker function for SwitchBSP().
> >
> >    Worker function for SwitchBSP(), assigned to the AP which is intended
> > @@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo (
> >    //
> >    // Get processor location information
> >    //
> > -  ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId,
> &ProcessorInfoBuffer->Location);
> > +  GetProcessorLocation (
> > +    CpuMpData->CpuData[ProcessorNumber].ApicId,
> > +    &ProcessorInfoBuffer->Location.Package,
> > +    &ProcessorInfoBuffer->Location.Core,
> > +    &ProcessorInfoBuffer->Location.Thread
> > +    );
> >
> >    if (HealthData != NULL) {
> >      HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
> > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > index 40f2a17..f377a36 100644
> > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {
> >  };
> >
> >  /**
> > -  Get Package ID/Core ID/Thread ID of a processor.
> > -
> > -  APIC ID must be an initial APIC ID.
> > -
> > -  The algorithm below assumes the target system has symmetry across physical package
> boundaries
> > -  with respect to the number of logical processors per package, number of cores per
> package.
> > -
> > -  @param  ApicId    APIC ID of the target logical processor.
> > -  @param  Location    Returns the processor location information.
> > -**/
> > -VOID
> > -SmmGetProcessorLocation (
> > -  IN UINT32 ApicId,
> > -  OUT EFI_CPU_PHYSICAL_LOCATION *Location
> > -  )
> > -{
> > -  UINTN   ThreadBits;
> > -  UINTN   CoreBits;
> > -  UINT32  RegEax;
> > -  UINT32  RegEbx;
> > -  UINT32  RegEcx;
> > -  UINT32  RegEdx;
> > -  UINT32  MaxCpuIdIndex;
> > -  UINT32  SubIndex;
> > -  UINTN   LevelType;
> > -  UINT32  MaxLogicProcessorsPerPackage;
> > -  UINT32  MaxCoresPerPackage;
> > -  BOOLEAN TopologyLeafSupported;
> > -
> > -  ASSERT (Location != NULL);
> > -
> > -  ThreadBits            = 0;
> > -  CoreBits              = 0;
> > -  TopologyLeafSupported = FALSE;
> > -
> > -  //
> > -  // Check if the processor is capable of supporting more than one logical
> processor.
> > -  //
> > -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
> > -  ASSERT ((RegEdx & BIT28) != 0);
> > -
> > -  //
> > -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > -  //
> > -
> > -  //
> > -  // Get the max index of basic CPUID
> > -  //
> > -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > -  //
> > -  // If the extended topology enumeration leaf is available, it
> > -  // is the preferred mechanism for enumerating topology.
> > -  //
> > -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > -    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
> > -    //
> > -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> > -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> > -    // supported on that processor.
> > -    //
> > -    if ((RegEbx & 0xffff) != 0) {
> > -      TopologyLeafSupported = TRUE;
> > -
> > -      //
> > -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> > -      // the SMT sub-field of x2APIC ID.
> > -      //
> > -      LevelType = (RegEcx >> 8) & 0xff;
> > -      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > -      if ((RegEbx & 0xffff) > 1 ) {
> > -        ThreadBits = RegEax & 0x1f;
> > -      } else {
> > -        //
> > -        // HT is not supported
> > -        //
> > -        ThreadBits = 0;
> > -      }
> > -
> > -      //
> > -      // Software must not assume any "level type" encoding
> > -      // value to be related to any sub-leaf index, except sub-leaf 0.
> > -      //
> > -      SubIndex = 1;
> > -      do {
> > -        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx,
> NULL);
> > -        LevelType = (RegEcx >> 8) & 0xff;
> > -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > -          CoreBits = (RegEax & 0x1f) - ThreadBits;
> > -          break;
> > -        }
> > -        SubIndex++;
> > -      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > -    }
> > -  }
> > -
> > -  if (!TopologyLeafSupported) {
> > -    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
> > -    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
> > -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
> > -      MaxCoresPerPackage = (RegEax >> 26) + 1;
> > -    } else {
> > -      //
> > -      // Must be a single-core processor.
> > -      //
> > -      MaxCoresPerPackage = 1;
> > -    }
> > -
> > -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > -  }
> > -
> > -  Location->Thread = ApicId & ~((-1) << ThreadBits);
> > -  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
> > -  Location->Package = (ApicId >> (ThreadBits+ CoreBits));
> > -}
> > -
> > -/**
> >    Gets processor information on the requested processor at the instant this call is
> made.
> >
> >    @param[in]  This                 A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL
> instance.
> > @@ -280,7 +161,12 @@ SmmAddProcessor (
> >          gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
> >        gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
> >        gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
> > -      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate-
> >ProcessorInfo[Index].Location);
> > +      GetProcessorLocation (
> > +        (UINT32)ProcessorId,
> > +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,
> > +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core,
> > +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread
> > +        );
> >
> >        *ProcessorNumber = Index;
> >        gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
> >
> 
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
  2016-10-31 21:29   ` Kinney, Michael D
@ 2016-11-01  0:48     ` Fan, Jeff
  0 siblings, 0 replies; 11+ messages in thread
From: Fan, Jeff @ 2016-11-01  0:48 UTC (permalink / raw)
  To: Kinney, Michael D, Laszlo Ersek, Leo Duran,
	edk2-devel@ml01.01.org
  Cc: Gao, Liming

Reviewed-by: Jeff Fan <jeff.fan@intel.com>

I will commit this patch after appending Mike's Signed-off-by.

-----Original Message-----
From: Kinney, Michael D 
Sent: Tuesday, November 01, 2016 5:29 AM
To: Laszlo Ersek; Leo Duran; edk2-devel@ml01.01.org; Fan, Jeff; Kinney, Michael D
Cc: Gao, Liming
Subject: RE: [edk2] [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library

Laszlo,

Thanks for the feedback and the additional testing.

Here is my Signed-off-by for this patch:

  Contributed-under: TianoCore Contribution Agreement 1.0
  Signed-off-by: Michael Kinney <Michael.d.kinney@intel.com >

Jeff Fan can add my Signed-off-by and his rb and push the patch.

Mike

> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of 
> Laszlo Ersek
> Sent: Monday, October 31, 2016 2:24 PM
> To: Leo Duran <leo.duran@amd.com>; edk2-devel@ml01.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Fan, Jeff 
> <jeff.fan@intel.com>; Gao, Liming <liming.gao@intel.com>
> Subject: Re: [edk2] [PATCH] UefiCpuPkg: Move GetProcessorLocation() to 
> LocalApicLib library
> 
> On 10/31/16 20:42, Leo Duran wrote:
> > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
> > 2) Remove ExtractProcessorLocation() from MpInitLib library.
> > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Leo Duran  <leo.duran@amd.com>
> > ---
> >  UefiCpuPkg/Include/Library/LocalApicLib.h          |  20 +++
> >  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 146 +++++++++++++++++++++
> >  .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 146 +++++++++++++++++++++
> >  UefiCpuPkg/Library/MpInitLib/MpLib.c               | 133 +------------------
> >  UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 126 +-----------------
> >  5 files changed, 324 insertions(+), 247 deletions(-)
> 
> (1) This patch should carry a "Signed-off-by" from Mike as well -- it 
> is my understanding that this v4 patch is the result of joint work (it 
> contains new code from two people).
> 
> I don't think it's necessary to repost the patch for this: if Mike 
> responds with his S-o-b, then I believe Jeff can simply add that tag 
> as well at commit time.
> 
> (2) I repeated my tests as described in 
> <https://lists.01.org/pipermail/edk2-devel/2016-October/003807.html>;
> the v4 patch too works fine.
> 
> Tested-by: Laszlo Ersek <lersek@redhat.com>
> 
> Thanks
> Laszlo
> 
> > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h
> b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > index cd4e613..179409e 100644
> > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h
> > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
> > @@ -410,6 +410,26 @@ GetApicMsiValue (
> >    IN BOOLEAN  LevelTriggered,
> >    IN BOOLEAN  AssertionLevel
> >    );
> > +
> > +/**
> > +  Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +  The algorithm assumes the target system has symmetry across 
> > + physical  package  boundaries with respect to the number of 
> > + logical processors  per package,  number of cores per package.
> > +
> > +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> > +  @param[out]  Package       Returns the processor package ID.
> > +  @param[out]  Core          Returns the processor core ID.
> > +  @param[out]  Thread        Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN  UINT32  InitialApicId,
> > +  OUT UINT32  *Package  OPTIONAL,
> > +  OUT UINT32  *Core    OPTIONAL,
> > +  OUT UINT32  *Thread  OPTIONAL
> > +  );
> >
> >  #endif
> >
> > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > index 8d0fb02..f32d287 100644
> > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > @@ -941,3 +941,149 @@ GetApicMsiValue (
> >    }
> >    return MsiData.Uint64;
> >  }
> > +
> > +/**
> > +  Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +  The algorithm assumes the target system has symmetry across 
> > + physical  package  boundaries with respect to the number of 
> > + logical processors  per package,  number of cores per package.
> > +
> > +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> > +  @param[out]  Package       Returns the processor package ID.
> > +  @param[out]  Core          Returns the processor core ID.
> > +  @param[out]  Thread        Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN  UINT32  InitialApicId,
> > +  OUT UINT32  *Package  OPTIONAL,
> > +  OUT UINT32  *Core    OPTIONAL,
> > +  OUT UINT32  *Thread  OPTIONAL
> > +  )
> > +{
> > +  BOOLEAN                       TopologyLeafSupported;
> > +  UINTN                         ThreadBits;
> > +  UINTN                         CoreBits;
> > +  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
> > +  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
> > +  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
> > +  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
> > +  UINT32                        MaxCpuIdIndex;
> > +  UINT32                        SubIndex;
> > +  UINTN                         LevelType;
> > +  UINT32                        MaxLogicProcessorsPerPackage;
> > +  UINT32                        MaxCoresPerPackage;
> > +
> > +  //
> > +  // Check if the processor is capable of supporting more than one 
> > + logical
> processor.
> > +  //
> > +  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, 
> > + &VersionInfoEdx.Uint32);  if (VersionInfoEdx.Bits.HTT == 0) {
> > +    if (Thread != NULL) {
> > +      *Thread  = 0;
> > +    }
> > +    if (Core != NULL) {
> > +      *Core    = 0;
> > +    }
> > +    if (Package != NULL) {
> > +      *Package = 0;
> > +    }
> > +    return;
> > +  }
> > +
> > +  ThreadBits = 0;
> > +  CoreBits = 0;
> > +
> > +  //
> > +  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > +  //
> > +  TopologyLeafSupported = FALSE;
> > +
> > +  //
> > +  // Get the max index of basic CPUID  //  
> > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > +
> > +  //
> > +  // If the extended topology enumeration leaf is available, it  // 
> > + is the preferred mechanism for enumerating topology.
> > +  //
> > +  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > +    AsmCpuidEx(
> > +      CPUID_EXTENDED_TOPOLOGY,
> > +      0,
> > +      &ExtendedTopologyEax.Uint32,
> > +      &ExtendedTopologyEbx.Uint32,
> > +      &ExtendedTopologyEcx.Uint32,
> > +      NULL
> > +      );
> > +    //
> > +    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> > +    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> > +    // supported on that processor.
> > +    //
> > +    if (ExtendedTopologyEbx.Uint32 != 0) {
> > +      TopologyLeafSupported = TRUE;
> > +
> > +      //
> > +      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration 
> > + parameters to
> extract
> > +      // the SMT sub-field of x2APIC ID.
> > +      //
> > +      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > +      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > +      //
> > +      // Software must not assume any "level type" encoding
> > +      // value to be related to any sub-leaf index, except sub-leaf 0.
> > +      //
> > +      SubIndex = 1;
> > +      do {
> > +        AsmCpuidEx(
> > +          CPUID_EXTENDED_TOPOLOGY,
> > +          SubIndex,
> > +          &ExtendedTopologyEax.Uint32,
> > +          NULL,
> > +          &ExtendedTopologyEcx.Uint32,
> > +          NULL
> > +          );
> > +        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > +          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > +          break;
> > +        }
> > +        SubIndex++;
> > +      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > +    }
> > +  }
> > +
> > +  if (!TopologyLeafSupported) {
> > +    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> > +    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > +      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> > +      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > +    }
> > +    else {
> > +      //
> > +      // Must be a single-core processor.
> > +      //
> > +      MaxCoresPerPackage = 1;
> > +    }
> > +
> > +    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage 
> > + /
> MaxCoresPerPackage - 1) + 1);
> > +    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  
> > + }
> > +
> > +  if (Thread != NULL) {
> > +    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > +  }
> > +  if (Core != NULL) {
> > +    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > +  }
> > +  if (Package != NULL) {
> > +    *Package = (InitialApicId >> (ThreadBits + CoreBits));
> > +  }
> > +}
> > diff --git 
> > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > index 4c42696..a34a272 100644
> > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > @@ -1036,3 +1036,149 @@ GetApicMsiValue (
> >    }
> >    return MsiData.Uint64;
> >  }
> > +
> > +/**
> > +  Get Package ID/Core ID/Thread ID of a processor.
> > +
> > +  The algorithm assumes the target system has symmetry across 
> > + physical  package  boundaries with respect to the number of 
> > + logical processors  per package,  number of cores per package.
> > +
> > +  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
> > +  @param[out]  Package       Returns the processor package ID.
> > +  @param[out]  Core          Returns the processor core ID.
> > +  @param[out]  Thread        Returns the processor thread ID.
> > +**/
> > +VOID
> > +GetProcessorLocation(
> > +  IN  UINT32  InitialApicId,
> > +  OUT UINT32  *Package  OPTIONAL,
> > +  OUT UINT32  *Core    OPTIONAL,
> > +  OUT UINT32  *Thread  OPTIONAL
> > +  )
> > +{
> > +  BOOLEAN                       TopologyLeafSupported;
> > +  UINTN                         ThreadBits;
> > +  UINTN                         CoreBits;
> > +  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
> > +  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
> > +  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
> > +  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
> > +  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
> > +  UINT32                        MaxCpuIdIndex;
> > +  UINT32                        SubIndex;
> > +  UINTN                         LevelType;
> > +  UINT32                        MaxLogicProcessorsPerPackage;
> > +  UINT32                        MaxCoresPerPackage;
> > +
> > +  //
> > +  // Check if the processor is capable of supporting more than one 
> > + logical
> processor.
> > +  //
> > +  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, 
> > + &VersionInfoEdx.Uint32);  if (VersionInfoEdx.Bits.HTT == 0) {
> > +    if (Thread != NULL) {
> > +      *Thread  = 0;
> > +    }
> > +    if (Core != NULL) {
> > +      *Core    = 0;
> > +    }
> > +    if (Package != NULL) {
> > +      *Package = 0;
> > +    }
> > +    return;
> > +  }
> > +
> > +  ThreadBits = 0;
> > +  CoreBits = 0;
> > +
> > +  //
> > +  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > +  //
> > +  TopologyLeafSupported = FALSE;
> > +
> > +  //
> > +  // Get the max index of basic CPUID  //  
> > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > +
> > +  //
> > +  // If the extended topology enumeration leaf is available, it  // 
> > + is the preferred mechanism for enumerating topology.
> > +  //
> > +  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > +    AsmCpuidEx(
> > +      CPUID_EXTENDED_TOPOLOGY,
> > +      0,
> > +      &ExtendedTopologyEax.Uint32,
> > +      &ExtendedTopologyEbx.Uint32,
> > +      &ExtendedTopologyEcx.Uint32,
> > +      NULL
> > +      );
> > +    //
> > +    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> > +    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> > +    // supported on that processor.
> > +    //
> > +    if (ExtendedTopologyEbx.Uint32 != 0) {
> > +      TopologyLeafSupported = TRUE;
> > +
> > +      //
> > +      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration 
> > + parameters to
> extract
> > +      // the SMT sub-field of x2APIC ID.
> > +      //
> > +      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > +      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > +
> > +      //
> > +      // Software must not assume any "level type" encoding
> > +      // value to be related to any sub-leaf index, except sub-leaf 0.
> > +      //
> > +      SubIndex = 1;
> > +      do {
> > +        AsmCpuidEx(
> > +          CPUID_EXTENDED_TOPOLOGY,
> > +          SubIndex,
> > +          &ExtendedTopologyEax.Uint32,
> > +          NULL,
> > +          &ExtendedTopologyEcx.Uint32,
> > +          NULL
> > +          );
> > +        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > +        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > +          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > +          break;
> > +        }
> > +        SubIndex++;
> > +      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > +    }
> > +  }
> > +
> > +  if (!TopologyLeafSupported) {
> > +    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> > +    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > +      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> > +      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > +    }
> > +    else {
> > +      //
> > +      // Must be a single-core processor.
> > +      //
> > +      MaxCoresPerPackage = 1;
> > +    }
> > +
> > +    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage 
> > + /
> MaxCoresPerPackage - 1) + 1);
> > +    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  
> > + }
> > +
> > +  if (Thread != NULL) {
> > +    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > +  }
> > +  if (Core != NULL) {
> > +    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > +  }
> > +  if (Package != NULL) {
> > +    *Package = (InitialApicId >> (ThreadBits + CoreBits));
> > +  }
> > +}
> > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > index c3fe721..e48ff6a 100644
> > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
> > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (  }
> >
> >  /**
> > -  Get CPU Package/Core/Thread location information.
> > -
> > -  @param[in]  InitialApicId     CPU APIC ID
> > -  @param[out] Location          Pointer to CPU location information
> > -**/
> > -VOID
> > -ExtractProcessorLocation (
> > -  IN  UINT32                     InitialApicId,
> > -  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
> > -  )
> > -{
> > -  BOOLEAN                        TopologyLeafSupported;
> > -  UINTN                          ThreadBits;
> > -  UINTN                          CoreBits;
> > -  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
> > -  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
> > -  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
> > -  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
> > -  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
> > -  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
> > -  UINT32                         MaxCpuIdIndex;
> > -  UINT32                         SubIndex;
> > -  UINTN                          LevelType;
> > -  UINT32                         MaxLogicProcessorsPerPackage;
> > -  UINT32                         MaxCoresPerPackage;
> > -
> > -  //
> > -  // Check if the processor is capable of supporting more than one 
> > logical
> processor.
> > -  //
> > -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, 
> > &VersionInfoEdx.Uint32);
> > -  if (VersionInfoEdx.Bits.HTT == 0) {
> > -    Location->Thread  = 0;
> > -    Location->Core    = 0;
> > -    Location->Package = 0;
> > -    return;
> > -  }
> > -
> > -  ThreadBits = 0;
> > -  CoreBits = 0;
> > -
> > -  //
> > -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > -  //
> > -
> > -  TopologyLeafSupported = FALSE;
> > -  //
> > -  // Get the max index of basic CPUID
> > -  //
> > -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > -  //
> > -  // If the extended topology enumeration leaf is available, it
> > -  // is the preferred mechanism for enumerating topology.
> > -  //
> > -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > -    AsmCpuidEx (
> > -      CPUID_EXTENDED_TOPOLOGY,
> > -      0,
> > -      &ExtendedTopologyEax.Uint32,
> > -      &ExtendedTopologyEbx.Uint32,
> > -      &ExtendedTopologyEcx.Uint32,
> > -      NULL
> > -      );
> > -    //
> > -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> > -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> > -    // supported on that processor.
> > -    //
> > -    if (ExtendedTopologyEbx.Uint32 != 0) {
> > -      TopologyLeafSupported = TRUE;
> > -
> > -      //
> > -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> > -      // the SMT sub-field of x2APIC ID.
> > -      //
> > -      LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > -      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > -      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
> > -
> > -      //
> > -      // Software must not assume any "level type" encoding
> > -      // value to be related to any sub-leaf index, except sub-leaf 0.
> > -      //
> > -      SubIndex = 1;
> > -      do {
> > -        AsmCpuidEx (
> > -          CPUID_EXTENDED_TOPOLOGY,
> > -          SubIndex,
> > -          &ExtendedTopologyEax.Uint32,
> > -          NULL,
> > -          &ExtendedTopologyEcx.Uint32,
> > -          NULL
> > -          );
> > -        LevelType = ExtendedTopologyEcx.Bits.LevelType;
> > -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > -          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
> > -          break;
> > -        }
> > -        SubIndex++;
> > -      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > -    }
> > -  }
> > -
> > -  if (!TopologyLeafSupported) {
> > -    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
> > -    MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
> > -      MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > -    } else {
> > -      //
> > -      // Must be a single-core processor.
> > -      //
> > -      MaxCoresPerPackage = 1;
> > -    }
> > -
> > -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > -  }
> > -
> > -  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
> > -  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > -  Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); 
> > -}
> > -
> > -/**
> >    Worker function for SwitchBSP().
> >
> >    Worker function for SwitchBSP(), assigned to the AP which is 
> > intended @@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo (
> >    //
> >    // Get processor location information
> >    //
> > -  ExtractProcessorLocation 
> > (CpuMpData->CpuData[ProcessorNumber].ApicId,
> &ProcessorInfoBuffer->Location);
> > +  GetProcessorLocation (
> > +    CpuMpData->CpuData[ProcessorNumber].ApicId,
> > +    &ProcessorInfoBuffer->Location.Package,
> > +    &ProcessorInfoBuffer->Location.Core,
> > +    &ProcessorInfoBuffer->Location.Thread
> > +    );
> >
> >    if (HealthData != NULL) {
> >      HealthData->Uint32 = 
> > CpuMpData->CpuData[ProcessorNumber].Health;
> > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > index 40f2a17..f377a36 100644
> > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
> > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {  
> > };
> >
> >  /**
> > -  Get Package ID/Core ID/Thread ID of a processor.
> > -
> > -  APIC ID must be an initial APIC ID.
> > -
> > -  The algorithm below assumes the target system has symmetry across 
> > physical package
> boundaries
> > -  with respect to the number of logical processors per package, 
> > number of cores per
> package.
> > -
> > -  @param  ApicId    APIC ID of the target logical processor.
> > -  @param  Location    Returns the processor location information.
> > -**/
> > -VOID
> > -SmmGetProcessorLocation (
> > -  IN UINT32 ApicId,
> > -  OUT EFI_CPU_PHYSICAL_LOCATION *Location
> > -  )
> > -{
> > -  UINTN   ThreadBits;
> > -  UINTN   CoreBits;
> > -  UINT32  RegEax;
> > -  UINT32  RegEbx;
> > -  UINT32  RegEcx;
> > -  UINT32  RegEdx;
> > -  UINT32  MaxCpuIdIndex;
> > -  UINT32  SubIndex;
> > -  UINTN   LevelType;
> > -  UINT32  MaxLogicProcessorsPerPackage;
> > -  UINT32  MaxCoresPerPackage;
> > -  BOOLEAN TopologyLeafSupported;
> > -
> > -  ASSERT (Location != NULL);
> > -
> > -  ThreadBits            = 0;
> > -  CoreBits              = 0;
> > -  TopologyLeafSupported = FALSE;
> > -
> > -  //
> > -  // Check if the processor is capable of supporting more than one 
> > logical
> processor.
> > -  //
> > -  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
> > -  ASSERT ((RegEdx & BIT28) != 0);
> > -
> > -  //
> > -  // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > -  //
> > -
> > -  //
> > -  // Get the max index of basic CPUID
> > -  //
> > -  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > -
> > -  //
> > -  // If the extended topology enumeration leaf is available, it
> > -  // is the preferred mechanism for enumerating topology.
> > -  //
> > -  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > -    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
> > -    //
> > -    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
> > -    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
> > -    // supported on that processor.
> > -    //
> > -    if ((RegEbx & 0xffff) != 0) {
> > -      TopologyLeafSupported = TRUE;
> > -
> > -      //
> > -      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> > -      // the SMT sub-field of x2APIC ID.
> > -      //
> > -      LevelType = (RegEcx >> 8) & 0xff;
> > -      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
> > -      if ((RegEbx & 0xffff) > 1 ) {
> > -        ThreadBits = RegEax & 0x1f;
> > -      } else {
> > -        //
> > -        // HT is not supported
> > -        //
> > -        ThreadBits = 0;
> > -      }
> > -
> > -      //
> > -      // Software must not assume any "level type" encoding
> > -      // value to be related to any sub-leaf index, except sub-leaf 0.
> > -      //
> > -      SubIndex = 1;
> > -      do {
> > -        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx,
> NULL);
> > -        LevelType = (RegEcx >> 8) & 0xff;
> > -        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
> > -          CoreBits = (RegEax & 0x1f) - ThreadBits;
> > -          break;
> > -        }
> > -        SubIndex++;
> > -      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > -    }
> > -  }
> > -
> > -  if (!TopologyLeafSupported) {
> > -    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
> > -    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
> > -    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > -      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
> > -      MaxCoresPerPackage = (RegEax >> 26) + 1;
> > -    } else {
> > -      //
> > -      // Must be a single-core processor.
> > -      //
> > -      MaxCoresPerPackage = 1;
> > -    }
> > -
> > -    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> > -    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
> > -  }
> > -
> > -  Location->Thread = ApicId & ~((-1) << ThreadBits);
> > -  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
> > -  Location->Package = (ApicId >> (ThreadBits+ CoreBits)); -}
> > -
> > -/**
> >    Gets processor information on the requested processor at the 
> > instant this call is
> made.
> >
> >    @param[in]  This                 A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL
> instance.
> > @@ -280,7 +161,12 @@ SmmAddProcessor (
> >          gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
> >        gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
> >        gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
> > -      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate-
> >ProcessorInfo[Index].Location);
> > +      GetProcessorLocation (
> > +        (UINT32)ProcessorId,
> > +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,
> > +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core,
> > +        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread
> > +        );
> >
> >        *ProcessorNumber = Index;
> >        gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
> >
> 
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel


^ permalink raw reply	[flat|nested] 11+ messages in thread

* Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library
  2016-10-31 19:42 [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Leo Duran
  2016-10-31 21:23 ` Laszlo Ersek
@ 2016-11-01  2:25 ` Fan, Jeff
  1 sibling, 0 replies; 11+ messages in thread
From: Fan, Jeff @ 2016-11-01  2:25 UTC (permalink / raw)
  To: Leo Duran, edk2-devel@lists.01.org
  Cc: Gao, Liming, lersek@redhat.com, Kinney, Michael D

Leo,

I just recognized GetProcessorLocation() is too generic name and used by other library or modules to return Processor location from MP services.
For example, the old Galileo-board-software-package used the same API to return Processor Location.

To avoid changing other library/modules, I suggest to use one specific name in Local APIC Library, for example GetProcessorLocationByApicId ().
I will create the patch to do this renaming.

Thanks!
Jeff

-----Original Message-----
From: Leo Duran [mailto:leo.duran@amd.com] 
Sent: Tuesday, November 01, 2016 3:43 AM
To: edk2-devel@lists.01.org
Cc: Gao, Liming; lersek@redhat.com; Fan, Jeff; Kinney, Michael D; Leo Duran
Subject: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library

1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver.
2) Remove ExtractProcessorLocation() from MpInitLib library.
3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran  <leo.duran@amd.com>
---
 UefiCpuPkg/Include/Library/LocalApicLib.h          |  20 +++
 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 146 +++++++++++++++++++++
 .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 146 +++++++++++++++++++++
 UefiCpuPkg/Library/MpInitLib/MpLib.c               | 133 +------------------
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c             | 126 +-----------------
 5 files changed, 324 insertions(+), 247 deletions(-)

diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
index cd4e613..179409e 100644
--- a/UefiCpuPkg/Include/Library/LocalApicLib.h
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -410,6 +410,26 @@ GetApicMsiValue (
   IN BOOLEAN  LevelTriggered,
   IN BOOLEAN  AssertionLevel
   );
+
+/**
+  Get Package ID/Core ID/Thread ID of a processor.
+
+  The algorithm assumes the target system has symmetry across physical  
+ package  boundaries with respect to the number of logical processors  
+ per package,  number of cores per package.
+
+  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
+  @param[out]  Package       Returns the processor package ID.
+  @param[out]  Core          Returns the processor core ID.
+  @param[out]  Thread        Returns the processor thread ID.
+**/
+VOID
+GetProcessorLocation(
+  IN  UINT32  InitialApicId,
+  OUT UINT32  *Package  OPTIONAL,
+  OUT UINT32  *Core    OPTIONAL,
+  OUT UINT32  *Thread  OPTIONAL
+  );
   
 #endif
 
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 8d0fb02..f32d287 100644
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -941,3 +941,149 @@ GetApicMsiValue (
   }
   return MsiData.Uint64;
 }
+
+/**
+  Get Package ID/Core ID/Thread ID of a processor.
+
+  The algorithm assumes the target system has symmetry across physical  
+ package  boundaries with respect to the number of logical processors  
+ per package,  number of cores per package.
+
+  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
+  @param[out]  Package       Returns the processor package ID.
+  @param[out]  Core          Returns the processor core ID.
+  @param[out]  Thread        Returns the processor thread ID.
+**/
+VOID
+GetProcessorLocation(
+  IN  UINT32  InitialApicId,
+  OUT UINT32  *Package  OPTIONAL,
+  OUT UINT32  *Core    OPTIONAL,
+  OUT UINT32  *Thread  OPTIONAL
+  )
+{
+  BOOLEAN                       TopologyLeafSupported;
+  UINTN                         ThreadBits;
+  UINTN                         CoreBits;
+  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
+  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
+  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
+  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
+  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
+  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
+  UINT32                        MaxCpuIdIndex;
+  UINT32                        SubIndex;
+  UINTN                         LevelType;
+  UINT32                        MaxLogicProcessorsPerPackage;
+  UINT32                        MaxCoresPerPackage;
+
+  //
+  // Check if the processor is capable of supporting more than one logical processor.
+  //
+  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, 
+ &VersionInfoEdx.Uint32);  if (VersionInfoEdx.Bits.HTT == 0) {
+    if (Thread != NULL) {
+      *Thread  = 0;
+    }
+    if (Core != NULL) {
+      *Core    = 0;
+    }
+    if (Package != NULL) {
+      *Package = 0;
+    }
+    return;
+  }
+
+  ThreadBits = 0;
+  CoreBits = 0;
+
+  //
+  // Assume three-level mapping of APIC ID: Package:Core:SMT.
+  //
+  TopologyLeafSupported = FALSE;
+
+  //
+  // Get the max index of basic CPUID
+  //
+  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+  //
+  // If the extended topology enumeration leaf is available, it  // is 
+ the preferred mechanism for enumerating topology.
+  //
+  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+    AsmCpuidEx(
+      CPUID_EXTENDED_TOPOLOGY,
+      0,
+      &ExtendedTopologyEax.Uint32,
+      &ExtendedTopologyEbx.Uint32,
+      &ExtendedTopologyEcx.Uint32,
+      NULL
+      );
+    //
+    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
+    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
+    // supported on that processor.
+    //
+    if (ExtendedTopologyEbx.Uint32 != 0) {
+      TopologyLeafSupported = TRUE;
+
+      //
+      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
+      // the SMT sub-field of x2APIC ID.
+      //
+      LevelType = ExtendedTopologyEcx.Bits.LevelType;
+      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
+      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
+
+      //
+      // Software must not assume any "level type" encoding
+      // value to be related to any sub-leaf index, except sub-leaf 0.
+      //
+      SubIndex = 1;
+      do {
+        AsmCpuidEx(
+          CPUID_EXTENDED_TOPOLOGY,
+          SubIndex,
+          &ExtendedTopologyEax.Uint32,
+          NULL,
+          &ExtendedTopologyEcx.Uint32,
+          NULL
+          );
+        LevelType = ExtendedTopologyEcx.Bits.LevelType;
+        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
+          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
+          break;
+        }
+        SubIndex++;
+      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+    }
+  }
+
+  if (!TopologyLeafSupported) {
+    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
+      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+    }
+    else {
+      //
+      // Must be a single-core processor.
+      //
+      MaxCoresPerPackage = 1;
+    }
+
+    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
+
+  if (Thread != NULL) {
+    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
+  }
+  if (Core != NULL) {
+    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+  }
+  if (Package != NULL) {
+    *Package = (InitialApicId >> (ThreadBits + CoreBits));
+  }
+}
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 4c42696..a34a272 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -1036,3 +1036,149 @@ GetApicMsiValue (
   }
   return MsiData.Uint64;
 }
+
+/**
+  Get Package ID/Core ID/Thread ID of a processor.
+
+  The algorithm assumes the target system has symmetry across physical  
+ package  boundaries with respect to the number of logical processors  
+ per package,  number of cores per package.
+
+  @param[in]  InitialApicId  Initial APIC ID of the target logical processor.
+  @param[out]  Package       Returns the processor package ID.
+  @param[out]  Core          Returns the processor core ID.
+  @param[out]  Thread        Returns the processor thread ID.
+**/
+VOID
+GetProcessorLocation(
+  IN  UINT32  InitialApicId,
+  OUT UINT32  *Package  OPTIONAL,
+  OUT UINT32  *Core    OPTIONAL,
+  OUT UINT32  *Thread  OPTIONAL
+  )
+{
+  BOOLEAN                       TopologyLeafSupported;
+  UINTN                         ThreadBits;
+  UINTN                         CoreBits;
+  CPUID_VERSION_INFO_EBX        VersionInfoEbx;
+  CPUID_VERSION_INFO_EDX        VersionInfoEdx;
+  CPUID_CACHE_PARAMS_EAX        CacheParamsEax;
+  CPUID_EXTENDED_TOPOLOGY_EAX   ExtendedTopologyEax;
+  CPUID_EXTENDED_TOPOLOGY_EBX   ExtendedTopologyEbx;
+  CPUID_EXTENDED_TOPOLOGY_ECX   ExtendedTopologyEcx;
+  UINT32                        MaxCpuIdIndex;
+  UINT32                        SubIndex;
+  UINTN                         LevelType;
+  UINT32                        MaxLogicProcessorsPerPackage;
+  UINT32                        MaxCoresPerPackage;
+
+  //
+  // Check if the processor is capable of supporting more than one logical processor.
+  //
+  AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, 
+ &VersionInfoEdx.Uint32);  if (VersionInfoEdx.Bits.HTT == 0) {
+    if (Thread != NULL) {
+      *Thread  = 0;
+    }
+    if (Core != NULL) {
+      *Core    = 0;
+    }
+    if (Package != NULL) {
+      *Package = 0;
+    }
+    return;
+  }
+
+  ThreadBits = 0;
+  CoreBits = 0;
+
+  //
+  // Assume three-level mapping of APIC ID: Package:Core:SMT.
+  //
+  TopologyLeafSupported = FALSE;
+
+  //
+  // Get the max index of basic CPUID
+  //
+  AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+
+  //
+  // If the extended topology enumeration leaf is available, it  // is 
+ the preferred mechanism for enumerating topology.
+  //
+  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+    AsmCpuidEx(
+      CPUID_EXTENDED_TOPOLOGY,
+      0,
+      &ExtendedTopologyEax.Uint32,
+      &ExtendedTopologyEbx.Uint32,
+      &ExtendedTopologyEcx.Uint32,
+      NULL
+      );
+    //
+    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
+    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
+    // supported on that processor.
+    //
+    if (ExtendedTopologyEbx.Uint32 != 0) {
+      TopologyLeafSupported = TRUE;
+
+      //
+      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
+      // the SMT sub-field of x2APIC ID.
+      //
+      LevelType = ExtendedTopologyEcx.Bits.LevelType;
+      ASSERT(LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
+      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
+
+      //
+      // Software must not assume any "level type" encoding
+      // value to be related to any sub-leaf index, except sub-leaf 0.
+      //
+      SubIndex = 1;
+      do {
+        AsmCpuidEx(
+          CPUID_EXTENDED_TOPOLOGY,
+          SubIndex,
+          &ExtendedTopologyEax.Uint32,
+          NULL,
+          &ExtendedTopologyEcx.Uint32,
+          NULL
+          );
+        LevelType = ExtendedTopologyEcx.Bits.LevelType;
+        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
+          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
+          break;
+        }
+        SubIndex++;
+      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+    }
+  }
+
+  if (!TopologyLeafSupported) {
+    AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
+      AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+    }
+    else {
+      //
+      // Must be a single-core processor.
+      //
+      MaxCoresPerPackage = 1;
+    }
+
+    ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+    CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);  }
+
+  if (Thread != NULL) {
+    *Thread  = InitialApicId & ((1 << ThreadBits) - 1);
+  }
+  if (Core != NULL) {
+    *Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+  }
+  if (Package != NULL) {
+    *Package = (InitialApicId >> (ThreadBits + CoreBits));
+  }
+}
diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c
index c3fe721..e48ff6a 100644
--- a/UefiCpuPkg/Library/MpInitLib/MpLib.c
+++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c
@@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled (  }
 
 /**
-  Get CPU Package/Core/Thread location information.
-
-  @param[in]  InitialApicId     CPU APIC ID
-  @param[out] Location          Pointer to CPU location information
-**/
-VOID
-ExtractProcessorLocation (
-  IN  UINT32                     InitialApicId,
-  OUT EFI_CPU_PHYSICAL_LOCATION  *Location
-  )
-{
-  BOOLEAN                        TopologyLeafSupported;
-  UINTN                          ThreadBits;
-  UINTN                          CoreBits;
-  CPUID_VERSION_INFO_EBX         VersionInfoEbx;
-  CPUID_VERSION_INFO_EDX         VersionInfoEdx;
-  CPUID_CACHE_PARAMS_EAX         CacheParamsEax;
-  CPUID_EXTENDED_TOPOLOGY_EAX    ExtendedTopologyEax;
-  CPUID_EXTENDED_TOPOLOGY_EBX    ExtendedTopologyEbx;
-  CPUID_EXTENDED_TOPOLOGY_ECX    ExtendedTopologyEcx;
-  UINT32                         MaxCpuIdIndex;
-  UINT32                         SubIndex;
-  UINTN                          LevelType;
-  UINT32                         MaxLogicProcessorsPerPackage;
-  UINT32                         MaxCoresPerPackage;
-
-  //
-  // Check if the processor is capable of supporting more than one logical processor.
-  //
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
-  if (VersionInfoEdx.Bits.HTT == 0) {
-    Location->Thread  = 0;
-    Location->Core    = 0;
-    Location->Package = 0;
-    return;
-  }
-
-  ThreadBits = 0;
-  CoreBits = 0;
-
-  //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
-  //
-
-  TopologyLeafSupported = FALSE;
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
-
-  //
-  // If the extended topology enumeration leaf is available, it
-  // is the preferred mechanism for enumerating topology.
-  //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
-    AsmCpuidEx (
-      CPUID_EXTENDED_TOPOLOGY,
-      0,
-      &ExtendedTopologyEax.Uint32,
-      &ExtendedTopologyEbx.Uint32,
-      &ExtendedTopologyEcx.Uint32,
-      NULL
-      );
-    //
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
-    // supported on that processor.
-    //
-    if (ExtendedTopologyEbx.Uint32 != 0) {
-      TopologyLeafSupported = TRUE;
-
-      //
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
-      // the SMT sub-field of x2APIC ID.
-      //
-      LevelType = ExtendedTopologyEcx.Bits.LevelType;
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
-      ThreadBits = ExtendedTopologyEax.Bits.ApicIdShift;
-
-      //
-      // Software must not assume any "level type" encoding
-      // value to be related to any sub-leaf index, except sub-leaf 0.
-      //
-      SubIndex = 1;
-      do {
-        AsmCpuidEx (
-          CPUID_EXTENDED_TOPOLOGY,
-          SubIndex,
-          &ExtendedTopologyEax.Uint32,
-          NULL,
-          &ExtendedTopologyEcx.Uint32,
-          NULL
-          );
-        LevelType = ExtendedTopologyEcx.Bits.LevelType;
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
-          CoreBits = ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits;
-          break;
-        }
-        SubIndex++;
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
-    }
-  }
-
-  if (!TopologyLeafSupported) {
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
-    MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
-      MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
-    } else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
-    }
-
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
-  }
-
-  Location->Thread  = InitialApicId & ((1 << ThreadBits) - 1);
-  Location->Core    = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
-  Location->Package = (InitialApicId >> (ThreadBits + CoreBits)); -}
-
-/**
   Worker function for SwitchBSP().
 
   Worker function for SwitchBSP(), assigned to the AP which is intended @@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo (
   //
   // Get processor location information
   //
-  ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location);
+  GetProcessorLocation (
+    CpuMpData->CpuData[ProcessorNumber].ApicId,
+    &ProcessorInfoBuffer->Location.Package,
+    &ProcessorInfoBuffer->Location.Core,
+    &ProcessorInfoBuffer->Location.Thread
+    );
 
   if (HealthData != NULL) {
     HealthData->Uint32 = CpuMpData->CpuData[ProcessorNumber].Health;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
index 40f2a17..f377a36 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c
@@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL  mSmmCpuService = {  };
 
 /**
-  Get Package ID/Core ID/Thread ID of a processor.
-
-  APIC ID must be an initial APIC ID.
-
-  The algorithm below assumes the target system has symmetry across physical package boundaries
-  with respect to the number of logical processors per package, number of cores per package.
-
-  @param  ApicId    APIC ID of the target logical processor.
-  @param  Location    Returns the processor location information.
-**/
-VOID
-SmmGetProcessorLocation (
-  IN UINT32 ApicId,
-  OUT EFI_CPU_PHYSICAL_LOCATION *Location
-  )
-{
-  UINTN   ThreadBits;
-  UINTN   CoreBits;
-  UINT32  RegEax;
-  UINT32  RegEbx;
-  UINT32  RegEcx;
-  UINT32  RegEdx;
-  UINT32  MaxCpuIdIndex;
-  UINT32  SubIndex;
-  UINTN   LevelType;
-  UINT32  MaxLogicProcessorsPerPackage;
-  UINT32  MaxCoresPerPackage;
-  BOOLEAN TopologyLeafSupported;
-
-  ASSERT (Location != NULL);
-
-  ThreadBits            = 0;
-  CoreBits              = 0;
-  TopologyLeafSupported = FALSE;
-
-  //
-  // Check if the processor is capable of supporting more than one logical processor.
-  //
-  AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);
-  ASSERT ((RegEdx & BIT28) != 0);
-
-  //
-  // Assume three-level mapping of APIC ID: Package:Core:SMT.
-  //
-
-  //
-  // Get the max index of basic CPUID
-  //
-  AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
-
-  //
-  // If the extended topology enumeration leaf is available, it
-  // is the preferred mechanism for enumerating topology.
-  //
-  if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
-    AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);
-    //
-    // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for
-    // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not
-    // supported on that processor.
-    //
-    if ((RegEbx & 0xffff) != 0) {
-      TopologyLeafSupported = TRUE;
-
-      //
-      // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
-      // the SMT sub-field of x2APIC ID.
-      //
-      LevelType = (RegEcx >> 8) & 0xff;
-      ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);
-      if ((RegEbx & 0xffff) > 1 ) {
-        ThreadBits = RegEax & 0x1f;
-      } else {
-        //
-        // HT is not supported
-        //
-        ThreadBits = 0;
-      }
-
-      //
-      // Software must not assume any "level type" encoding
-      // value to be related to any sub-leaf index, except sub-leaf 0.
-      //
-      SubIndex = 1;
-      do {
-        AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);
-        LevelType = (RegEcx >> 8) & 0xff;
-        if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {
-          CoreBits = (RegEax & 0x1f) - ThreadBits;
-          break;
-        }
-        SubIndex++;
-      } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
-    }
-  }
-
-  if (!TopologyLeafSupported) {
-    AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);
-    MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;
-    if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
-      AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);
-      MaxCoresPerPackage = (RegEax >> 26) + 1;
-    } else {
-      //
-      // Must be a single-core processor.
-      //
-      MaxCoresPerPackage = 1;
-    }
-
-    ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
-    CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);
-  }
-
-  Location->Thread = ApicId & ~((-1) << ThreadBits);
-  Location->Core = (ApicId >> ThreadBits) & ~((-1) << CoreBits);
-  Location->Package = (ApicId >> (ThreadBits+ CoreBits)); -}
-
-/**
   Gets processor information on the requested processor at the instant this call is made.
 
   @param[in]  This                 A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
@@ -280,7 +161,12 @@ SmmAddProcessor (
         gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId == INVALID_APIC_ID) {
       gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId = ProcessorId;
       gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag = 0;
-      SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->ProcessorInfo[Index].Location);
+      GetProcessorLocation (
+        (UINT32)ProcessorId,
+        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package,
+        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core,
+        &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread
+        );
 
       *ProcessorNumber = Index;
       gSmmCpuPrivate->Operation[Index] = SmmCpuAdd;
--
1.9.1



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2016-10-31 19:42 [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Leo Duran
2016-10-31 21:23 ` Laszlo Ersek
2016-10-31 21:26   ` Duran, Leo
2016-10-31 21:29   ` Kinney, Michael D
2016-11-01  0:48     ` Fan, Jeff
2016-11-01  2:25 ` Fan, Jeff
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2016-10-28 17:08 Leo Duran
2016-10-28 17:10 ` Duran, Leo
2016-10-28 16:26 [PATCH] UefiCpuPkg: GetProcessorLocation() Leo Duran
2016-10-28 16:26 ` [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Leo Duran
2016-10-28 16:38   ` Laszlo Ersek
2016-10-28 16:49     ` Duran, Leo

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