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charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Laszlo Ersek [mailto:lersek@redhat.com] > Sent: Monday, October 31, 2016 4:24 PM > To: Duran, Leo ; edk2-devel@ml01.01.org > Cc: liming.gao@intel.com; jeff.fan@intel.com; michael.d.kinney@intel.com > Subject: Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to > LocalApicLib library >=20 > On 10/31/16 20:42, Leo Duran wrote: > > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. > > 2) Remove ExtractProcessorLocation() from MpInitLib library. > > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. > > > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Signed-off-by: Leo Duran > > --- > > UefiCpuPkg/Include/Library/LocalApicLib.h | 20 +++ > > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 146 > +++++++++++++++++++++ > > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 146 > +++++++++++++++++++++ > > UefiCpuPkg/Library/MpInitLib/MpLib.c | 133 +------------= ------ > > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 126 +------------= ----- > > 5 files changed, 324 insertions(+), 247 deletions(-) >=20 > (1) This patch should carry a "Signed-off-by" from Mike as well -- it is = my > understanding that this v4 patch is the result of joint work (it contains= new > code from two people). >=20 > I don't think it's necessary to repost the patch for this: if Mike respon= ds with > his S-o-b, then I believe Jeff can simply add that tag as well at commit = time. >=20 [Duran, Leo]=20 Yes, please make that happen. Thanks. > (2) I repeated my tests as described in > ; > the v4 patch too works fine. >=20 > Tested-by: Laszlo Ersek >=20 [Duran, Leo]=20 Great, thanks. > Thanks > Laszlo >=20 > > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h > > b/UefiCpuPkg/Include/Library/LocalApicLib.h > > index cd4e613..179409e 100644 > > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h > > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h > > @@ -410,6 +410,26 @@ GetApicMsiValue ( > > IN BOOLEAN LevelTriggered, > > IN BOOLEAN AssertionLevel > > ); > > + > > +/** > > + Get Package ID/Core ID/Thread ID of a processor. > > + > > + The algorithm assumes the target system has symmetry across > > + physical package boundaries with respect to the number of logical > > + processors per package, number of cores per package. > > + > > + @param[in] InitialApicId Initial APIC ID of the target logical pro= cessor. > > + @param[out] Package Returns the processor package ID. > > + @param[out] Core Returns the processor core ID. > > + @param[out] Thread Returns the processor thread ID. > > +**/ > > +VOID > > +GetProcessorLocation( > > + IN UINT32 InitialApicId, > > + OUT UINT32 *Package OPTIONAL, > > + OUT UINT32 *Core OPTIONAL, > > + OUT UINT32 *Thread OPTIONAL > > + ); > > > > #endif > > > > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > index 8d0fb02..f32d287 100644 > > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > > @@ -941,3 +941,149 @@ GetApicMsiValue ( > > } > > return MsiData.Uint64; > > } > > + > > +/** > > + Get Package ID/Core ID/Thread ID of a processor. > > + > > + The algorithm assumes the target system has symmetry across > > + physical package boundaries with respect to the number of logical > > + processors per package, number of cores per package. > > + > > + @param[in] InitialApicId Initial APIC ID of the target logical pro= cessor. > > + @param[out] Package Returns the processor package ID. > > + @param[out] Core Returns the processor core ID. > > + @param[out] Thread Returns the processor thread ID. > > +**/ > > +VOID > > +GetProcessorLocation( > > + IN UINT32 InitialApicId, > > + OUT UINT32 *Package OPTIONAL, > > + OUT UINT32 *Core OPTIONAL, > > + OUT UINT32 *Thread OPTIONAL > > + ) > > +{ > > + BOOLEAN TopologyLeafSupported; > > + UINTN ThreadBits; > > + UINTN CoreBits; > > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > + UINT32 MaxCpuIdIndex; > > + UINT32 SubIndex; > > + UINTN LevelType; > > + UINT32 MaxLogicProcessorsPerPackage; > > + UINT32 MaxCoresPerPackage; > > + > > + // > > + // Check if the processor is capable of supporting more than one log= ical > processor. > > + // > > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > > + &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > + if (Thread !=3D NULL) { > > + *Thread =3D 0; > > + } > > + if (Core !=3D NULL) { > > + *Core =3D 0; > > + } > > + if (Package !=3D NULL) { > > + *Package =3D 0; > > + } > > + return; > > + } > > + > > + ThreadBits =3D 0; > > + CoreBits =3D 0; > > + > > + // > > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > > + // > > + TopologyLeafSupported =3D FALSE; > > + > > + // > > + // Get the max index of basic CPUID // AsmCpuid(CPUID_SIGNATURE, > > + &MaxCpuIdIndex, NULL, NULL, NULL); > > + > > + // > > + // If the extended topology enumeration leaf is available, it // > > + is the preferred mechanism for enumerating topology. > > + // > > + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + 0, > > + &ExtendedTopologyEax.Uint32, > > + &ExtendedTopologyEbx.Uint32, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + // > > + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum inp= ut > value for > > + // basic CPUID information is greater than 0BH, then CPUID.0BH lea= f is > not > > + // supported on that processor. > > + // > > + if (ExtendedTopologyEbx.Uint32 !=3D 0) { > > + TopologyLeafSupported =3D TRUE; > > + > > + // > > + // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration par= ameters > to extract > > + // the SMT sub-field of x2APIC ID. > > + // > > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > + ASSERT(LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > > + > > + // > > + // Software must not assume any "level type" encoding > > + // value to be related to any sub-leaf index, except sub-leaf 0. > > + // > > + SubIndex =3D 1; > > + do { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + SubIndex, > > + &ExtendedTopologyEax.Uint32, > > + NULL, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > + if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) = { > > + CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBi= ts; > > + break; > > + } > > + SubIndex++; > > + } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > + } > > + } > > + > > + if (!TopologyLeafSupported) { > > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, > NULL, NULL); > > + MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > > + MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > + } > > + else { > > + // > > + // Must be a single-core processor. > > + // > > + MaxCoresPerPackage =3D 1; > > + } > > + > > + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } > > + > > + if (Thread !=3D NULL) { > > + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > + } > > + if (Core !=3D NULL) { > > + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1)= ; > > + } > > + if (Package !=3D NULL) { > > + *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); > > + } > > +} > > diff --git > > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > index 4c42696..a34a272 100644 > > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > > @@ -1036,3 +1036,149 @@ GetApicMsiValue ( > > } > > return MsiData.Uint64; > > } > > + > > +/** > > + Get Package ID/Core ID/Thread ID of a processor. > > + > > + The algorithm assumes the target system has symmetry across > > + physical package boundaries with respect to the number of logical > > + processors per package, number of cores per package. > > + > > + @param[in] InitialApicId Initial APIC ID of the target logical pro= cessor. > > + @param[out] Package Returns the processor package ID. > > + @param[out] Core Returns the processor core ID. > > + @param[out] Thread Returns the processor thread ID. > > +**/ > > +VOID > > +GetProcessorLocation( > > + IN UINT32 InitialApicId, > > + OUT UINT32 *Package OPTIONAL, > > + OUT UINT32 *Core OPTIONAL, > > + OUT UINT32 *Thread OPTIONAL > > + ) > > +{ > > + BOOLEAN TopologyLeafSupported; > > + UINTN ThreadBits; > > + UINTN CoreBits; > > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > + UINT32 MaxCpuIdIndex; > > + UINT32 SubIndex; > > + UINTN LevelType; > > + UINT32 MaxLogicProcessorsPerPackage; > > + UINT32 MaxCoresPerPackage; > > + > > + // > > + // Check if the processor is capable of supporting more than one log= ical > processor. > > + // > > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > > + &VersionInfoEdx.Uint32); if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > + if (Thread !=3D NULL) { > > + *Thread =3D 0; > > + } > > + if (Core !=3D NULL) { > > + *Core =3D 0; > > + } > > + if (Package !=3D NULL) { > > + *Package =3D 0; > > + } > > + return; > > + } > > + > > + ThreadBits =3D 0; > > + CoreBits =3D 0; > > + > > + // > > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > > + // > > + TopologyLeafSupported =3D FALSE; > > + > > + // > > + // Get the max index of basic CPUID // AsmCpuid(CPUID_SIGNATURE, > > + &MaxCpuIdIndex, NULL, NULL, NULL); > > + > > + // > > + // If the extended topology enumeration leaf is available, it // > > + is the preferred mechanism for enumerating topology. > > + // > > + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + 0, > > + &ExtendedTopologyEax.Uint32, > > + &ExtendedTopologyEbx.Uint32, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + // > > + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum inp= ut > value for > > + // basic CPUID information is greater than 0BH, then CPUID.0BH lea= f is > not > > + // supported on that processor. > > + // > > + if (ExtendedTopologyEbx.Uint32 !=3D 0) { > > + TopologyLeafSupported =3D TRUE; > > + > > + // > > + // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration par= ameters > to extract > > + // the SMT sub-field of x2APIC ID. > > + // > > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > + ASSERT(LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > > + > > + // > > + // Software must not assume any "level type" encoding > > + // value to be related to any sub-leaf index, except sub-leaf 0. > > + // > > + SubIndex =3D 1; > > + do { > > + AsmCpuidEx( > > + CPUID_EXTENDED_TOPOLOGY, > > + SubIndex, > > + &ExtendedTopologyEax.Uint32, > > + NULL, > > + &ExtendedTopologyEcx.Uint32, > > + NULL > > + ); > > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > + if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) = { > > + CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBi= ts; > > + break; > > + } > > + SubIndex++; > > + } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > + } > > + } > > + > > + if (!TopologyLeafSupported) { > > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, > NULL, NULL); > > + MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > > + MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > + } > > + else { > > + // > > + // Must be a single-core processor. > > + // > > + MaxCoresPerPackage =3D 1; > > + } > > + > > + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } > > + > > + if (Thread !=3D NULL) { > > + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > + } > > + if (Core !=3D NULL) { > > + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1)= ; > > + } > > + if (Package !=3D NULL) { > > + *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); > > + } > > +} > > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c > > b/UefiCpuPkg/Library/MpInitLib/MpLib.c > > index c3fe721..e48ff6a 100644 > > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( } > > > > /** > > - Get CPU Package/Core/Thread location information. > > - > > - @param[in] InitialApicId CPU APIC ID > > - @param[out] Location Pointer to CPU location information > > -**/ > > -VOID > > -ExtractProcessorLocation ( > > - IN UINT32 InitialApicId, > > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > > - ) > > -{ > > - BOOLEAN TopologyLeafSupported; > > - UINTN ThreadBits; > > - UINTN CoreBits; > > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > > - UINT32 MaxCpuIdIndex; > > - UINT32 SubIndex; > > - UINTN LevelType; > > - UINT32 MaxLogicProcessorsPerPackage; > > - UINT32 MaxCoresPerPackage; > > - > > - // > > - // Check if the processor is capable of supporting more than one log= ical > processor. > > - // > > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, > > &VersionInfoEdx.Uint32); > > - if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > > - Location->Thread =3D 0; > > - Location->Core =3D 0; > > - Location->Package =3D 0; > > - return; > > - } > > - > > - ThreadBits =3D 0; > > - CoreBits =3D 0; > > - > > - // > > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > > - // > > - > > - TopologyLeafSupported =3D FALSE; > > - // > > - // Get the max index of basic CPUID > > - // > > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > > - > > - // > > - // If the extended topology enumeration leaf is available, it > > - // is the preferred mechanism for enumerating topology. > > - // > > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > - AsmCpuidEx ( > > - CPUID_EXTENDED_TOPOLOGY, > > - 0, > > - &ExtendedTopologyEax.Uint32, > > - &ExtendedTopologyEbx.Uint32, > > - &ExtendedTopologyEcx.Uint32, > > - NULL > > - ); > > - // > > - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum inp= ut > value for > > - // basic CPUID information is greater than 0BH, then CPUID.0BH lea= f is > not > > - // supported on that processor. > > - // > > - if (ExtendedTopologyEbx.Uint32 !=3D 0) { > > - TopologyLeafSupported =3D TRUE; > > - > > - // > > - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration par= ameters > to extract > > - // the SMT sub-field of x2APIC ID. > > - // > > - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > - ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > - ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > > - > > - // > > - // Software must not assume any "level type" encoding > > - // value to be related to any sub-leaf index, except sub-leaf 0. > > - // > > - SubIndex =3D 1; > > - do { > > - AsmCpuidEx ( > > - CPUID_EXTENDED_TOPOLOGY, > > - SubIndex, > > - &ExtendedTopologyEax.Uint32, > > - NULL, > > - &ExtendedTopologyEcx.Uint32, > > - NULL > > - ); > > - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > > - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) = { > > - CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBi= ts; > > - break; > > - } > > - SubIndex++; > > - } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > - } > > - } > > - > > - if (!TopologyLeafSupported) { > > - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, > NULL, NULL); > > - MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > > - MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > > - } else { > > - // > > - // Must be a single-core processor. > > - // > > - MaxCoresPerPackage =3D 1; > > - } > > - > > - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage= / > MaxCoresPerPackage - 1) + 1); > > - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > > - } > > - > > - Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > > - Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBit= s) - 1); > > - Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); -} > > - > > -/** > > Worker function for SwitchBSP(). > > > > Worker function for SwitchBSP(), assigned to the AP which is > > intended @@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo ( > > // > > // Get processor location information > > // > > - ExtractProcessorLocation > > (CpuMpData->CpuData[ProcessorNumber].ApicId, > > &ProcessorInfoBuffer->Location); > > + GetProcessorLocation ( > > + CpuMpData->CpuData[ProcessorNumber].ApicId, > > + &ProcessorInfoBuffer->Location.Package, > > + &ProcessorInfoBuffer->Location.Core, > > + &ProcessorInfoBuffer->Location.Thread > > + ); > > > > if (HealthData !=3D NULL) { > > HealthData->Uint32 =3D CpuMpData->CpuData[ProcessorNumber].Health; > > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > index 40f2a17..f377a36 100644 > > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL > mSmmCpuService =3D { > > }; > > > > /** > > - Get Package ID/Core ID/Thread ID of a processor. > > - > > - APIC ID must be an initial APIC ID. > > - > > - The algorithm below assumes the target system has symmetry across > > physical package boundaries > > - with respect to the number of logical processors per package, number= of > cores per package. > > - > > - @param ApicId APIC ID of the target logical processor. > > - @param Location Returns the processor location information. > > -**/ > > -VOID > > -SmmGetProcessorLocation ( > > - IN UINT32 ApicId, > > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > > - ) > > -{ > > - UINTN ThreadBits; > > - UINTN CoreBits; > > - UINT32 RegEax; > > - UINT32 RegEbx; > > - UINT32 RegEcx; > > - UINT32 RegEdx; > > - UINT32 MaxCpuIdIndex; > > - UINT32 SubIndex; > > - UINTN LevelType; > > - UINT32 MaxLogicProcessorsPerPackage; > > - UINT32 MaxCoresPerPackage; > > - BOOLEAN TopologyLeafSupported; > > - > > - ASSERT (Location !=3D NULL); > > - > > - ThreadBits =3D 0; > > - CoreBits =3D 0; > > - TopologyLeafSupported =3D FALSE; > > - > > - // > > - // Check if the processor is capable of supporting more than one log= ical > processor. > > - // > > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); > > - ASSERT ((RegEdx & BIT28) !=3D 0); > > - > > - // > > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > > - // > > - > > - // > > - // Get the max index of basic CPUID > > - // > > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > > - > > - // > > - // If the extended topology enumeration leaf is available, it > > - // is the preferred mechanism for enumerating topology. > > - // > > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, > &RegEcx, NULL); > > - // > > - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum inp= ut > value for > > - // basic CPUID information is greater than 0BH, then CPUID.0BH lea= f is > not > > - // supported on that processor. > > - // > > - if ((RegEbx & 0xffff) !=3D 0) { > > - TopologyLeafSupported =3D TRUE; > > - > > - // > > - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration par= ameters > to extract > > - // the SMT sub-field of x2APIC ID. > > - // > > - LevelType =3D (RegEcx >> 8) & 0xff; > > - ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > > - if ((RegEbx & 0xffff) > 1 ) { > > - ThreadBits =3D RegEax & 0x1f; > > - } else { > > - // > > - // HT is not supported > > - // > > - ThreadBits =3D 0; > > - } > > - > > - // > > - // Software must not assume any "level type" encoding > > - // value to be related to any sub-leaf index, except sub-leaf 0. > > - // > > - SubIndex =3D 1; > > - do { > > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, > NULL, &RegEcx, NULL); > > - LevelType =3D (RegEcx >> 8) & 0xff; > > - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) = { > > - CoreBits =3D (RegEax & 0x1f) - ThreadBits; > > - break; > > - } > > - SubIndex++; > > - } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > > - } > > - } > > - > > - if (!TopologyLeafSupported) { > > - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); > > - MaxLogicProcessorsPerPackage =3D (RegEbx >> 16) & 0xff; > > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); > > - MaxCoresPerPackage =3D (RegEax >> 26) + 1; > > - } else { > > - // > > - // Must be a single-core processor. > > - // > > - MaxCoresPerPackage =3D 1; > > - } > > - > > - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage= / > MaxCoresPerPackage - 1) + 1); > > - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > > - } > > - > > - Location->Thread =3D ApicId & ~((-1) << ThreadBits); > > - Location->Core =3D (ApicId >> ThreadBits) & ~((-1) << CoreBits); > > - Location->Package =3D (ApicId >> (ThreadBits+ CoreBits)); -} > > - > > -/** > > Gets processor information on the requested processor at the instant= this > call is made. > > > > @param[in] This A pointer to the > EFI_SMM_CPU_SERVICE_PROTOCOL instance. > > @@ -280,7 +161,12 @@ SmmAddProcessor ( > > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D=3D > INVALID_APIC_ID) { > > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D ProcessorId= ; > > gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag =3D 0; > > - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate- > >ProcessorInfo[Index].Location); > > + GetProcessorLocation ( > > + (UINT32)ProcessorId, > > + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package, > > + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core, > > + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread > > + ); > > > > *ProcessorNumber =3D Index; > > gSmmCpuPrivate->Operation[Index] =3D SmmCpuAdd; > >