* [PATCH v3 0/2] UefiCpuPkg: Add CPUID support for AMD.
@ 2017-06-06 15:58 Leo Duran
2017-06-06 15:59 ` [PATCH v3 1/2] UefiCpuPkg: Add CPUID definitions " Leo Duran
2017-06-06 15:59 ` [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD Leo Duran
0 siblings, 2 replies; 8+ messages in thread
From: Leo Duran @ 2017-06-06 15:58 UTC (permalink / raw)
To: edk2-devel; +Cc: Leo Duran
This patch-set requires and builds upon this submission:
https://lists.01.org/pipermail/edk2-devel/2017-May/010867.html
Changes since v2:
- Account for actual thread count (e.g., SMT disabled).
Changes since v1:
- Revert to (MaxCoresPerPackage = 1) when CPUID is not explicit.
Leo Duran (2):
UefiCpuPkg: Add CPUID definitions for AMD.
UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
UefiCpuPkg/Include/Register/Amd/Cpuid.h | 574 ++++++++++++++++++++-
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++--
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++--
3 files changed, 749 insertions(+), 85 deletions(-)
mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
--
2.7.4
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v3 1/2] UefiCpuPkg: Add CPUID definitions for AMD.
2017-06-06 15:58 [PATCH v3 0/2] UefiCpuPkg: Add CPUID support for AMD Leo Duran
@ 2017-06-06 15:59 ` Leo Duran
2017-06-06 15:59 ` [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD Leo Duran
1 sibling, 0 replies; 8+ messages in thread
From: Leo Duran @ 2017-06-06 15:59 UTC (permalink / raw)
To: edk2-devel; +Cc: Leo Duran, Jordan Justen, Jeff Fan, Liming Gao, Brijesh Singh
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/Include/Register/Amd/Cpuid.h | 574 +++++++++++++++++++++++++++++++-
1 file changed, 565 insertions(+), 9 deletions(-)
diff --git a/UefiCpuPkg/Include/Register/Amd/Cpuid.h b/UefiCpuPkg/Include/Register/Amd/Cpuid.h
index 74ffb95..d4d777b 100644
--- a/UefiCpuPkg/Include/Register/Amd/Cpuid.h
+++ b/UefiCpuPkg/Include/Register/Amd/Cpuid.h
@@ -7,6 +7,7 @@
not provided for that register.
Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
+
This program and the accompanying materials are licensed and made available
under the terms and conditions of the BSD License which accompanies this
distribution. The full text of the license may be found at
@@ -24,8 +25,562 @@
#define __AMD_CPUID_H__
/**
+ CPUID Extended Processor Signature and Features
- Memory Encryption Information
+ @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
+
+ @retval EAX Extended Family, Model, Stepping Identifiers
+ described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
+ @retval EBX Brand Identifier
+ described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
+ @retval ECX Extended Feature Identifiers
+ described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
+ @retval EDX Extended Feature Identifiers
+ described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
+**/
+
+/**
+ CPUID Extended Processor Signature and Features EAX for CPUID leaf
+ #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 3:0] Stepping.
+ ///
+ UINT32 Stepping:4;
+ ///
+ /// [Bits 7:4] Base Model.
+ ///
+ UINT32 BaseModel:4;
+ ///
+ /// [Bits 11:8] Base Family.
+ ///
+ UINT32 BaseFamily:4;
+ ///
+ /// [Bit 15:12] Reserved.
+ ///
+ UINT32 Reserved1:4;
+ ///
+ /// [Bits 19:16] Extended Model.
+ ///
+ UINT32 ExtModel:4;
+ ///
+ /// [Bits 27:20] Extended Family.
+ ///
+ UINT32 ExtFamily:8;
+ ///
+ /// [Bit 31:28] Reserved.
+ ///
+ UINT32 Reserved2:4;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EAX;
+
+/**
+ CPUID Extended Processor Signature and Features EBX for CPUID leaf
+ #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 27:0] Reserved.
+ ///
+ UINT32 Reserved:28;
+ ///
+ /// [Bit 31:28] Package Type.
+ ///
+ UINT32 PkgType:4;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EBX;
+
+/**
+ CPUID Extended Processor Signature and Features ECX for CPUID leaf
+ #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] LAHF/SAHF available in 64-bit mode.
+ ///
+ UINT32 LAHF_SAHF:1;
+ ///
+ /// [Bit 1] Core multi-processing legacy mode.
+ ///
+ UINT32 CmpLegacy:1;
+ ///
+ /// [Bit 2] Secure Virtual Mode feature.
+ ///
+ UINT32 SVM:1;
+ ///
+ /// [Bit 3] Extended APIC register space.
+ ///
+ UINT32 ExtApicSpace:1;
+ ///
+ /// [Bit 4] LOCK MOV CR0 means MOV CR8.
+ ///
+ UINT32 AltMovCr8:1;
+ ///
+ /// [Bit 5] LZCNT instruction support.
+ ///
+ UINT32 LZCNT:1;
+ ///
+ /// [Bit 6] SSE4A instruction support.
+ ///
+ UINT32 SSE4A:1;
+ ///
+ /// [Bit 7] Misaligned SSE Mode.
+ ///
+ UINT32 MisAlignSse:1;
+ ///
+ /// [Bit 8] ThreeDNow Prefetch instructions.
+ ///
+ UINT32 PREFETCHW:1;
+ ///
+ /// [Bit 9] OS Visible Work-around support.
+ ///
+ UINT32 OSVW:1;
+ ///
+ /// [Bit 10] Instruction Based Sampling.
+ ///
+ UINT32 IBS:1;
+ ///
+ /// [Bit 11] Extended Operation Support.
+ ///
+ UINT32 XOP:1;
+ ///
+ /// [Bit 12] SKINIT and STGI support.
+ ///
+ UINT32 SKINIT:1;
+ ///
+ /// [Bit 13] Watchdog Timer support.
+ ///
+ UINT32 WDT:1;
+ ///
+ /// [Bit 14] Reserved.
+ ///
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 15] Lightweight Profiling support.
+ ///
+ UINT32 LWP:1;
+ ///
+ /// [Bit 16] 4-Operand FMA instruction support.
+ ///
+ UINT32 FMA4:1;
+ ///
+ /// [Bit 17] Translation Cache Extension.
+ ///
+ UINT32 TCE:1;
+ ///
+ /// [Bit 21:18] Reserved.
+ ///
+ UINT32 Reserved2:4;
+ ///
+ /// [Bit 22] Topology Extensions support.
+ ///
+ UINT32 TopologyExtensions:1;
+ ///
+ /// [Bit 23] Core Performance Counter Extensions.
+ ///
+ UINT32 PerfCtrExtCore:1;
+ ///
+ /// [Bit 25:24] Reserved.
+ ///
+ UINT32 Reserved3:2;
+ ///
+ /// [Bit 26] Data Breakpoint Extension.
+ ///
+ UINT32 DataBreakpointExtension:1;
+ ///
+ /// [Bit 27] Performance Time-Stamp Counter.
+ ///
+ UINT32 PerfTsc:1;
+ ///
+ /// [Bit 28] L3 Performance Counter Extensions.
+ ///
+ UINT32 PerfCtrExtL3:1;
+ ///
+ /// [Bit 29] MWAITX and MONITORX capability.
+ ///
+ UINT32 MwaitExtended:1;
+ ///
+ /// [Bit 31:30] Reserved.
+ ///
+ UINT32 Reserved4:2;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_ECX;
+
+/**
+ CPUID Extended Processor Signature and Features EDX for CPUID leaf
+ #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 0] x87 floating point unit on-chip.
+ ///
+ UINT32 FPU:1;
+ ///
+ /// [Bit 1] Virtual-mode enhancements.
+ ///
+ UINT32 VME:1;
+ ///
+ /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
+ ///
+ UINT32 DE:1;
+ ///
+ /// [Bit 3] Page-size extensions (4 MB pages).
+ ///
+ UINT32 PSE:1;
+ ///
+ /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
+ ///
+ UINT32 TSC:1;
+ ///
+ /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
+ ///
+ UINT32 MSR:1;
+ ///
+ /// [Bit 6] Physical-address extensions (PAE).
+ ///
+ UINT32 PAE:1;
+ ///
+ /// [Bit 7] Machine check exception, CR4.MCE.
+ ///
+ UINT32 MCE:1;
+ ///
+ /// [Bit 8] CMPXCHG8B instruction.
+ ///
+ UINT32 CMPXCHG8B:1;
+ ///
+ /// [Bit 9] APIC exists and is enabled.
+ ///
+ UINT32 APIC:1;
+ ///
+ /// [Bit 10] Reserved.
+ ///
+ UINT32 Reserved1:1;
+ ///
+ /// [Bit 11] SYSCALL and SYSRET instructions.
+ ///
+ UINT32 SYSCALL_SYSRET:1;
+ ///
+ /// [Bit 12] Memory-type range registers.
+ ///
+ UINT32 MTRR:1;
+ ///
+ /// [Bit 13] Page global extension, CR4.PGE.
+ ///
+ UINT32 PGE:1;
+ ///
+ /// [Bit 14] Machine check architecture, MCG_CAP.
+ ///
+ UINT32 MCA:1;
+ ///
+ /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
+ ///
+ UINT32 CMOV:1;
+ ///
+ /// [Bit 16] Page attribute table.
+ ///
+ UINT32 PAT:1;
+ ///
+ /// [Bit 17] Page-size extensions.
+ ///
+ UINT32 PSE36 : 1;
+ ///
+ /// [Bit 19:18] Reserved.
+ ///
+ UINT32 Reserved2:2;
+ ///
+ /// [Bit 20] No-execute page protection.
+ ///
+ UINT32 NX:1;
+ ///
+ /// [Bit 21] Reserved.
+ ///
+ UINT32 Reserved3:1;
+ ///
+ /// [Bit 22] AMD Extensions to MMX instructions.
+ ///
+ UINT32 MmxExt:1;
+ ///
+ /// [Bit 23] MMX instructions.
+ ///
+ UINT32 MMX:1;
+ ///
+ /// [Bit 24] FXSAVE and FXRSTOR instructions.
+ ///
+ UINT32 FFSR:1;
+ ///
+ /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
+ ///
+ UINT32 FFXSR:1;
+ ///
+ /// [Bit 26] 1-GByte large page support.
+ ///
+ UINT32 Page1GB:1;
+ ///
+ /// [Bit 27] RDTSCP intructions.
+ ///
+ UINT32 RDTSCP:1;
+ ///
+ /// [Bit 28] Reserved.
+ ///
+ UINT32 Reserved4:1;
+ ///
+ /// [Bit 29] Long Mode.
+ ///
+ UINT32 LM:1;
+ ///
+ /// [Bit 30] 3DNow! instructions.
+ ///
+ UINT32 ThreeDNow:1;
+ ///
+ /// [Bit 31] AMD Extensions to 3DNow! instructions.
+ ///
+ UINT32 ThreeDNowExt:1;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EDX;
+
+
+/**
+CPUID Linear Physical Address Size
+
+@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
+
+@retval EAX Linear/Physical Address Size described by the type
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
+@retval EBX Linear/Physical Address Size described by the type
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
+@retval ECX Linear/Physical Address Size described by the type
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
+@retval EDX Reserved.
+**/
+
+/**
+ CPUID Linear Physical Address Size EAX for CPUID leaf
+ #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Maximum physical byte address size in bits.
+ ///
+ UINT32 PhysicalAddressBits:8;
+ ///
+ /// [Bits 15:8] Maximum linear byte address size in bits.
+ ///
+ UINT32 LinearAddressBits:8;
+ ///
+ /// [Bits 23:16] Maximum guest physical byte address size in bits.
+ ///
+ UINT32 GuestPhysAddrSize:8;
+ ///
+ /// [Bit 31:24] Reserved.
+ ///
+ UINT32 Reserved:8;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;
+
+/**
+ CPUID Linear Physical Address Size EBX for CPUID leaf
+ #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 0] Clear Zero Instruction.
+ ///
+ UINT32 CLZERO:1;
+ ///
+ /// [Bits 1] Instructions retired count support.
+ ///
+ UINT32 IRPerf:1;
+ ///
+ /// [Bits 2] Restore error pointers for XSave instructions.
+ ///
+ UINT32 XSaveErPtr:1;
+ ///
+ /// [Bit 31:3] Reserved.
+ ///
+ UINT32 Reserved:29;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;
+
+/**
+ CPUID Linear Physical Address Size ECX for CPUID leaf
+ #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Number of threads - 1.
+ ///
+ UINT32 NC:8;
+ ///
+ /// [Bit 11:8] Reserved.
+ ///
+ UINT32 Reserved1:4;
+ ///
+ /// [Bits 15:12] APIC ID size.
+ ///
+ UINT32 ApicIdCoreIdSize:4;
+ ///
+ /// [Bits 17:16] Performance time-stamp counter size.
+ ///
+ UINT32 PerfTscSize:2;
+ ///
+ /// [Bit 31:18] Reserved.
+ ///
+ UINT32 Reserved2:14;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;
+
+
+/**
+ CPUID AMD Processor Topology
+
+ @param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
+
+ @retval EAX Extended APIC ID described by the type
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
+ @retval EBX Core Indentifiers described by the type
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
+ @retval ECX Node Indentifiers described by the type
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
+ @retval EDX Reserved.
+**/
+#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E
+
+/**
+ CPUID AMD Processor Topology EAX for CPUID leaf
+ #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bit 31:0] Extended APIC Id.
+ ///
+ UINT32 ExtendedApicId;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;
+
+/**
+ CPUID AMD Processor Topology EBX for CPUID leaf
+ #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Core Id.
+ ///
+ UINT32 CoreId:8;
+ ///
+ /// [Bits 15:8] Threads per core.
+ ///
+ UINT32 ThreadsPerCore:8;
+ ///
+ /// [Bit 31:16] Reserved.
+ ///
+ UINT32 Reserved:16;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;
+
+/**
+ CPUID AMD Processor Topology ECX for CPUID leaf
+ #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+ ///
+ /// Individual bit fields
+ ///
+ struct {
+ ///
+ /// [Bits 7:0] Node Id.
+ ///
+ UINT32 NodeId:8;
+ ///
+ /// [Bits 10:8] Nodes per processor.
+ ///
+ UINT32 NodesPerProcessor:3;
+ ///
+ /// [Bit 31:11] Reserved.
+ ///
+ UINT32 Reserved:21;
+ } Bits;
+ ///
+ /// All bit fields as a 32-bit value
+ ///
+ UINT32 Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;
+
+
+/**
+ CPUID Memory Encryption Information
@param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
@@ -33,8 +588,8 @@
@retval EBX If memory encryption feature is present then return
the page table bit number used to enable memory encryption support
and reducing of physical address space in bits.
- @retval ECX Returns number of encrypted guest supported simultaneosuly.
- @retval EDX Returns minimum SEV enabled and SEV disbled ASID..
+ @retval ECX Returns number of encrypted guest supported simultaneously.
+ @retval EDX Returns minimum SEV enabled and SEV disabled ASID.
<b>Example usage</b>
@code
@@ -79,7 +634,7 @@ typedef union {
UINT32 SevEsBit:1;
///
- /// [Bit 4:31] Reserved
+ /// [Bit 31:4] Reserved
///
UINT32 ReservedBits:28;
} Bits;
@@ -99,17 +654,18 @@ typedef union {
///
struct {
///
- /// [Bit 0:5] Page table bit number used to enable memory encryption
+ /// [Bit 5:0] Page table bit number used to enable memory encryption
///
UINT32 PtePosBits:6;
///
- /// [Bit 6:11] Reduction of system physical address space bits when memory encryption is enabled
+ /// [Bit 11:6] Reduction of system physical address space bits when
+ /// memory encryption is enabled
///
UINT32 ReducedPhysBits:5;
///
- /// [Bit 12:31] Reserved
+ /// [Bit 31:12] Reserved
///
UINT32 ReservedBits:21;
} Bits;
@@ -129,7 +685,7 @@ typedef union {
///
struct {
///
- /// [Bit 0:31] Number of encrypted guest supported simultaneously
+ /// [Bit 31:0] Number of encrypted guest supported simultaneously
///
UINT32 NumGuests;
} Bits;
@@ -149,7 +705,7 @@ typedef union {
///
struct {
///
- /// [Bit 0:31] Minimum SEV enabled, SEV-ES disabled ASID
+ /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
///
UINT32 MinAsid;
} Bits;
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
2017-06-06 15:58 [PATCH v3 0/2] UefiCpuPkg: Add CPUID support for AMD Leo Duran
2017-06-06 15:59 ` [PATCH v3 1/2] UefiCpuPkg: Add CPUID definitions " Leo Duran
@ 2017-06-06 15:59 ` Leo Duran
2017-06-08 5:34 ` Fan, Jeff
1 sibling, 1 reply; 8+ messages in thread
From: Leo Duran @ 2017-06-06 15:59 UTC (permalink / raw)
To: edk2-devel; +Cc: Leo Duran, Jordan Justen, Jeff Fan, Liming Gao, Brijesh Singh
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++------
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++------
2 files changed, 184 insertions(+), 76 deletions(-)
mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index f81bbb2..02dfabc
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -4,6 +4,8 @@
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,6 +17,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index e690d2a..726e1e0 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -5,6 +5,8 @@
which have xAPIC and x2APIC modes.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,6 +18,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
2017-06-06 15:59 ` [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD Leo Duran
@ 2017-06-08 5:34 ` Fan, Jeff
2017-06-08 5:36 ` Fan, Jeff
0 siblings, 1 reply; 8+ messages in thread
From: Fan, Jeff @ 2017-06-08 5:34 UTC (permalink / raw)
To: Leo Duran, edk2-devel@lists.01.org
Cc: Justen, Jordan L, Gao, Liming, Brijesh Singh
Leo,
1. If Intel SDM supports the ExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY(0x in the future, the following code may cause expected result for Intel processor.
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY)
May we use another way to check AMD or Intel processor?
2. Goto Statements should not be used (in general) except for error handling (https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf)
Thanks!
Jeff
-----Original Message-----
From: Leo Duran [mailto:leo.duran@amd.com]
Sent: Tuesday, June 06, 2017 11:59 PM
To: edk2-devel@lists.01.org
Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh
Subject: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++------
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++------
2 files changed, 184 insertions(+), 76 deletions(-)
mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index f81bbb2..02dfabc
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -4,6 +4,8 @@
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -15,6 +17,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index e690d2a..726e1e0 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -5,6 +5,8 @@
which have xAPIC and x2APIC modes.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
@@ -16,6 +18,7 @@
**/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL, NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
+ MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage / (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage / (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
2017-06-08 5:34 ` Fan, Jeff
@ 2017-06-08 5:36 ` Fan, Jeff
2017-06-09 20:12 ` Duran, Leo
0 siblings, 1 reply; 8+ messages in thread
From: Fan, Jeff @ 2017-06-08 5:36 UTC (permalink / raw)
To: Fan, Jeff, Leo Duran, edk2-devel@lists.01.org
Cc: Justen, Jordan L, Gao, Liming
Leo,
Correct some words in below mail body.
Jeff
-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Fan, Jeff
Sent: Thursday, June 08, 2017 1:34 PM
To: Leo Duran; edk2-devel@lists.01.org
Cc: Justen, Jordan L; Gao, Liming
Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
Leo,
1. If Intel SDM supports the ExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY(0x8000001E) in the future, the following code may cause unexpected result for Intel processor.
if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY)
May we use another way to check AMD or Intel processor?
2. Goto Statements should not be used (in general) except for error handling (https://github.com/tianocore-docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf)
Thanks!
Jeff
-----Original Message-----
From: Leo Duran [mailto:leo.duran@amd.com]
Sent: Tuesday, June 06, 2017 11:59 PM
To: edk2-devel@lists.01.org
Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh
Subject: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
---
UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++------
.../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++------
2 files changed, 184 insertions(+), 76 deletions(-) mode change 100644 => 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
old mode 100644
new mode 100755
index f81bbb2..02dfabc
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -4,6 +4,8 @@
This local APIC library instance supports xAPIC mode only.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at @@ -15,6 +17,7 @@ **/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL,
+ NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
+ NULL); MaxLogicProcessorsPerPackage =
+ VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
+ (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage /
+ (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
+MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits)); diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index e690d2a..726e1e0 100644
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -5,6 +5,8 @@
which have xAPIC and x2APIC modes.
Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
+
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at @@ -16,6 +18,7 @@ **/
#include <Register/Cpuid.h>
+#include <Register/Amd/Cpuid.h>
#include <Register/Msr.h>
#include <Register/LocalApic.h>
@@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
OUT UINT32 *Thread OPTIONAL
)
{
- BOOLEAN TopologyLeafSupported;
- UINTN ThreadBits;
- UINTN CoreBits;
- CPUID_VERSION_INFO_EBX VersionInfoEbx;
- CPUID_VERSION_INFO_EDX VersionInfoEdx;
- CPUID_CACHE_PARAMS_EAX CacheParamsEax;
- CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
- CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
- CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
- UINT32 MaxCpuIdIndex;
- UINT32 SubIndex;
- UINTN LevelType;
- UINT32 MaxLogicProcessorsPerPackage;
- UINT32 MaxCoresPerPackage;
+ CPUID_VERSION_INFO_EBX VersionInfoEbx;
+ CPUID_VERSION_INFO_EDX VersionInfoEdx;
+ CPUID_CACHE_PARAMS_EAX CacheParamsEax;
+ CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
+ CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
+ CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
+ CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
+ CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
+ CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
+ UINT32 MaxStandardCpuIdIndex;
+ UINT32 MaxExtendedCpuIdIndex;
+ UINT32 SubIndex;
+ UINTN LevelType;
+ UINT32 MaxLogicProcessorsPerPackage;
+ UINT32 MaxCoresPerPackage;
+ UINT32 MaxThreadPerPackageMask;
+ UINT32 ActualThreadPerPackageMask;
+ UINT32 MaxCoresPerNode;
+ UINT32 CorePerNodeMask;
+ UINT32 ApicIdShift;
+ UINTN ThreadBits;
+ UINTN CoreBits;
//
// Check if the processor is capable of supporting more than one logical processor.
@@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32);
if (VersionInfoEdx.Bits.HTT == 0) {
if (Thread != NULL) {
- *Thread = 0;
+ *Thread = 0;
}
if (Core != NULL) {
- *Core = 0;
+ *Core = 0;
}
if (Package != NULL) {
*Package = 0;
@@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
CoreBits = 0;
//
- // Assume three-level mapping of APIC ID: Package:Core:SMT.
+ // Get the max index of CPUID
//
- TopologyLeafSupported = FALSE;
-
- //
- // Get the max index of basic CPUID
- //
- AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, NULL);
+ AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, NULL, NULL,
+ NULL);
//
// If the extended topology enumeration leaf is available, it
// is the preferred mechanism for enumerating topology.
//
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
+ if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
AsmCpuidEx(
CPUID_EXTENDED_TOPOLOGY,
0,
@@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
// supported on that processor.
//
if (ExtendedTopologyEbx.Uint32 != 0) {
- TopologyLeafSupported = TRUE;
-
//
// Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract
// the SMT sub-field of x2APIC ID.
@@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
}
SubIndex++;
} while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
+ goto GetLocation;
}
}
- if (!TopologyLeafSupported) {
- AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL);
- MaxLogicProcessorsPerPackage = VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
- AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
+ NULL); MaxLogicProcessorsPerPackage =
+ VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
+
+ if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
+ AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, NULL);
+ if (CacheParamsEax.Uint32 != 0) {
MaxCoresPerPackage = CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
+ goto GetBits;
}
- else {
+ }
+
+ if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
+ AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, &AmdExtendedCpuSigEcx.Uint32, NULL);
+ if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
+ AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, &AmdProcessorTopologyEbx.Uint32,
+ &AmdProcessorTopologyEcx.Uint32, NULL);
+
+ MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
+ (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
+
//
- // Must be a single-core processor.
+ // Account for actual thread count (e.g., SMT disabled)
//
- MaxCoresPerPackage = 1;
+ AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, &AmdVirPhyAddressSizeEcx.Uint32, NULL);
+ MaxThreadPerPackageMask = 1 << AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
+ ActualThreadPerPackageMask = 1;
+ while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) {
+ ActualThreadPerPackageMask <<= 1;
+ }
+
+ if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
+ MaxCoresPerNode = MaxCoresPerPackage /
+ (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
+
+ CorePerNodeMask = 1;
+ while (CorePerNodeMask < MaxCoresPerNode) {
+ CorePerNodeMask <<= 1;
+ }
+ CorePerNodeMask -= 1;
+
+ ApicIdShift = 0;
+ do {
+ ApicIdShift += 1;
+ ActualThreadPerPackageMask <<= 1;
+ } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
+
+ //
+ // Adjust APIC Id to report concatenation of Package|Core|Thread.
+ //
+ InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) | (InitialApicId & CorePerNodeMask);
+ }
+
+ goto GetBits;
}
+ }
+
+ //
+ // Must be a single-core processor.
+ //
+ MaxCoresPerPackage = 1;
- ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);
- CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
+GetBits:
+ ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
+MaxCoresPerPackage - 1) + 1);
+ CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
+GetLocation:
if (Thread != NULL) {
- *Thread = InitialApicId & ((1 << ThreadBits) - 1);
+ *Thread = InitialApicId & ((1 << ThreadBits) - 1);
}
if (Core != NULL) {
- *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
+ *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
}
if (Package != NULL) {
*Package = (InitialApicId >> (ThreadBits + CoreBits));
--
2.7.4
_______________________________________________
edk2-devel mailing list
edk2-devel@lists.01.org
https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
2017-06-08 5:36 ` Fan, Jeff
@ 2017-06-09 20:12 ` Duran, Leo
2017-06-15 8:52 ` Fan, Jeff
0 siblings, 1 reply; 8+ messages in thread
From: Duran, Leo @ 2017-06-09 20:12 UTC (permalink / raw)
To: 'Fan, Jeff', edk2-devel@lists.01.org
Cc: Justen, Jordan L, Gao, Liming
Hi Jeff,
Please see my replies below.
Thanks,
Leo.
> -----Original Message-----
> From: Fan, Jeff [mailto:jeff.fan@intel.com]
> Sent: Thursday, June 08, 2017 12:37 AM
> To: Fan, Jeff <jeff.fan@intel.com>; Duran, Leo <leo.duran@amd.com>;
> edk2-devel@lists.01.org
> Cc: Justen, Jordan L <jordan.l.justen@intel.com>; Gao, Liming
> <liming.gao@intel.com>
> Subject: RE: [PATCH v3 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Leo,
>
> Correct some words in below mail body.
>
> Jeff
>
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Fan, Jeff
> Sent: Thursday, June 08, 2017 1:34 PM
> To: Leo Duran; edk2-devel@lists.01.org
> Cc: Justen, Jordan L; Gao, Liming
> Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Leo,
>
> 1. If Intel SDM supports the ExtendedCpuIdIndex >=
> CPUID_AMD_PROCESSOR_TOPOLOGY(0x8000001E) in the future, the
> following code may cause unexpected result for Intel processor.
> if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY)
> May we use another way to check AMD or Intel processor?
[Duran, Leo] Any specific suggestions? Thanks.
>
> 2. Goto Statements should not be used (in general) except for error handling
> (https://github.com/tianocore-
> docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf)
[Duran, Leo] OK, I will not use 'goto' in this case.
>
> Thanks!
> Jeff
>
> -----Original Message-----
> From: Leo Duran [mailto:leo.duran@amd.com]
> Sent: Tuesday, June 06, 2017 11:59 PM
> To: edk2-devel@lists.01.org
> Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh
> Subject: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId()
> to support AMD.
>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Jeff Fan <jeff.fan@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Brijesh Singh <brijesh.singh@amd.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran <leo.duran@amd.com>
> ---
> UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130
> +++++++++++++++------
> .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++--
> ----
> 2 files changed, 184 insertions(+), 76 deletions(-) mode change 100644 =>
> 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
>
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> old mode 100644
> new mode 100755
> index f81bbb2..02dfabc
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> @@ -4,6 +4,8 @@
> This local APIC library instance supports xAPIC mode only.
>
> Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> +
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of the BSD
> License
> which accompanies this distribution. The full text of the license may be
> found at @@ -15,6 +17,7 @@ **/
>
> #include <Register/Cpuid.h>
> +#include <Register/Amd/Cpuid.h>
> #include <Register/Msr.h>
> #include <Register/LocalApic.h>
>
> @@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
> OUT UINT32 *Thread OPTIONAL
> )
> {
> - BOOLEAN TopologyLeafSupported;
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> + UINT32 MaxStandardCpuIdIndex;
> + UINT32 MaxExtendedCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> + UINT32 MaxThreadPerPackageMask;
> + UINT32 ActualThreadPerPackageMask;
> + UINT32 MaxCoresPerNode;
> + UINT32 CorePerNodeMask;
> + UINT32 ApicIdShift;
> + UINTN ThreadBits;
> + UINTN CoreBits;
>
> //
> // Check if the processor is capable of supporting more than one logical
> processor.
> @@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
> AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> if (VersionInfoEdx.Bits.HTT == 0) {
> if (Thread != NULL) {
> - *Thread = 0;
> + *Thread = 0;
> }
> if (Core != NULL) {
> - *Core = 0;
> + *Core = 0;
> }
> if (Package != NULL) {
> *Package = 0;
> @@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
> CoreBits = 0;
>
> //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + // Get the max index of CPUID
> //
> - TopologyLeafSupported = FALSE;
> -
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> NULL);
> + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> NULL, NULL,
> + NULL);
>
> //
> // If the extended topology enumeration leaf is available, it
> // is the preferred mechanism for enumerating topology.
> //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> AsmCpuidEx(
> CPUID_EXTENDED_TOPOLOGY,
> 0,
> @@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
> // supported on that processor.
> //
> if (ExtendedTopologyEbx.Uint32 != 0) {
> - TopologyLeafSupported = TRUE;
> -
> //
> // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> // the SMT sub-field of x2APIC ID.
> @@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
> }
> SubIndex++;
> } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> + goto GetLocation;
> }
> }
>
> - if (!TopologyLeafSupported) {
> - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> NULL);
> - MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> + NULL); MaxLogicProcessorsPerPackage =
> + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +
> + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + if (CacheParamsEax.Uint32 != 0) {
> MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + goto GetBits;
> }
> - else {
> + }
> +
> + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> &AmdExtendedCpuSigEcx.Uint32, NULL);
> + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> &AmdProcessorTopologyEbx.Uint32,
> + &AmdProcessorTopologyEcx.Uint32, NULL);
> +
> + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> +
> //
> - // Must be a single-core processor.
> + // Account for actual thread count (e.g., SMT disabled)
> //
> - MaxCoresPerPackage = 1;
> + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> + MaxThreadPerPackageMask = 1 <<
> AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> + ActualThreadPerPackageMask = 1;
> + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage)
> {
> + ActualThreadPerPackageMask <<= 1;
> + }
> +
> + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> + MaxCoresPerNode = MaxCoresPerPackage /
> + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> +
> + CorePerNodeMask = 1;
> + while (CorePerNodeMask < MaxCoresPerNode) {
> + CorePerNodeMask <<= 1;
> + }
> + CorePerNodeMask -= 1;
> +
> + ApicIdShift = 0;
> + do {
> + ApicIdShift += 1;
> + ActualThreadPerPackageMask <<= 1;
> + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
> +
> + //
> + // Adjust APIC Id to report concatenation of Package|Core|Thread.
> + //
> + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) |
> (InitialApicId & CorePerNodeMask);
> + }
> +
> + goto GetBits;
> }
> + }
> +
> + //
> + // Must be a single-core processor.
> + //
> + MaxCoresPerPackage = 1;
>
> - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> +GetBits:
> + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> +MaxCoresPerPackage - 1) + 1);
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
>
> +GetLocation:
> if (Thread != NULL) {
> - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> }
> if (Core != NULL) {
> - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> }
> if (Package != NULL) {
> *Package = (InitialApicId >> (ThreadBits + CoreBits)); diff --git
> a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> index e690d2a..726e1e0 100644
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> @@ -5,6 +5,8 @@
> which have xAPIC and x2APIC modes.
>
> Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
> + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> +
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of the BSD
> License
> which accompanies this distribution. The full text of the license may be
> found at @@ -16,6 +18,7 @@ **/
>
> #include <Register/Cpuid.h>
> +#include <Register/Amd/Cpuid.h>
> #include <Register/Msr.h>
> #include <Register/LocalApic.h>
>
> @@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
> OUT UINT32 *Thread OPTIONAL
> )
> {
> - BOOLEAN TopologyLeafSupported;
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> + UINT32 MaxStandardCpuIdIndex;
> + UINT32 MaxExtendedCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> + UINT32 MaxThreadPerPackageMask;
> + UINT32 ActualThreadPerPackageMask;
> + UINT32 MaxCoresPerNode;
> + UINT32 CorePerNodeMask;
> + UINT32 ApicIdShift;
> + UINTN ThreadBits;
> + UINTN CoreBits;
>
> //
> // Check if the processor is capable of supporting more than one logical
> processor.
> @@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
> AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> if (VersionInfoEdx.Bits.HTT == 0) {
> if (Thread != NULL) {
> - *Thread = 0;
> + *Thread = 0;
> }
> if (Core != NULL) {
> - *Core = 0;
> + *Core = 0;
> }
> if (Package != NULL) {
> *Package = 0;
> @@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
> CoreBits = 0;
>
> //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + // Get the max index of CPUID
> //
> - TopologyLeafSupported = FALSE;
> -
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> NULL);
> + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> NULL, NULL,
> + NULL);
>
> //
> // If the extended topology enumeration leaf is available, it
> // is the preferred mechanism for enumerating topology.
> //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> AsmCpuidEx(
> CPUID_EXTENDED_TOPOLOGY,
> 0,
> @@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
> // supported on that processor.
> //
> if (ExtendedTopologyEbx.Uint32 != 0) {
> - TopologyLeafSupported = TRUE;
> -
> //
> // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to
> extract
> // the SMT sub-field of x2APIC ID.
> @@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
> }
> SubIndex++;
> } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> + goto GetLocation;
> }
> }
>
> - if (!TopologyLeafSupported) {
> - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> NULL);
> - MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> + NULL); MaxLogicProcessorsPerPackage =
> + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +
> + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + if (CacheParamsEax.Uint32 != 0) {
> MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + goto GetBits;
> }
> - else {
> + }
> +
> + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> &AmdExtendedCpuSigEcx.Uint32, NULL);
> + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> &AmdProcessorTopologyEbx.Uint32,
> + &AmdProcessorTopologyEcx.Uint32, NULL);
> +
> + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> +
> //
> - // Must be a single-core processor.
> + // Account for actual thread count (e.g., SMT disabled)
> //
> - MaxCoresPerPackage = 1;
> + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> + MaxThreadPerPackageMask = 1 <<
> AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> + ActualThreadPerPackageMask = 1;
> + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage)
> {
> + ActualThreadPerPackageMask <<= 1;
> + }
> +
> + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> + MaxCoresPerNode = MaxCoresPerPackage /
> + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> +
> + CorePerNodeMask = 1;
> + while (CorePerNodeMask < MaxCoresPerNode) {
> + CorePerNodeMask <<= 1;
> + }
> + CorePerNodeMask -= 1;
> +
> + ApicIdShift = 0;
> + do {
> + ApicIdShift += 1;
> + ActualThreadPerPackageMask <<= 1;
> + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask);
> +
> + //
> + // Adjust APIC Id to report concatenation of Package|Core|Thread.
> + //
> + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >> ApicIdShift) |
> (InitialApicId & CorePerNodeMask);
> + }
> +
> + goto GetBits;
> }
> + }
> +
> + //
> + // Must be a single-core processor.
> + //
> + MaxCoresPerPackage = 1;
>
> - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> +GetBits:
> + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> +MaxCoresPerPackage - 1) + 1);
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
>
> +GetLocation:
> if (Thread != NULL) {
> - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> }
> if (Core != NULL) {
> - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> }
> if (Package != NULL) {
> *Package = (InitialApicId >> (ThreadBits + CoreBits));
> --
> 2.7.4
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
2017-06-09 20:12 ` Duran, Leo
@ 2017-06-15 8:52 ` Fan, Jeff
2017-06-15 16:28 ` Kirkendall, Garrett
0 siblings, 1 reply; 8+ messages in thread
From: Fan, Jeff @ 2017-06-15 8:52 UTC (permalink / raw)
To: Duran, Leo, edk2-devel@lists.01.org; +Cc: Justen, Jordan L, Gao, Liming
Leo,
Could you use the CPUID Fn0000_0000_E[D,C,B]X values as below to identify AMD processor?
Table E-1. CPUID Fn0000_0000_E[D,C,B]X values
Register Value Description
CPUID Fn0000_0000_EBX 6874_7541h The ASCII characters "h t u A".
CPUID Fn0000_0000_ECX 444D_4163h The ASCII characters "D M A c".
CPUID Fn0000_0000_EDX 6974_6E65h The ASCII characters "i t n e".
Maybe, your guys have other better solution.
Thanks!
Jeff
-----Original Message-----
From: Duran, Leo [mailto:leo.duran@amd.com]
Sent: Saturday, June 10, 2017 4:12 AM
To: Fan, Jeff; edk2-devel@lists.01.org
Cc: Justen, Jordan L; Gao, Liming
Subject: RE: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
Hi Jeff,
Please see my replies below.
Thanks,
Leo.
> -----Original Message-----
> From: Fan, Jeff [mailto:jeff.fan@intel.com]
> Sent: Thursday, June 08, 2017 12:37 AM
> To: Fan, Jeff <jeff.fan@intel.com>; Duran, Leo <leo.duran@amd.com>;
> edk2-devel@lists.01.org
> Cc: Justen, Jordan L <jordan.l.justen@intel.com>; Gao, Liming
> <liming.gao@intel.com>
> Subject: RE: [PATCH v3 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Leo,
>
> Correct some words in below mail body.
>
> Jeff
>
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Fan, Jeff
> Sent: Thursday, June 08, 2017 1:34 PM
> To: Leo Duran; edk2-devel@lists.01.org
> Cc: Justen, Jordan L; Gao, Liming
> Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Leo,
>
> 1. If Intel SDM supports the ExtendedCpuIdIndex >=
> CPUID_AMD_PROCESSOR_TOPOLOGY(0x8000001E) in the future, the following
> code may cause unexpected result for Intel processor.
> if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY)
> May we use another way to check AMD or Intel processor?
[Duran, Leo] Any specific suggestions? Thanks.
>
> 2. Goto Statements should not be used (in general) except for error
> handling
> (https://github.com/tianocore-
> docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf)
[Duran, Leo] OK, I will not use 'goto' in this case.
>
> Thanks!
> Jeff
>
> -----Original Message-----
> From: Leo Duran [mailto:leo.duran@amd.com]
> Sent: Tuesday, June 06, 2017 11:59 PM
> To: edk2-devel@lists.01.org
> Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh
> Subject: [PATCH v3 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Cc: Jordan Justen <jordan.l.justen@intel.com>
> Cc: Jeff Fan <jeff.fan@intel.com>
> Cc: Liming Gao <liming.gao@intel.com>
> Cc: Brijesh Singh <brijesh.singh@amd.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Leo Duran <leo.duran@amd.com>
> ---
> UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130
> +++++++++++++++------
> .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++--
> ----
> 2 files changed, 184 insertions(+), 76 deletions(-) mode change
> 100644 =>
> 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
>
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> old mode 100644
> new mode 100755
> index f81bbb2..02dfabc
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> @@ -4,6 +4,8 @@
> This local APIC library instance supports xAPIC mode only.
>
> Copyright (c) 2010 - 2016, Intel Corporation. All rights
> reserved.<BR>
> + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> +
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of
> the BSD License
> which accompanies this distribution. The full text of the license
> may be found at @@ -15,6 +17,7 @@ **/
>
> #include <Register/Cpuid.h>
> +#include <Register/Amd/Cpuid.h>
> #include <Register/Msr.h>
> #include <Register/LocalApic.h>
>
> @@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
> OUT UINT32 *Thread OPTIONAL
> )
> {
> - BOOLEAN TopologyLeafSupported;
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> + UINT32 MaxStandardCpuIdIndex;
> + UINT32 MaxExtendedCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> + UINT32 MaxThreadPerPackageMask;
> + UINT32 ActualThreadPerPackageMask;
> + UINT32 MaxCoresPerNode;
> + UINT32 CorePerNodeMask;
> + UINT32 ApicIdShift;
> + UINTN ThreadBits;
> + UINTN CoreBits;
>
> //
> // Check if the processor is capable of supporting more than one
> logical processor.
> @@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
> AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> if (VersionInfoEdx.Bits.HTT == 0) {
> if (Thread != NULL) {
> - *Thread = 0;
> + *Thread = 0;
> }
> if (Core != NULL) {
> - *Core = 0;
> + *Core = 0;
> }
> if (Package != NULL) {
> *Package = 0;
> @@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
> CoreBits = 0;
>
> //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + // Get the max index of CPUID
> //
> - TopologyLeafSupported = FALSE;
> -
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> NULL);
> + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> NULL, NULL,
> + NULL);
>
> //
> // If the extended topology enumeration leaf is available, it
> // is the preferred mechanism for enumerating topology.
> //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> AsmCpuidEx(
> CPUID_EXTENDED_TOPOLOGY,
> 0,
> @@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
> // supported on that processor.
> //
> if (ExtendedTopologyEbx.Uint32 != 0) {
> - TopologyLeafSupported = TRUE;
> -
> //
> // Sub-leaf index 0 (ECX= 0 as input) provides enumeration
> parameters to extract
> // the SMT sub-field of x2APIC ID.
> @@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
> }
> SubIndex++;
> } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> + goto GetLocation;
> }
> }
>
> - if (!TopologyLeafSupported) {
> - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> NULL);
> - MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> + NULL); MaxLogicProcessorsPerPackage =
> + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +
> + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + if (CacheParamsEax.Uint32 != 0) {
> MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + goto GetBits;
> }
> - else {
> + }
> +
> + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> &AmdExtendedCpuSigEcx.Uint32, NULL);
> + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> &AmdProcessorTopologyEbx.Uint32,
> + &AmdProcessorTopologyEcx.Uint32, NULL);
> +
> + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> +
> //
> - // Must be a single-core processor.
> + // Account for actual thread count (e.g., SMT disabled)
> //
> - MaxCoresPerPackage = 1;
> + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> + MaxThreadPerPackageMask = 1 <<
> AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> + ActualThreadPerPackageMask = 1;
> + while (ActualThreadPerPackageMask <
> + MaxLogicProcessorsPerPackage)
> {
> + ActualThreadPerPackageMask <<= 1;
> + }
> +
> + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> + MaxCoresPerNode = MaxCoresPerPackage /
> + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> +
> + CorePerNodeMask = 1;
> + while (CorePerNodeMask < MaxCoresPerNode) {
> + CorePerNodeMask <<= 1;
> + }
> + CorePerNodeMask -= 1;
> +
> + ApicIdShift = 0;
> + do {
> + ApicIdShift += 1;
> + ActualThreadPerPackageMask <<= 1;
> + } while (ActualThreadPerPackageMask <
> + MaxThreadPerPackageMask);
> +
> + //
> + // Adjust APIC Id to report concatenation of Package|Core|Thread.
> + //
> + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >>
> + ApicIdShift) |
> (InitialApicId & CorePerNodeMask);
> + }
> +
> + goto GetBits;
> }
> + }
> +
> + //
> + // Must be a single-core processor.
> + //
> + MaxCoresPerPackage = 1;
>
> - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> +GetBits:
> + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> +MaxCoresPerPackage - 1) + 1);
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
>
> +GetLocation:
> if (Thread != NULL) {
> - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> }
> if (Core != NULL) {
> - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> }
> if (Package != NULL) {
> *Package = (InitialApicId >> (ThreadBits + CoreBits)); diff --git
> a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> index e690d2a..726e1e0 100644
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> @@ -5,6 +5,8 @@
> which have xAPIC and x2APIC modes.
>
> Copyright (c) 2010 - 2016, Intel Corporation. All rights
> reserved.<BR>
> + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> +
> This program and the accompanying materials
> are licensed and made available under the terms and conditions of
> the BSD License
> which accompanies this distribution. The full text of the license
> may be found at @@ -16,6 +18,7 @@ **/
>
> #include <Register/Cpuid.h>
> +#include <Register/Amd/Cpuid.h>
> #include <Register/Msr.h>
> #include <Register/LocalApic.h>
>
> @@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
> OUT UINT32 *Thread OPTIONAL
> )
> {
> - BOOLEAN TopologyLeafSupported;
> - UINTN ThreadBits;
> - UINTN CoreBits;
> - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> - UINT32 MaxCpuIdIndex;
> - UINT32 SubIndex;
> - UINTN LevelType;
> - UINT32 MaxLogicProcessorsPerPackage;
> - UINT32 MaxCoresPerPackage;
> + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> + UINT32 MaxStandardCpuIdIndex;
> + UINT32 MaxExtendedCpuIdIndex;
> + UINT32 SubIndex;
> + UINTN LevelType;
> + UINT32 MaxLogicProcessorsPerPackage;
> + UINT32 MaxCoresPerPackage;
> + UINT32 MaxThreadPerPackageMask;
> + UINT32 ActualThreadPerPackageMask;
> + UINT32 MaxCoresPerNode;
> + UINT32 CorePerNodeMask;
> + UINT32 ApicIdShift;
> + UINTN ThreadBits;
> + UINTN CoreBits;
>
> //
> // Check if the processor is capable of supporting more than one
> logical processor.
> @@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
> AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> &VersionInfoEdx.Uint32);
> if (VersionInfoEdx.Bits.HTT == 0) {
> if (Thread != NULL) {
> - *Thread = 0;
> + *Thread = 0;
> }
> if (Core != NULL) {
> - *Core = 0;
> + *Core = 0;
> }
> if (Package != NULL) {
> *Package = 0;
> @@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
> CoreBits = 0;
>
> //
> - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> + // Get the max index of CPUID
> //
> - TopologyLeafSupported = FALSE;
> -
> - //
> - // Get the max index of basic CPUID
> - //
> - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> NULL);
> + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> NULL, NULL,
> + NULL);
>
> //
> // If the extended topology enumeration leaf is available, it
> // is the preferred mechanism for enumerating topology.
> //
> - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> AsmCpuidEx(
> CPUID_EXTENDED_TOPOLOGY,
> 0,
> @@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
> // supported on that processor.
> //
> if (ExtendedTopologyEbx.Uint32 != 0) {
> - TopologyLeafSupported = TRUE;
> -
> //
> // Sub-leaf index 0 (ECX= 0 as input) provides enumeration
> parameters to extract
> // the SMT sub-field of x2APIC ID.
> @@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
> }
> SubIndex++;
> } while (LevelType !=
> CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> + goto GetLocation;
> }
> }
>
> - if (!TopologyLeafSupported) {
> - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> NULL);
> - MaxLogicProcessorsPerPackage =
> VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> + NULL); MaxLogicProcessorsPerPackage =
> + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> +
> + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> NULL, NULL, NULL);
> + if (CacheParamsEax.Uint32 != 0) {
> MaxCoresPerPackage =
> CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> + goto GetBits;
> }
> - else {
> + }
> +
> + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> &AmdExtendedCpuSigEcx.Uint32, NULL);
> + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> &AmdProcessorTopologyEbx.Uint32,
> + &AmdProcessorTopologyEcx.Uint32, NULL);
> +
> + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> +
> //
> - // Must be a single-core processor.
> + // Account for actual thread count (e.g., SMT disabled)
> //
> - MaxCoresPerPackage = 1;
> + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> + MaxThreadPerPackageMask = 1 <<
> AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> + ActualThreadPerPackageMask = 1;
> + while (ActualThreadPerPackageMask <
> + MaxLogicProcessorsPerPackage)
> {
> + ActualThreadPerPackageMask <<= 1;
> + }
> +
> + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> + MaxCoresPerNode = MaxCoresPerPackage /
> + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> +
> + CorePerNodeMask = 1;
> + while (CorePerNodeMask < MaxCoresPerNode) {
> + CorePerNodeMask <<= 1;
> + }
> + CorePerNodeMask -= 1;
> +
> + ApicIdShift = 0;
> + do {
> + ApicIdShift += 1;
> + ActualThreadPerPackageMask <<= 1;
> + } while (ActualThreadPerPackageMask <
> + MaxThreadPerPackageMask);
> +
> + //
> + // Adjust APIC Id to report concatenation of Package|Core|Thread.
> + //
> + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >>
> + ApicIdShift) |
> (InitialApicId & CorePerNodeMask);
> + }
> +
> + goto GetBits;
> }
> + }
> +
> + //
> + // Must be a single-core processor.
> + //
> + MaxCoresPerPackage = 1;
>
> - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> MaxCoresPerPackage - 1) + 1);
> - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> +GetBits:
> + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> +MaxCoresPerPackage - 1) + 1);
> + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
>
> +GetLocation:
> if (Thread != NULL) {
> - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> }
> if (Core != NULL) {
> - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> }
> if (Package != NULL) {
> *Package = (InitialApicId >> (ThreadBits + CoreBits));
> --
> 2.7.4
>
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD.
2017-06-15 8:52 ` Fan, Jeff
@ 2017-06-15 16:28 ` Kirkendall, Garrett
0 siblings, 0 replies; 8+ messages in thread
From: Kirkendall, Garrett @ 2017-06-15 16:28 UTC (permalink / raw)
To: Fan, Jeff, Duran, Leo, edk2-devel@lists.01.org
Cc: Justen, Jordan L, Gao, Liming
Jeff, that would be a good option for determining that the processor is manufactured by AMD. It looks like you correctly found this in the "AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions, Appendix E".
Also, if more precise identification is needed, Family Model and Stepping can be obtained from "CPUID Fn0000_0001_EAX Family, Model, Stepping Identifiers" also documented there.
GARRETT KIRKENDALL
SMTS Firmware Engineer | CTE
7171 Southwest Parkway, Austin, TX 78735 USA
AMD facebook | amd.com
> -----Original Message-----
> From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> Fan, Jeff
> Sent: Thursday, June 15, 2017 3:52 AM
> To: Duran, Leo <leo.duran@amd.com>; edk2-devel@lists.01.org
> Cc: Justen, Jordan L <jordan.l.justen@intel.com>; Gao, Liming
> <liming.gao@intel.com>
> Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Leo,
>
> Could you use the CPUID Fn0000_0000_E[D,C,B]X values as below to identify
> AMD processor?
>
> Table E-1. CPUID Fn0000_0000_E[D,C,B]X values Register Value Description
> CPUID Fn0000_0000_EBX 6874_7541h The ASCII characters "h t u A".
> CPUID Fn0000_0000_ECX 444D_4163h The ASCII characters "D M A c".
> CPUID Fn0000_0000_EDX 6974_6E65h The ASCII characters "i t n e".
>
> Maybe, your guys have other better solution.
>
> Thanks!
> Jeff
> -----Original Message-----
> From: Duran, Leo [mailto:leo.duran@amd.com]
> Sent: Saturday, June 10, 2017 4:12 AM
> To: Fan, Jeff; edk2-devel@lists.01.org
> Cc: Justen, Jordan L; Gao, Liming
> Subject: RE: [PATCH v3 2/2] UefiCpuPkg: Modify
> GetProcessorLocationByApicId() to support AMD.
>
> Hi Jeff,
> Please see my replies below.
> Thanks,
> Leo.
>
> > -----Original Message-----
> > From: Fan, Jeff [mailto:jeff.fan@intel.com]
> > Sent: Thursday, June 08, 2017 12:37 AM
> > To: Fan, Jeff <jeff.fan@intel.com>; Duran, Leo <leo.duran@amd.com>;
> > edk2-devel@lists.01.org
> > Cc: Justen, Jordan L <jordan.l.justen@intel.com>; Gao, Liming
> > <liming.gao@intel.com>
> > Subject: RE: [PATCH v3 2/2] UefiCpuPkg: Modify
> > GetProcessorLocationByApicId() to support AMD.
> >
> > Leo,
> >
> > Correct some words in below mail body.
> >
> > Jeff
> >
> > -----Original Message-----
> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of
> > Fan, Jeff
> > Sent: Thursday, June 08, 2017 1:34 PM
> > To: Leo Duran; edk2-devel@lists.01.org
> > Cc: Justen, Jordan L; Gao, Liming
> > Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify
> > GetProcessorLocationByApicId() to support AMD.
> >
> > Leo,
> >
> > 1. If Intel SDM supports the ExtendedCpuIdIndex >=
> > CPUID_AMD_PROCESSOR_TOPOLOGY(0x8000001E) in the future, the following
> > code may cause unexpected result for Intel processor.
> > if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY)
> > May we use another way to check AMD or Intel processor?
> [Duran, Leo] Any specific suggestions? Thanks.
>
> >
> > 2. Goto Statements should not be used (in general) except for error
> > handling
> > (https://github.com/tianocore-
> > docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf)
>
> [Duran, Leo] OK, I will not use 'goto' in this case.
>
> >
> > Thanks!
> > Jeff
> >
> > -----Original Message-----
> > From: Leo Duran [mailto:leo.duran@amd.com]
> > Sent: Tuesday, June 06, 2017 11:59 PM
> > To: edk2-devel@lists.01.org
> > Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh
> > Subject: [PATCH v3 2/2] UefiCpuPkg: Modify
> > GetProcessorLocationByApicId() to support AMD.
> >
> > Cc: Jordan Justen <jordan.l.justen@intel.com>
> > Cc: Jeff Fan <jeff.fan@intel.com>
> > Cc: Liming Gao <liming.gao@intel.com>
> > Cc: Brijesh Singh <brijesh.singh@amd.com>
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Leo Duran <leo.duran@amd.com>
> > ---
> > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130
> > +++++++++++++++------
> > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130
> +++++++++++++++--
> > ----
> > 2 files changed, 184 insertions(+), 76 deletions(-) mode change
> > 100644 =>
> > 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> >
> > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > old mode 100644
> > new mode 100755
> > index f81bbb2..02dfabc
> > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> > @@ -4,6 +4,8 @@
> > This local APIC library instance supports xAPIC mode only.
> >
> > Copyright (c) 2010 - 2016, Intel Corporation. All rights
> > reserved.<BR>
> > + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> > +
> > This program and the accompanying materials
> > are licensed and made available under the terms and conditions of
> > the BSD License
> > which accompanies this distribution. The full text of the license
> > may be found at @@ -15,6 +17,7 @@ **/
> >
> > #include <Register/Cpuid.h>
> > +#include <Register/Amd/Cpuid.h>
> > #include <Register/Msr.h>
> > #include <Register/LocalApic.h>
> >
> > @@ -966,20 +969,29 @@ GetProcessorLocationByApicId (
> > OUT UINT32 *Thread OPTIONAL
> > )
> > {
> > - BOOLEAN TopologyLeafSupported;
> > - UINTN ThreadBits;
> > - UINTN CoreBits;
> > - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> > - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> > - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> > - UINT32 MaxCpuIdIndex;
> > - UINT32 SubIndex;
> > - UINTN LevelType;
> > - UINT32 MaxLogicProcessorsPerPackage;
> > - UINT32 MaxCoresPerPackage;
> > + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> > + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> > + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> > + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> > + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> > + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> > + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> > + UINT32 MaxStandardCpuIdIndex;
> > + UINT32 MaxExtendedCpuIdIndex;
> > + UINT32 SubIndex;
> > + UINTN LevelType;
> > + UINT32 MaxLogicProcessorsPerPackage;
> > + UINT32 MaxCoresPerPackage;
> > + UINT32 MaxThreadPerPackageMask;
> > + UINT32 ActualThreadPerPackageMask;
> > + UINT32 MaxCoresPerNode;
> > + UINT32 CorePerNodeMask;
> > + UINT32 ApicIdShift;
> > + UINTN ThreadBits;
> > + UINTN CoreBits;
> >
> > //
> > // Check if the processor is capable of supporting more than one
> > logical processor.
> > @@ -987,10 +999,10 @@ GetProcessorLocationByApicId (
> > AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> > &VersionInfoEdx.Uint32);
> > if (VersionInfoEdx.Bits.HTT == 0) {
> > if (Thread != NULL) {
> > - *Thread = 0;
> > + *Thread = 0;
> > }
> > if (Core != NULL) {
> > - *Core = 0;
> > + *Core = 0;
> > }
> > if (Package != NULL) {
> > *Package = 0;
> > @@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId (
> > CoreBits = 0;
> >
> > //
> > - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > + // Get the max index of CPUID
> > //
> > - TopologyLeafSupported = FALSE;
> > -
> > - //
> > - // Get the max index of basic CPUID
> > - //
> > - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> > NULL);
> > + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> > NULL, NULL,
> > + NULL);
> >
> > //
> > // If the extended topology enumeration leaf is available, it
> > // is the preferred mechanism for enumerating topology.
> > //
> > - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > AsmCpuidEx(
> > CPUID_EXTENDED_TOPOLOGY,
> > 0,
> > @@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId (
> > // supported on that processor.
> > //
> > if (ExtendedTopologyEbx.Uint32 != 0) {
> > - TopologyLeafSupported = TRUE;
> > -
> > //
> > // Sub-leaf index 0 (ECX= 0 as input) provides enumeration
> > parameters to extract
> > // the SMT sub-field of x2APIC ID.
> > @@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId (
> > }
> > SubIndex++;
> > } while (LevelType !=
> > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > + goto GetLocation;
> > }
> > }
> >
> > - if (!TopologyLeafSupported) {
> > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> > NULL);
> > - MaxLogicProcessorsPerPackage =
> > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> > NULL, NULL, NULL);
> > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> > + NULL); MaxLogicProcessorsPerPackage =
> > + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +
> > + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> > NULL, NULL, NULL);
> > + if (CacheParamsEax.Uint32 != 0) {
> > MaxCoresPerPackage =
> > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > + goto GetBits;
> > }
> > - else {
> > + }
> > +
> > + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> > + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> > &AmdExtendedCpuSigEcx.Uint32, NULL);
> > + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> > + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> > &AmdProcessorTopologyEbx.Uint32,
> > + &AmdProcessorTopologyEcx.Uint32, NULL);
> > +
> > + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> > + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> > +
> > //
> > - // Must be a single-core processor.
> > + // Account for actual thread count (e.g., SMT disabled)
> > //
> > - MaxCoresPerPackage = 1;
> > + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> > &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> > + MaxThreadPerPackageMask = 1 <<
> > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> > + ActualThreadPerPackageMask = 1;
> > + while (ActualThreadPerPackageMask <
> > + MaxLogicProcessorsPerPackage)
> > {
> > + ActualThreadPerPackageMask <<= 1;
> > + }
> > +
> > + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> > + MaxCoresPerNode = MaxCoresPerPackage /
> > + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> > +
> > + CorePerNodeMask = 1;
> > + while (CorePerNodeMask < MaxCoresPerNode) {
> > + CorePerNodeMask <<= 1;
> > + }
> > + CorePerNodeMask -= 1;
> > +
> > + ApicIdShift = 0;
> > + do {
> > + ApicIdShift += 1;
> > + ActualThreadPerPackageMask <<= 1;
> > + } while (ActualThreadPerPackageMask <
> > + MaxThreadPerPackageMask);
> > +
> > + //
> > + // Adjust APIC Id to report concatenation of
> Package|Core|Thread.
> > + //
> > + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >>
> > + ApicIdShift) |
> > (InitialApicId & CorePerNodeMask);
> > + }
> > +
> > + goto GetBits;
> > }
> > + }
> > +
> > + //
> > + // Must be a single-core processor.
> > + //
> > + MaxCoresPerPackage = 1;
> >
> > - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> > MaxCoresPerPackage - 1) + 1);
> > - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> > +GetBits:
> > + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> > +MaxCoresPerPackage - 1) + 1);
> > + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
> >
> > +GetLocation:
> > if (Thread != NULL) {
> > - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> > + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> > }
> > if (Core != NULL) {
> > - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > }
> > if (Package != NULL) {
> > *Package = (InitialApicId >> (ThreadBits + CoreBits)); diff --git
> > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > index e690d2a..726e1e0 100644
> > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> > @@ -5,6 +5,8 @@
> > which have xAPIC and x2APIC modes.
> >
> > Copyright (c) 2010 - 2016, Intel Corporation. All rights
> > reserved.<BR>
> > + Copyright (c) 2017, AMD Inc. All rights reserved.<BR>
> > +
> > This program and the accompanying materials
> > are licensed and made available under the terms and conditions of
> > the BSD License
> > which accompanies this distribution. The full text of the license
> > may be found at @@ -16,6 +18,7 @@ **/
> >
> > #include <Register/Cpuid.h>
> > +#include <Register/Amd/Cpuid.h>
> > #include <Register/Msr.h>
> > #include <Register/LocalApic.h>
> >
> > @@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId (
> > OUT UINT32 *Thread OPTIONAL
> > )
> > {
> > - BOOLEAN TopologyLeafSupported;
> > - UINTN ThreadBits;
> > - UINTN CoreBits;
> > - CPUID_VERSION_INFO_EBX VersionInfoEbx;
> > - CPUID_VERSION_INFO_EDX VersionInfoEdx;
> > - CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> > - UINT32 MaxCpuIdIndex;
> > - UINT32 SubIndex;
> > - UINTN LevelType;
> > - UINT32 MaxLogicProcessorsPerPackage;
> > - UINT32 MaxCoresPerPackage;
> > + CPUID_VERSION_INFO_EBX VersionInfoEbx;
> > + CPUID_VERSION_INFO_EDX VersionInfoEdx;
> > + CPUID_CACHE_PARAMS_EAX CacheParamsEax;
> > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax;
> > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx;
> > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx;
> > + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx;
> > + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx;
> > + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx;
> > + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx;
> > + UINT32 MaxStandardCpuIdIndex;
> > + UINT32 MaxExtendedCpuIdIndex;
> > + UINT32 SubIndex;
> > + UINTN LevelType;
> > + UINT32 MaxLogicProcessorsPerPackage;
> > + UINT32 MaxCoresPerPackage;
> > + UINT32 MaxThreadPerPackageMask;
> > + UINT32 ActualThreadPerPackageMask;
> > + UINT32 MaxCoresPerNode;
> > + UINT32 CorePerNodeMask;
> > + UINT32 ApicIdShift;
> > + UINTN ThreadBits;
> > + UINTN CoreBits;
> >
> > //
> > // Check if the processor is capable of supporting more than one
> > logical processor.
> > @@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId (
> > AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL,
> > &VersionInfoEdx.Uint32);
> > if (VersionInfoEdx.Bits.HTT == 0) {
> > if (Thread != NULL) {
> > - *Thread = 0;
> > + *Thread = 0;
> > }
> > if (Core != NULL) {
> > - *Core = 0;
> > + *Core = 0;
> > }
> > if (Package != NULL) {
> > *Package = 0;
> > @@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId (
> > CoreBits = 0;
> >
> > //
> > - // Assume three-level mapping of APIC ID: Package:Core:SMT.
> > + // Get the max index of CPUID
> > //
> > - TopologyLeafSupported = FALSE;
> > -
> > - //
> > - // Get the max index of basic CPUID
> > - //
> > - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);
> > + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL,
> > NULL);
> > + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex,
> > NULL, NULL,
> > + NULL);
> >
> > //
> > // If the extended topology enumeration leaf is available, it
> > // is the preferred mechanism for enumerating topology.
> > //
> > - if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > + if (MaxStandardCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {
> > AsmCpuidEx(
> > CPUID_EXTENDED_TOPOLOGY,
> > 0,
> > @@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId (
> > // supported on that processor.
> > //
> > if (ExtendedTopologyEbx.Uint32 != 0) {
> > - TopologyLeafSupported = TRUE;
> > -
> > //
> > // Sub-leaf index 0 (ECX= 0 as input) provides enumeration
> > parameters to extract
> > // the SMT sub-field of x2APIC ID.
> > @@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId (
> > }
> > SubIndex++;
> > } while (LevelType !=
> > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);
> > + goto GetLocation;
> > }
> > }
> >
> > - if (!TopologyLeafSupported) {
> > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> > NULL);
> > - MaxLogicProcessorsPerPackage =
> > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > - if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> > NULL, NULL, NULL);
> > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL,
> > + NULL); MaxLogicProcessorsPerPackage =
> > + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors;
> > +
> > + if (MaxStandardCpuIdIndex >= CPUID_CACHE_PARAMS) {
> > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32,
> > NULL, NULL, NULL);
> > + if (CacheParamsEax.Uint32 != 0) {
> > MaxCoresPerPackage =
> > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1;
> > + goto GetBits;
> > }
> > - else {
> > + }
> > +
> > + if (MaxExtendedCpuIdIndex >= CPUID_AMD_PROCESSOR_TOPOLOGY) {
> > + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL,
> > &AmdExtendedCpuSigEcx.Uint32, NULL);
> > + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions != 0) {
> > + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL,
> > &AmdProcessorTopologyEbx.Uint32,
> > + &AmdProcessorTopologyEcx.Uint32, NULL);
> > +
> > + MaxCoresPerPackage = MaxLogicProcessorsPerPackage /
> > + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1);
> > +
> > //
> > - // Must be a single-core processor.
> > + // Account for actual thread count (e.g., SMT disabled)
> > //
> > - MaxCoresPerPackage = 1;
> > + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL,
> > &AmdVirPhyAddressSizeEcx.Uint32, NULL);
> > + MaxThreadPerPackageMask = 1 <<
> > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize;
> > + ActualThreadPerPackageMask = 1;
> > + while (ActualThreadPerPackageMask <
> > + MaxLogicProcessorsPerPackage)
> > {
> > + ActualThreadPerPackageMask <<= 1;
> > + }
> > +
> > + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) {
> > + MaxCoresPerNode = MaxCoresPerPackage /
> > + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1);
> > +
> > + CorePerNodeMask = 1;
> > + while (CorePerNodeMask < MaxCoresPerNode) {
> > + CorePerNodeMask <<= 1;
> > + }
> > + CorePerNodeMask -= 1;
> > +
> > + ApicIdShift = 0;
> > + do {
> > + ApicIdShift += 1;
> > + ActualThreadPerPackageMask <<= 1;
> > + } while (ActualThreadPerPackageMask <
> > + MaxThreadPerPackageMask);
> > +
> > + //
> > + // Adjust APIC Id to report concatenation of
> Package|Core|Thread.
> > + //
> > + InitialApicId = ((InitialApicId & ~CorePerNodeMask) >>
> > + ApicIdShift) |
> > (InitialApicId & CorePerNodeMask);
> > + }
> > +
> > + goto GetBits;
> > }
> > + }
> > +
> > + //
> > + // Must be a single-core processor.
> > + //
> > + MaxCoresPerPackage = 1;
> >
> > - ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> > MaxCoresPerPackage - 1) + 1);
> > - CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); }
> > +GetBits:
> > + ThreadBits = (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage /
> > +MaxCoresPerPackage - 1) + 1);
> > + CoreBits = (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1);
> >
> > +GetLocation:
> > if (Thread != NULL) {
> > - *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> > + *Thread = InitialApicId & ((1 << ThreadBits) - 1);
> > }
> > if (Core != NULL) {
> > - *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > + *Core = (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1);
> > }
> > if (Package != NULL) {
> > *Package = (InitialApicId >> (ThreadBits + CoreBits));
> > --
> > 2.7.4
> >
> > _______________________________________________
> > edk2-devel mailing list
> > edk2-devel@lists.01.org
> > https://lists.01.org/mailman/listinfo/edk2-devel
> _______________________________________________
> edk2-devel mailing list
> edk2-devel@lists.01.org
> https://lists.01.org/mailman/listinfo/edk2-devel
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2017-06-06 15:58 [PATCH v3 0/2] UefiCpuPkg: Add CPUID support for AMD Leo Duran
2017-06-06 15:59 ` [PATCH v3 1/2] UefiCpuPkg: Add CPUID definitions " Leo Duran
2017-06-06 15:59 ` [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() to support AMD Leo Duran
2017-06-08 5:34 ` Fan, Jeff
2017-06-08 5:36 ` Fan, Jeff
2017-06-09 20:12 ` Duran, Leo
2017-06-15 8:52 ` Fan, Jeff
2017-06-15 16:28 ` Kirkendall, Garrett
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