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X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Jun 2017 20:10:54 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Jeff, Please see my replies below. Thanks, Leo. > -----Original Message----- > From: Fan, Jeff [mailto:jeff.fan@intel.com] > Sent: Thursday, June 08, 2017 12:37 AM > To: Fan, Jeff ; Duran, Leo ; > edk2-devel@lists.01.org > Cc: Justen, Jordan L ; Gao, Liming > > Subject: RE: [PATCH v3 2/2] UefiCpuPkg: Modify > GetProcessorLocationByApicId() to support AMD. >=20 > Leo, >=20 > Correct some words in below mail body. >=20 > Jeff >=20 > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of > Fan, Jeff > Sent: Thursday, June 08, 2017 1:34 PM > To: Leo Duran; edk2-devel@lists.01.org > Cc: Justen, Jordan L; Gao, Liming > Subject: Re: [edk2] [PATCH v3 2/2] UefiCpuPkg: Modify > GetProcessorLocationByApicId() to support AMD. >=20 > Leo, >=20 > 1. If Intel SDM supports the ExtendedCpuIdIndex >=3D > CPUID_AMD_PROCESSOR_TOPOLOGY(0x8000001E) in the future, the > following code may cause unexpected result for Intel processor. > if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) > May we use another way to check AMD or Intel processor? [Duran, Leo] Any specific suggestions? Thanks. >=20 > 2. Goto Statements should not be used (in general) except for error handl= ing > (https://github.com/tianocore- > docs/Docs/raw/master/Specifications/CCS_2_1_Draft.pdf) [Duran, Leo] OK, I will not use 'goto' in this case. >=20 > Thanks! > Jeff >=20 > -----Original Message----- > From: Leo Duran [mailto:leo.duran@amd.com] > Sent: Tuesday, June 06, 2017 11:59 PM > To: edk2-devel@lists.01.org > Cc: Leo Duran; Justen, Jordan L; Fan, Jeff; Gao, Liming; Brijesh Singh > Subject: [PATCH v3 2/2] UefiCpuPkg: Modify GetProcessorLocationByApicId() > to support AMD. >=20 > Cc: Jordan Justen > Cc: Jeff Fan > Cc: Liming Gao > Cc: Brijesh Singh > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Leo Duran > --- > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 > +++++++++++++++------ > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++= -- > ---- > 2 files changed, 184 insertions(+), 76 deletions(-) mode change 100644 = =3D> > 100755 UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c >=20 > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > old mode 100644 > new mode 100755 > index f81bbb2..02dfabc > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > @@ -4,6 +4,8 @@ > This local APIC library instance supports xAPIC mode only. >=20 > Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2017, AMD Inc. All rights reserved.
> + > This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be > found at @@ -15,6 +17,7 @@ **/ >=20 > #include > +#include > #include > #include >=20 > @@ -966,20 +969,29 @@ GetProcessorLocationByApicId ( > OUT UINT32 *Thread OPTIONAL > ) > { > - BOOLEAN TopologyLeafSupported; > - UINTN ThreadBits; > - UINTN CoreBits; > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > - UINT32 MaxCpuIdIndex; > - UINT32 SubIndex; > - UINTN LevelType; > - UINT32 MaxLogicProcessorsPerPackage; > - UINT32 MaxCoresPerPackage; > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; > + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; > + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; > + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; > + UINT32 MaxStandardCpuIdIndex; > + UINT32 MaxExtendedCpuIdIndex; > + UINT32 SubIndex; > + UINTN LevelType; > + UINT32 MaxLogicProcessorsPerPackage; > + UINT32 MaxCoresPerPackage; > + UINT32 MaxThreadPerPackageMask; > + UINT32 ActualThreadPerPackageMask; > + UINT32 MaxCoresPerNode; > + UINT32 CorePerNodeMask; > + UINT32 ApicIdShift; > + UINTN ThreadBits; > + UINTN CoreBits; >=20 > // > // Check if the processor is capable of supporting more than one logic= al > processor. > @@ -987,10 +999,10 @@ GetProcessorLocationByApicId ( > AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > if (Thread !=3D NULL) { > - *Thread =3D 0; > + *Thread =3D 0; > } > if (Core !=3D NULL) { > - *Core =3D 0; > + *Core =3D 0; > } > if (Package !=3D NULL) { > *Package =3D 0; > @@ -1002,20 +1014,16 @@ GetProcessorLocationByApicId ( > CoreBits =3D 0; >=20 > // > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > + // Get the max index of CPUID > // > - TopologyLeafSupported =3D FALSE; > - > - // > - // Get the max index of basic CPUID > - // > - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > NULL); > + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > NULL, NULL, > + NULL); >=20 > // > // If the extended topology enumeration leaf is available, it > // is the preferred mechanism for enumerating topology. > // > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > + if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > AsmCpuidEx( > CPUID_EXTENDED_TOPOLOGY, > 0, > @@ -1030,8 +1038,6 @@ GetProcessorLocationByApicId ( > // supported on that processor. > // > if (ExtendedTopologyEbx.Uint32 !=3D 0) { > - TopologyLeafSupported =3D TRUE; > - > // > // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration param= eters to > extract > // the SMT sub-field of x2APIC ID. > @@ -1061,31 +1067,79 @@ GetProcessorLocationByApicId ( > } > SubIndex++; > } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > + goto GetLocation; > } > } >=20 > - if (!TopologyLeafSupported) { > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > NULL); > - MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > + NULL); MaxLogicProcessorsPerPackage =3D > + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > + > + if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > + if (CacheParamsEax.Uint32 !=3D 0) { > MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > + goto GetBits; > } > - else { > + } > + > + if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { > + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, > &AmdExtendedCpuSigEcx.Uint32, NULL); > + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { > + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > &AmdProcessorTopologyEbx.Uint32, > + &AmdProcessorTopologyEcx.Uint32, NULL); > + > + MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / > + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); > + > // > - // Must be a single-core processor. > + // Account for actual thread count (e.g., SMT disabled) > // > - MaxCoresPerPackage =3D 1; > + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > &AmdVirPhyAddressSizeEcx.Uint32, NULL); > + MaxThreadPerPackageMask =3D 1 << > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; > + ActualThreadPerPackageMask =3D 1; > + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) > { > + ActualThreadPerPackageMask <<=3D 1; > + } > + > + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { > + MaxCoresPerNode =3D MaxCoresPerPackage / > + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); > + > + CorePerNodeMask =3D 1; > + while (CorePerNodeMask < MaxCoresPerNode) { > + CorePerNodeMask <<=3D 1; > + } > + CorePerNodeMask -=3D 1; > + > + ApicIdShift =3D 0; > + do { > + ApicIdShift +=3D 1; > + ActualThreadPerPackageMask <<=3D 1; > + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); > + > + // > + // Adjust APIC Id to report concatenation of Package|Core|Thread= . > + // > + InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicIdS= hift) | > (InitialApicId & CorePerNodeMask); > + } > + > + goto GetBits; > } > + } > + > + // > + // Must be a single-core processor. > + // > + MaxCoresPerPackage =3D 1; >=20 > - ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > - CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } > +GetBits: > + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > +MaxCoresPerPackage - 1) + 1); > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); >=20 > +GetLocation: > if (Thread !=3D NULL) { > - *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > } > if (Core !=3D NULL) { > - *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > } > if (Package !=3D NULL) { > *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); diff --git > a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > index e690d2a..726e1e0 100644 > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > @@ -5,6 +5,8 @@ > which have xAPIC and x2APIC modes. >=20 > Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2017, AMD Inc. All rights reserved.
> + > This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD > License > which accompanies this distribution. The full text of the license may= be > found at @@ -16,6 +18,7 @@ **/ >=20 > #include > +#include > #include > #include >=20 > @@ -1061,20 +1064,29 @@ GetProcessorLocationByApicId ( > OUT UINT32 *Thread OPTIONAL > ) > { > - BOOLEAN TopologyLeafSupported; > - UINTN ThreadBits; > - UINTN CoreBits; > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > - UINT32 MaxCpuIdIndex; > - UINT32 SubIndex; > - UINTN LevelType; > - UINT32 MaxLogicProcessorsPerPackage; > - UINT32 MaxCoresPerPackage; > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > + CPUID_AMD_EXTENDED_CPU_SIG_ECX AmdExtendedCpuSigEcx; > + CPUID_AMD_PROCESSOR_TOPOLOGY_EBX AmdProcessorTopologyEbx; > + CPUID_AMD_PROCESSOR_TOPOLOGY_ECX AmdProcessorTopologyEcx; > + CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX AmdVirPhyAddressSizeEcx; > + UINT32 MaxStandardCpuIdIndex; > + UINT32 MaxExtendedCpuIdIndex; > + UINT32 SubIndex; > + UINTN LevelType; > + UINT32 MaxLogicProcessorsPerPackage; > + UINT32 MaxCoresPerPackage; > + UINT32 MaxThreadPerPackageMask; > + UINT32 ActualThreadPerPackageMask; > + UINT32 MaxCoresPerNode; > + UINT32 CorePerNodeMask; > + UINT32 ApicIdShift; > + UINTN ThreadBits; > + UINTN CoreBits; >=20 > // > // Check if the processor is capable of supporting more than one logic= al > processor. > @@ -1082,10 +1094,10 @@ GetProcessorLocationByApicId ( > AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > if (Thread !=3D NULL) { > - *Thread =3D 0; > + *Thread =3D 0; > } > if (Core !=3D NULL) { > - *Core =3D 0; > + *Core =3D 0; > } > if (Package !=3D NULL) { > *Package =3D 0; > @@ -1097,20 +1109,16 @@ GetProcessorLocationByApicId ( > CoreBits =3D 0; >=20 > // > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > + // Get the max index of CPUID > // > - TopologyLeafSupported =3D FALSE; > - > - // > - // Get the max index of basic CPUID > - // > - AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > + AsmCpuid(CPUID_SIGNATURE, &MaxStandardCpuIdIndex, NULL, NULL, > NULL); > + AsmCpuid(CPUID_EXTENDED_FUNCTION, &MaxExtendedCpuIdIndex, > NULL, NULL, > + NULL); >=20 > // > // If the extended topology enumeration leaf is available, it > // is the preferred mechanism for enumerating topology. > // > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > + if (MaxStandardCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > AsmCpuidEx( > CPUID_EXTENDED_TOPOLOGY, > 0, > @@ -1125,8 +1133,6 @@ GetProcessorLocationByApicId ( > // supported on that processor. > // > if (ExtendedTopologyEbx.Uint32 !=3D 0) { > - TopologyLeafSupported =3D TRUE; > - > // > // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration param= eters to > extract > // the SMT sub-field of x2APIC ID. > @@ -1156,31 +1162,79 @@ GetProcessorLocationByApicId ( > } > SubIndex++; > } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > + goto GetLocation; > } > } >=20 > - if (!TopologyLeafSupported) { > - AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > NULL); > - MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > - AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > + NULL); MaxLogicProcessorsPerPackage =3D > + VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > + > + if (MaxStandardCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > + if (CacheParamsEax.Uint32 !=3D 0) { > MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > + goto GetBits; > } > - else { > + } > + > + if (MaxExtendedCpuIdIndex >=3D CPUID_AMD_PROCESSOR_TOPOLOGY) { > + AsmCpuid(CPUID_EXTENDED_CPU_SIG, NULL, NULL, > &AmdExtendedCpuSigEcx.Uint32, NULL); > + if (AmdExtendedCpuSigEcx.Bits.TopologyExtensions !=3D 0) { > + AsmCpuid(CPUID_AMD_PROCESSOR_TOPOLOGY, NULL, > &AmdProcessorTopologyEbx.Uint32, > + &AmdProcessorTopologyEcx.Uint32, NULL); > + > + MaxCoresPerPackage =3D MaxLogicProcessorsPerPackage / > + (AmdProcessorTopologyEbx.Bits.ThreadsPerCore + 1); > + > // > - // Must be a single-core processor. > + // Account for actual thread count (e.g., SMT disabled) > // > - MaxCoresPerPackage =3D 1; > + AsmCpuid(CPUID_VIR_PHY_ADDRESS_SIZE, NULL, NULL, > &AmdVirPhyAddressSizeEcx.Uint32, NULL); > + MaxThreadPerPackageMask =3D 1 << > AmdVirPhyAddressSizeEcx.Bits.ApicIdCoreIdSize; > + ActualThreadPerPackageMask =3D 1; > + while (ActualThreadPerPackageMask < MaxLogicProcessorsPerPackage) > { > + ActualThreadPerPackageMask <<=3D 1; > + } > + > + if (ActualThreadPerPackageMask < MaxThreadPerPackageMask) { > + MaxCoresPerNode =3D MaxCoresPerPackage / > + (AmdProcessorTopologyEcx.Bits.NodesPerProcessor + 1); > + > + CorePerNodeMask =3D 1; > + while (CorePerNodeMask < MaxCoresPerNode) { > + CorePerNodeMask <<=3D 1; > + } > + CorePerNodeMask -=3D 1; > + > + ApicIdShift =3D 0; > + do { > + ApicIdShift +=3D 1; > + ActualThreadPerPackageMask <<=3D 1; > + } while (ActualThreadPerPackageMask < MaxThreadPerPackageMask); > + > + // > + // Adjust APIC Id to report concatenation of Package|Core|Thread= . > + // > + InitialApicId =3D ((InitialApicId & ~CorePerNodeMask) >> ApicIdS= hift) | > (InitialApicId & CorePerNodeMask); > + } > + > + goto GetBits; > } > + } > + > + // > + // Must be a single-core processor. > + // > + MaxCoresPerPackage =3D 1; >=20 > - ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > - CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); } > +GetBits: > + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > +MaxCoresPerPackage - 1) + 1); > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); >=20 > +GetLocation: > if (Thread !=3D NULL) { > - *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > } > if (Core !=3D NULL) { > - *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); > } > if (Package !=3D NULL) { > *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); > -- > 2.7.4 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel