From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from NAM01-BN3-obe.outbound.protection.outlook.com (mail-bn3nam01on0620.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe41::620]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DBFAA81DEB for ; Fri, 28 Oct 2016 10:10:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=BvPMcX4p4oR3TlUH6t3f4+IFNrvMLpJTiOd4Rz1olek=; b=xrTQaDRZ8LhMSHo5Jev7/dgI8btLKMSdZ3i+2q0LJriEBkaaCuF56lO+soXxPAUNESgTNV0i9zYeJisPJkw8RxxHgneUxzD83uCjB8gJoIQAt66uOnb03p/KgJtWQeTGcJlfyMManLbNuB+uW9ZDj3eDBa6dCc6fxP6Rf+2wXsc= Received: from DM5PR12MB1243.namprd12.prod.outlook.com (10.168.237.22) by DM5PR12MB1243.namprd12.prod.outlook.com (10.168.237.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.1.679.12; Fri, 28 Oct 2016 17:10:17 +0000 Received: from DM5PR12MB1243.namprd12.prod.outlook.com ([10.168.237.22]) by DM5PR12MB1243.namprd12.prod.outlook.com ([10.168.237.22]) with mapi id 15.01.0679.018; Fri, 28 Oct 2016 17:10:17 +0000 From: "Duran, Leo" To: "edk2-devel@lists.01.org" CC: "liming.gao@intel.com" , "lersek@redhat.com" , "jeff.fan@intel.com" , "michael.d.kinney@intel.com" Thread-Topic: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Thread-Index: AQHSMT3gy6+judeLuk2/A6xOB3yjrKC+GaRw Date: Fri, 28 Oct 2016 17:10:17 +0000 Message-ID: References: <1477674486-18380-1-git-send-email-leo.duran@amd.com> In-Reply-To: <1477674486-18380-1-git-send-email-leo.duran@amd.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=leo.duran@amd.com; x-originating-ip: [165.204.77.1] x-ms-office365-filtering-correlation-id: 28bd2ebe-1c72-4266-4d9f-08d3ff554a6c x-microsoft-exchange-diagnostics: 1; DM5PR12MB1243; 7:sbVXOxOBOlwPOlpolqZFc0GqULucmKz4AlK5BJLu8oapRxt3Ka7A5CORmAWTINQl0vKYBtcUiD8oOdJdkntdnJbTVidWTSv2C5I7+vLByV+70sfISjFhWCxtuHVAoHZH0Ygy7m5n0G0xsrl/Jj3EqJ15GGwslo3LH2/o6ix96q6ZICLUsck2OUpskYZ8vNNBPUz0eE5oXhhHkdi0ZCCbrgkvIyX+FgrdM+HCUEQfRA9eNnvY/K1oDhic+FzRVO0fZBvzwKodboq04Pt/DJPz06WU+0UUB1Xx69JcGIDVRNxBO5O6gasglNRrQLmg1VYyDhG3zxVMwuDcwMv6ryUWigbvHY+ff8oteCUAJNvAEGI=; 20:mz577j1IIdDo1u8E41o94zB6K81cOOP5G+LW++I/uhF+1uJ6WwTM5p74UIX3Njuuo8eioGLicLFkWebJfnAbg4XgP7YS5vT/ALWDKQ7AymFxSa6PjbC6fTkgUrw/ShZB4rmw08XTXGfJekACDYTPm92HZRuSyVBICSNzP/L4szTqq0gC//IFkU280Pk8xL9ndxPNDM94DjdBsDa8R4Zk4Ec5Y3XG2rDnsX49d+jYAdBY5K8vlHXGA2Yw571XUjmM x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:;SRVR:DM5PR12MB1243; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(143289334528602)(166708455590820)(192374486261705)(767451399110)(42262312472803)(162533806227266)(63843785518722)(211171220733660)(31960201722614)(228905959029699); x-exchange-antispam-report-cfa-test: BCL:0; PCL:0; RULEID:(6040176)(601004)(2401047)(8121501046)(5005006)(10201501046)(3002001)(6055026); SRVR:DM5PR12MB1243; BCL:0; PCL:0; RULEID:; SRVR:DM5PR12MB1243; x-forefront-prvs: 0109D382B0 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(6009001)(7916002)(199003)(377454003)(13464003)(189002)(102836003)(33656002)(122556002)(586003)(19580395003)(92566002)(77096005)(1720100001)(15975445007)(4326007)(6916009)(110136003)(2950100002)(7696004)(6116002)(3846002)(2906002)(5660300001)(575784001)(86362001)(8676002)(81166006)(81156014)(74316002)(7846002)(7736002)(305945005)(97736004)(76576001)(2900100001)(19580405001)(66066001)(189998001)(9686002)(76176999)(2351001)(99286002)(106356001)(105586002)(106116001)(10400500002)(3280700002)(50986999)(68736007)(3660700001)(2501003)(11100500001)(54356999)(87936001)(101416001)(8936002)(3900700001)(5002640100001)(579004)(569005); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1243; H:DM5PR12MB1243.namprd12.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2016 17:10:17.3555 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1243 Subject: Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Oct 2016 17:10:19 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Sorry, the file mode looks wrong again.... I will fix this. Leo. > -----Original Message----- > From: Duran, Leo > Sent: Friday, October 28, 2016 12:08 PM > To: edk2-devel@lists.01.org > Cc: liming.gao@intel.com; lersek@redhat.com; jeff.fan@intel.com; > michael.d.kinney@intel.com; Duran, Leo > Subject: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib > library >=20 > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. > 2) Remove ExtractProcessorLocation() from MpInitLib library. > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. >=20 > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Leo Duran > --- > Maintainers.txt | 240 ---------------= ------ > UefiCpuPkg/Include/Library/LocalApicLib.h | 18 ++ > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++ > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++ > UefiCpuPkg/Library/MpInitLib/MpLib.c | 128 +---------- > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 121 +---------- > 6 files changed, 280 insertions(+), 487 deletions(-) delete mode 100644 > Maintainers.txt mode change 100644 =3D> 100755 > UefiCpuPkg/Include/Library/LocalApicLib.h > mode change 100644 =3D> 100755 > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > mode change 100644 =3D> 100755 > UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > mode change 100644 =3D> 100755 UefiCpuPkg/Library/MpInitLib/MpLib.c > mode change 100644 =3D> 100755 > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c >=20 > diff --git a/Maintainers.txt b/Maintainers.txt deleted file mode 100644 i= ndex > 94d3380..0000000 > --- a/Maintainers.txt > +++ /dev/null > @@ -1,240 +0,0 @@ > -EDK II Maintainers > -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > - > -This file provides information about the primary maintainers for -EDK II= . > - > -In general, you should not privately email the maintainer. You should -e= mail > the edk2-devel list, but you can also Cc the maintainer. > - > -Descriptions of section entries: > - > - L: Mailing list that is relevant to this area (default is edk2-devel) > - Patches and questions should be sent to the email list. > - M: Cc address for patches and questions (ie, the package maintainer) > - W: Web-page with status/info > - T: SCM tree type and location. Type is one of: git, svn. > - S: Status, one of the following: > - Supported: Someone is actually paid to look after this. > - Maintained: Someone actually looks after it. > - Odd Fixes: It has a maintainer but they don't have time to do > - much other than throw the odd patch in. See below. > - Orphan: No current maintainer [but maybe you could take the > - role as you write your new code]. > - Obsolete: Old code. Something tagged obsolete generally means > - it has been replaced by a better system and you > - should be using that. > - > -EDK II > ------- > -W: http://www.tianocore.org/edk2/ > -L: https://lists.sourceforge.net/lists/listinfo/edk2-devel > -T: git - https://github.com/tianocore/edk2.git > -T: git (mirror) - https://bitbucket.org/tianocore/edk2.git > -T: git (mirror) - http://git.code.sf.net/p/tianocore/edk2 > -T: svn (read-only, deprecated) - > https://svn.code.sf.net/p/edk2/code/trunk/edk2 > - > -Responsible Disclosure, Reporting Security Issues > -------------------------------------------------- > -W: https://github.com/tianocore/tianocore.github.io/wiki/Security > - > -EDK II Releases: > ----------------- > -UDK2014 > -W: http://www.tianocore.org/udk2014/ > -S: Supported > - > -EDK II Packages: > ----------------- > -AppPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/AppPkg > -M: Daryl McDaniel > -M: Jaben Carsey > - > -ArmPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/ArmPkg > -M: Leif Lindholm > -M: Ard Biesheuvel > - > -ArmPlatformPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/ArmPlatformPkg > -M: Leif Lindholm > -M: Ard Biesheuvel > - > -ArmVirtPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/ArmVirtPkg > -M: Laszlo Ersek > -M: Ard Biesheuvel > - > -BaseTools > -W: https://github.com/tianocore/tianocore.github.io/wiki/BaseTools > -M: Yonghong Zhu > -M: Liming Gao > - > -BeagleBoardPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/BeagleBoardPkg > -M: Leif Lindholm > -M: Ard Biesheuvel > - > -CorebootModulePkg, CorebootPayloadPkg > -W: > https://github.com/tianocore/tianocore.github.io/wiki/Coreboot_UEFI_payl > oad > -M: Maurice Ma > -M: Prince Agyeman > -S: Maintained > - > -CryptoPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/CryptoPkg > -M: Qin Long > -M: Ting Ye > - > -DuetPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/DuetPkg > -M: Ruiyu Ni > - > -EdkCompatibilityPkg > -W: > https://github.com/tianocore/tianocore.github.io/wiki/EdkCompatibilityPkg > -M: Liming Gao > - > -EdkShellPkg, EdkShellBinPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/EdkShellPkg > -M: Ruiyu Ni > -T: svn - https://svn.code.sf.net/p/efi-shell/code/trunk/Shell/ > -S: Obsolete (Use ShellPkg & ShellBinPkg instead) > - > -EmbeddedPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/EmbeddedPkg > -M: Leif Lindholm > -M: Ard Biesheuvel > - > -EmulatorPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/EmulatorPkg > -M: Jordan Justen > -M: Andrew Fish > -S: Maintained > - > -FatPkg, FatBinPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/Edk2-fat-driver > -M: Ruiyu Ni > -T: svn - https://svn.code.sf.net/p/edk2-fatdriver2/code/trunk/EnhancedFa= t > -T: git - https://github.com/tianocore/edk2-FatPkg.git > - > -IntelFrameworkModulePkg > -W: > https://github.com/tianocore/tianocore.github.io/wiki/IntelFrameworkMod > ulePkg > -M: Jeff Fan > - > -IntelFrameworkPkg > -W: > https://github.com/tianocore/tianocore.github.io/wiki/IntelFrameworkPkg > -M: Michael D Kinney > -M: Jeff Fan > - > -IntelFsp2Pkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2Pkg > -M: Jiewen Yao > -M: Giri P Mudusuru > - > -IntelFsp2WrapperPkg > -W: > https://github.com/tianocore/tianocore.github.io/wiki/IntelFsp2WrapperPk > g > -M: Jiewen Yao > -M: Giri P Mudusuru > - > -IntelFspPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/IntelFspPkg > -M: Jiewen Yao > - > -IntelFspWrapperPkg > -W: > https://github.com/tianocore/tianocore.github.io/wiki/IntelFspWrapperPkg > -M: Jiewen Yao > - > -IntelSiliconPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/IntelSiliconPkg > -M: Jiewen Yao > -M: Giri P Mudusuru > - > -MdeModulePkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/MdeModulePkg > -M: Feng Tian > -M: Star Zeng > - > -MdePkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/MdePkg > -M: Michael D Kinney > -M: Liming Gao > - > -NetworkPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/NetworkPkg > -M: Siyuan Fu > -M: Jiaxin Wu > - > -Nt32Pkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/Nt32Pkg > -M: Ruiyu Ni > - > -Omap35xxPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/Omap35xxPkg > -M: Leif Lindholm > -M: Ard Biesheuvel > - > -OptionRomPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/OptionRomPkg > -M: Ruiyu Ni > - > -OvmfPkg > -W: http://www.tianocore.org/ovmf/ > -M: Jordan Justen > -M: Laszlo Ersek > -S: Maintained > - > -PcAtChipsetPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/PcAtChipsetPkg > -M: Ruiyu Ni > - > -PerformancePkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/PerformancePkg > -M: Daryl McDaniel > -M: Jaben Carsey > - > -QuarkPlatformPkg, QuarkSocPkg > -M: Michael D Kinney > -M: Kelly Steele > - > -SecurityPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg > -M: Chao Zhang > - > -ShellBinPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/ShellPkg > -M: Jaben Carsey (Ia32/X64) > -M: Ruiyu Ni (Ia32/X64) > -M: Leif Lindholm (ARM/AArch64) > -M: Ard Biesheuvel (ARM/AArch64) > - > -ShellPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/ShellPkg > -M: Jaben Carsey > -M: Ruiyu Ni > - > -SourceLevelDebugPkg > -W: > https://github.com/tianocore/tianocore.github.io/wiki/SourceLevelDebugPk > g > -M: Jeff Fan > -M: Hao Wu > - > -StdLib, StdLibPrivateInternalFiles > -W: https://github.com/tianocore/tianocore.github.io/wiki/StdLib > -M: Daryl McDaniel > -M: Jaben Carsey > - > -UefiCpuPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/UefiCpuPkg > -M: Jeff Fan > - > -UnixPkg > -W: https://github.com/tianocore/tianocore.github.io/wiki/UnixPkg > -S: Obsolete (Use EmulatorPkg instead) > - > -Vlv2DeviceRefCodePkg > -M: David Wei > -M: Mang Guo > - > -Vlv2TbltDevicePkg > -M: David Wei > -M: Mang Guo > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h > b/UefiCpuPkg/Include/Library/LocalApicLib.h > old mode 100644 > new mode 100755 > index cd4e613..4abf64c > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h > @@ -21,6 +21,9 @@ > #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode. > #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode. >=20 > +#include > +#include > + > /** > Retrieve the base address of local APIC. >=20 > @@ -410,6 +413,21 @@ GetApicMsiValue ( > IN BOOLEAN LevelTriggered, > IN BOOLEAN AssertionLevel > ); > + > +/** > +Get Package ID/Core ID/Thread ID of a processor. > + > +The algorithm assumes the target system has symmetry across physical > +package boundaries with respect to the number of logical processors per > package, number of cores per package. > + > +@param InitialApicId Must be the initial APIC ID of the target logical > processor. > +@param Location Returns the processor location information. > +**/ > +VOID > +GetProcessorLocation( > + IN UINT32 InitialApicId, > + OUT EFI_CPU_PHYSICAL_LOCATION *Location ); >=20 > #endif >=20 > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > old mode 100644 > new mode 100755 > index 8d0fb02..219f99f > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > @@ -941,3 +941,133 @@ GetApicMsiValue ( > } > return MsiData.Uint64; > } > + > +/** > +Get Package ID/Core ID/Thread ID of a processor. > + > +The algorithm assumes the target system has symmetry across physical > +package boundaries with respect to the number of logical processors per > package, number of cores per package. > + > +@param InitialApicId Must be the initial APIC ID of the target logical > processor. > +@param Location Returns the processor location information. > +**/ > +VOID > +GetProcessorLocation( > +IN UINT32 InitialApicId, > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > +) > +{ > + BOOLEAN TopologyLeafSupported; > + UINTN ThreadBits; > + UINTN CoreBits; > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > + UINT32 MaxCpuIdIndex; > + UINT32 SubIndex; > + UINTN LevelType; > + UINT32 MaxLogicProcessorsPerPackage; > + UINT32 MaxCoresPerPackage; > + > + // > + // Check if the processor is capable of supporting more than one > logical processor. > + // > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > + if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > + Location->Thread =3D 0; > + Location->Core =3D 0; > + Location->Package =3D 0; > + return; > + } > + > + ThreadBits =3D 0; > + CoreBits =3D 0; > + > + // > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > + // > + > + TopologyLeafSupported =3D FALSE; > + // > + // Get the max index of basic CPUID > + // > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, > NULL); > + > + // > + // If the extended topology enumeration leaf is available, it > + // is the preferred mechanism for enumerating topology. > + // > + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + 0, > + &ExtendedTopologyEax.Uint32, > + &ExtendedTopologyEbx.Uint32, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + // > + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and > maximum input value for > + // basic CPUID information is greater than 0BH, then > CPUID.0BH leaf is not > + // supported on that processor. > + // > + if (ExtendedTopologyEbx.Uint32 !=3D 0) { > + TopologyLeafSupported =3D TRUE; > + > + // > + // Sub-leaf index 0 (ECX=3D 0 as input) provides > enumeration parameters to extract > + // the SMT sub-field of x2APIC ID. > + // > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > + ASSERT(LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > + > + // > + // Software must not assume any "level type" > encoding > + // value to be related to any sub-leaf index, except > sub-leaf 0. > + // > + SubIndex =3D 1; > + do { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + SubIndex, > + &ExtendedTopologyEax.Uint32, > + NULL, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + LevelType =3D > ExtendedTopologyEcx.Bits.LevelType; > + if (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > + CoreBits =3D > ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > + break; > + } > + SubIndex++; > + } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > + } > + } > + > + if (!TopologyLeafSupported) { > + AsmCpuid(CPUID_VERSION_INFO, NULL, > &VersionInfoEbx.Uint32, NULL, NULL); > + MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, > &CacheParamsEax.Uint32, NULL, NULL, NULL); > + MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > + } > + else { > + // > + // Must be a single-core processor. > + // > + MaxCoresPerPackage =3D 1; > + } > + > + ThreadBits =3D > (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + > 1); > + } > + > + Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > + Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1= ); > + Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); } > diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > old mode 100644 > new mode 100755 > index 4c42696..16395a3 > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > @@ -1036,3 +1036,133 @@ GetApicMsiValue ( > } > return MsiData.Uint64; > } > + > +/** > +Get Package ID/Core ID/Thread ID of a processor. > + > +The algorithm assumes the target system has symmetry across physical > +package boundaries with respect to the number of logical processors per > package, number of cores per package. > + > +@param InitialApicId Must be the initial APIC ID of the target logical > processor. > +@param Location Returns the processor location information. > +**/ > +VOID > +GetProcessorLocation( > +IN UINT32 InitialApicId, > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > +) > +{ > + BOOLEAN TopologyLeafSupported; > + UINTN ThreadBits; > + UINTN CoreBits; > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > + UINT32 MaxCpuIdIndex; > + UINT32 SubIndex; > + UINTN LevelType; > + UINT32 MaxLogicProcessorsPerPackage; > + UINT32 MaxCoresPerPackage; > + > + // > + // Check if the processor is capable of supporting more than one > logical processor. > + // > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > + if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > + Location->Thread =3D 0; > + Location->Core =3D 0; > + Location->Package =3D 0; > + return; > + } > + > + ThreadBits =3D 0; > + CoreBits =3D 0; > + > + // > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > + // > + > + TopologyLeafSupported =3D FALSE; > + // > + // Get the max index of basic CPUID > + // > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, > NULL); > + > + // > + // If the extended topology enumeration leaf is available, it > + // is the preferred mechanism for enumerating topology. > + // > + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + 0, > + &ExtendedTopologyEax.Uint32, > + &ExtendedTopologyEbx.Uint32, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + // > + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and > maximum input value for > + // basic CPUID information is greater than 0BH, then > CPUID.0BH leaf is not > + // supported on that processor. > + // > + if (ExtendedTopologyEbx.Uint32 !=3D 0) { > + TopologyLeafSupported =3D TRUE; > + > + // > + // Sub-leaf index 0 (ECX=3D 0 as input) provides > enumeration parameters to extract > + // the SMT sub-field of x2APIC ID. > + // > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > + ASSERT(LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > + > + // > + // Software must not assume any "level type" > encoding > + // value to be related to any sub-leaf index, except > sub-leaf 0. > + // > + SubIndex =3D 1; > + do { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + SubIndex, > + &ExtendedTopologyEax.Uint32, > + NULL, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + LevelType =3D > ExtendedTopologyEcx.Bits.LevelType; > + if (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > + CoreBits =3D > ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > + break; > + } > + SubIndex++; > + } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > + } > + } > + > + if (!TopologyLeafSupported) { > + AsmCpuid(CPUID_VERSION_INFO, NULL, > &VersionInfoEbx.Uint32, NULL, NULL); > + MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, > &CacheParamsEax.Uint32, NULL, NULL, NULL); > + MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > + } > + else { > + // > + // Must be a single-core processor. > + // > + MaxCoresPerPackage =3D 1; > + } > + > + ThreadBits =3D > (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + > 1); > + } > + > + Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > + Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1= ); > + Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); } > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c > b/UefiCpuPkg/Library/MpInitLib/MpLib.c > old mode 100644 > new mode 100755 > index c3fe721..f3380bb > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( } >=20 > /** > - Get CPU Package/Core/Thread location information. > - > - @param[in] InitialApicId CPU APIC ID > - @param[out] Location Pointer to CPU location information > -**/ > -VOID > -ExtractProcessorLocation ( > - IN UINT32 InitialApicId, > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > - ) > -{ > - BOOLEAN TopologyLeafSupported; > - UINTN ThreadBits; > - UINTN CoreBits; > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > - UINT32 MaxCpuIdIndex; > - UINT32 SubIndex; > - UINTN LevelType; > - UINT32 MaxLogicProcessorsPerPackage; > - UINT32 MaxCoresPerPackage; > - > - // > - // Check if the processor is capable of supporting more than one logic= al > processor. > - // > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, > &VersionInfoEdx.Uint32); > - if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > - Location->Thread =3D 0; > - Location->Core =3D 0; > - Location->Package =3D 0; > - return; > - } > - > - ThreadBits =3D 0; > - CoreBits =3D 0; > - > - // > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > - // > - > - TopologyLeafSupported =3D FALSE; > - // > - // Get the max index of basic CPUID > - // > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > - > - // > - // If the extended topology enumeration leaf is available, it > - // is the preferred mechanism for enumerating topology. > - // > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > - AsmCpuidEx ( > - CPUID_EXTENDED_TOPOLOGY, > - 0, > - &ExtendedTopologyEax.Uint32, > - &ExtendedTopologyEbx.Uint32, > - &ExtendedTopologyEcx.Uint32, > - NULL > - ); > - // > - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input > value for > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf = is not > - // supported on that processor. > - // > - if (ExtendedTopologyEbx.Uint32 !=3D 0) { > - TopologyLeafSupported =3D TRUE; > - > - // > - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration param= eters to > extract > - // the SMT sub-field of x2APIC ID. > - // > - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > - ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > - ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > - > - // > - // Software must not assume any "level type" encoding > - // value to be related to any sub-leaf index, except sub-leaf 0. > - // > - SubIndex =3D 1; > - do { > - AsmCpuidEx ( > - CPUID_EXTENDED_TOPOLOGY, > - SubIndex, > - &ExtendedTopologyEax.Uint32, > - NULL, > - &ExtendedTopologyEcx.Uint32, > - NULL > - ); > - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > - CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits= ; > - break; > - } > - SubIndex++; > - } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > - } > - } > - > - if (!TopologyLeafSupported) { > - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, > NULL); > - MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, > NULL, NULL, NULL); > - MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > - } else { > - // > - // Must be a single-core processor. > - // > - MaxCoresPerPackage =3D 1; > - } > - > - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > - } > - > - Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > - Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits)= - 1); > - Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); -} > - > -/** > Worker function for SwitchBSP(). >=20 > Worker function for SwitchBSP(), assigned to the AP which is intended = @@ > -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo ( > // > // Get processor location information > // > - ExtractProcessorLocation (CpuMpData- > >CpuData[ProcessorNumber].ApicId, &ProcessorInfoBuffer->Location); > + GetProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, > + &ProcessorInfoBuffer->Location); >=20 > if (HealthData !=3D NULL) { > HealthData->Uint32 =3D CpuMpData->CpuData[ProcessorNumber].Health; > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > old mode 100644 > new mode 100755 > index 40f2a17..67cd0a0 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL > mSmmCpuService =3D { }; >=20 > /** > - Get Package ID/Core ID/Thread ID of a processor. > - > - APIC ID must be an initial APIC ID. > - > - The algorithm below assumes the target system has symmetry across > physical package boundaries > - with respect to the number of logical processors per package, number o= f > cores per package. > - > - @param ApicId APIC ID of the target logical processor. > - @param Location Returns the processor location information. > -**/ > -VOID > -SmmGetProcessorLocation ( > - IN UINT32 ApicId, > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > - ) > -{ > - UINTN ThreadBits; > - UINTN CoreBits; > - UINT32 RegEax; > - UINT32 RegEbx; > - UINT32 RegEcx; > - UINT32 RegEdx; > - UINT32 MaxCpuIdIndex; > - UINT32 SubIndex; > - UINTN LevelType; > - UINT32 MaxLogicProcessorsPerPackage; > - UINT32 MaxCoresPerPackage; > - BOOLEAN TopologyLeafSupported; > - > - ASSERT (Location !=3D NULL); > - > - ThreadBits =3D 0; > - CoreBits =3D 0; > - TopologyLeafSupported =3D FALSE; > - > - // > - // Check if the processor is capable of supporting more than one logic= al > processor. > - // > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); > - ASSERT ((RegEdx & BIT28) !=3D 0); > - > - // > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > - // > - > - // > - // Get the max index of basic CPUID > - // > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > - > - // > - // If the extended topology enumeration leaf is available, it > - // is the preferred mechanism for enumerating topology. > - // > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, > &RegEcx, NULL); > - // > - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input > value for > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf = is not > - // supported on that processor. > - // > - if ((RegEbx & 0xffff) !=3D 0) { > - TopologyLeafSupported =3D TRUE; > - > - // > - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration param= eters to > extract > - // the SMT sub-field of x2APIC ID. > - // > - LevelType =3D (RegEcx >> 8) & 0xff; > - ASSERT (LevelType =3D=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > - if ((RegEbx & 0xffff) > 1 ) { > - ThreadBits =3D RegEax & 0x1f; > - } else { > - // > - // HT is not supported > - // > - ThreadBits =3D 0; > - } > - > - // > - // Software must not assume any "level type" encoding > - // value to be related to any sub-leaf index, except sub-leaf 0. > - // > - SubIndex =3D 1; > - do { > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, > &RegEcx, NULL); > - LevelType =3D (RegEcx >> 8) & 0xff; > - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > - CoreBits =3D (RegEax & 0x1f) - ThreadBits; > - break; > - } > - SubIndex++; > - } while (LevelType !=3D > CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > - } > - } > - > - if (!TopologyLeafSupported) { > - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); > - MaxLogicProcessorsPerPackage =3D (RegEbx >> 16) & 0xff; > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); > - MaxCoresPerPackage =3D (RegEax >> 26) + 1; > - } else { > - // > - // Must be a single-core processor. > - // > - MaxCoresPerPackage =3D 1; > - } > - > - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > - } > - > - Location->Thread =3D ApicId & ~((-1) << ThreadBits); > - Location->Core =3D (ApicId >> ThreadBits) & ~((-1) << CoreBits); > - Location->Package =3D (ApicId >> (ThreadBits+ CoreBits)); -} > - > -/** > Gets processor information on the requested processor at the instant t= his > call is made. >=20 > @param[in] This A pointer to the > EFI_SMM_CPU_SERVICE_PROTOCOL instance. > @@ -280,7 +161,7 @@ SmmAddProcessor ( > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D=3D > INVALID_APIC_ID) { > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D ProcessorId; > gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag =3D 0; > - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate- > >ProcessorInfo[Index].Location); > + GetProcessorLocation ((UINT32)ProcessorId, > + &gSmmCpuPrivate->ProcessorInfo[Index].Location); >=20 > *ProcessorNumber =3D Index; > gSmmCpuPrivate->Operation[Index] =3D SmmCpuAdd; > -- > 1.9.1