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SCL:1; SRVR:DM5PR12MB1241; H:DM5PR12MB1243.namprd12.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; MX:1; A:1; LANG:en; received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Oct 2017 16:30:27.0284 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1241 Subject: Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global variables to replace macros X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Oct 2017 16:26:53 -0000 Content-Language: en-US Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Yao, Jiewen [mailto:jiewen.yao@intel.com] > Sent: Tuesday, October 17, 2017 9:51 AM > To: Duran, Leo > Cc: edk2-devel@lists.01.org; Laszlo Ersek ; Paolo > Bonzini ; Ni, Ruiyu ; Kinney, > Michael D ; Justen, Jordan L > ; Gao, Liming > Subject: Re: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global > variables to replace macros >=20 > I think it is unnecessary. All intel CPU is using same offset. All amd CP= U is > using same offset. It can be identified easily by code. > Adding a new API now is also an incompatible change because that requires > all existing featurelib change to add a new API. We have lots of close so= urce > platform using its own featurelib. >=20 > May I know what problem we are trying to resolve by adding a new API? Yao, The idea is to have PiSmmDxeSmm invoke the API to get the 'real' SAVE_STATE= _AREA offset, which is different on Intel vs AMD. But as Paolo points out, it really comes down to dealing with 0x200 bytes o= f padding (0xFC00->0xFE00).... which an instance of SmmCpuFeaturesLib may s= olve. Anyway,=20 I'm going to look into leaving the definition of SRAM_SAVE_STATE_MAP_OFFSET= as-is (@ 0xFC00), and see I can deal with the 0x200 bytes in the library. And if that all works out, then we'll just drop this whole patch series! Thanks, Leo. >=20 > thank you! > Yao, Jiewen >=20 >=20 > > =1B$B:_=1B(B 2017=1B$BG/=1B(B10=1B$B7n=1B(B17=1B$BF|!$2<8a=1B(B10:20=1B= $B!$=1B(BDuran, Leo =1B$B =1B$BF;!'=1B(B > > > > Yao, Lazlo, et al, > > > > For the SRAM_SAVE_STATE_MAP_OFFSET: > > I propose returning the value by a function in SmmCpuFeaturesLib... Her= e's > the rationale: > > - The value is fixed per CPU architecture, so this qualifies as a CPU f= eature. > > - The logic for CPU architecture detection would be in one place > > (e.g., PiSmmCpuDxeSmm would call the library function) > > - The OVMF and Quark instances of the library could just return the cur= rent > (default) value, so no compatibility issues. > > > > if you agree with this is an acceptable solution, I will submit a revis= ed patch- > set to address just the SRAM_SAVE_STATE_MAP_OFFSET. > > (BTW, I'm re-evaluating the changes submitted for the PSD offset, with > > the goal of just using the default value and dropping those changes) > > > > Thanks, > > Leo. > > > >> -----Original Message----- > >> From: Duran, Leo > >> Sent: Wednesday, October 11, 2017 2:46 PM > >> To: edk2-devel@lists.01.org > >> Cc: Duran, Leo ; Jiewen Yao > >> ; Ruiyu Ni ; Michael D > >> Kinney ; Jordan Justen > >> ; Liming Gao > >> Subject: [PATCH v5 1/2] UefiCpuPkg/SmmCpuFeaturesLib: Use global > >> variables to replace macros > >> > >> Set global variables on Constructor function based on CPUID checks. > >> The variables replace Intel macros to allow support on AMD x86 systems= . > >> > >> Specifically, the replaced macros are: > >> 1) SRAM_SAVE_STATE_MAP_OFFSET > >> 2) TXT_SMM_PSD_OFFSET > >> > >> Cc: Jiewen Yao > >> Cc: Ruiyu Ni > >> Cc: Michael D Kinney > >> Cc: Jordan Justen > >> Cc: Liming Gao > >> Contributed-under: TianoCore Contribution Agreement 1.1 > >> Signed-off-by: Leo Duran > >> --- > >> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S | 28 ++++++---- > >> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm | 29 +++++++---- > >> .../Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm | 43 > ++++++++++++--- > >> - > >> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h | 48 > >> ++++++++++++++++++ > >> .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 59 > >> ++++++++++++++++++---- > >> .../SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf | 3 ++ > >> .../SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf | 3 ++ > >> UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c | 39 > >> ++++++++++++-- > >> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.S | 28 ++++++---- > >> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.asm | 30 +++++++---- > >> .../Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm | 47 > ++++++++++++--- > >> -- > >> 11 files changed, 282 insertions(+), 75 deletions(-) create mode > >> 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h > >> > >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S > >> index 4c0f8c8..c7b49d7 100644 > >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.S > >> @@ -1,6 +1,8 @@ > >> #-------------------------------------------------------------------- > >> ---------- > >> # > >> # Copyright (c) 2009 - 2016, Intel Corporation. All rights > >> reserved.
> >> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# > >> # This program and the accompanying materials # are licensed and > >> made available under the terms and conditions of the BSD License # > >> which accompanies this distribution. The full text of the license > >> may be found at @@ -28,6 +30,9 @@ ASM_GLOBAL > ASM_PFX(gStmSmbase) > >> ASM_GLOBAL > >> ASM_PFX(gStmXdSupported) ASM_GLOBAL ASM_PFX(FeaturePcdGet > >> (PcdCpuSmmStackGuard)) ASM_GLOBAL > ASM_PFX(gStmSmiHandlerIdtr) > >> +ASM_GLOBAL ASM_PFX(gStmPsdOffset) > >> +ASM_GLOBAL ASM_PFX(gStmGdtSize) > >> +ASM_GLOBAL ASM_PFX(gStmGdtPtr) > >> > >> .equ MSR_IA32_MISC_ENABLE, 0x1A0 > >> .equ MSR_EFER, 0xc0000080 > >> @@ -36,12 +41,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # > # > >> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR # > >> -.equ DSC_OFFSET, 0xfb00 > >> -.equ DSC_GDTPTR, 0x48 > >> -.equ DSC_GDTSIZ, 0x50 > >> -.equ DSC_CS, 0x14 > >> -.equ DSC_DS, 0x16 > >> -.equ DSC_SS, 0x18 > >> +# .equ DSC_OFFSET, 0xfb00 > >> +# .equ DSC_GDTPTR, 0x48 > >> +# .equ DSC_GDTSIZ, 0x50 > >> +# > >> +.equ DSC_CS, 0x14 > >> +.equ DSC_DS, 0x16 > >> +.equ DSC_SS, 0x18 > >> .equ DSC_OTHERSEG, 0x1A > >> > >> .equ PROTECT_MODE_CS, 0x08 > >> @@ -55,11 +61,11 @@ _StmSmiEntryPoint: > >> .byte 0xbb # mov bx, imm16 > >> .word _StmGdtDesc - _StmSmiEntryPoint + 0x8000 > >> .byte 0x2e,0xa1 # mov ax, cs:[offset16] > >> - .word DSC_OFFSET + DSC_GDTSIZ > >> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + > DSC_GDTSIZ > >> decl %eax > >> movl %eax, %cs:(%edi) # mov cs:[bx], ax > >> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16] > >> - .word DSC_OFFSET + DSC_GDTPTR > >> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + > DSC_GDTPTR > >> movw %ax, %cs:2(%edi) > >> movw %ax, %bp # ebp =3D GDT base > >> .byte 0x66 > >> @@ -167,7 +173,11 @@ XdDone: > >> movl %cr0, %ebx > >> orl $0x080010023, %ebx # enable paging + WP + NE += MP + PE > >> movl %ebx, %cr0 > >> - leal DSC_OFFSET(%edi),%ebx > >> + > >> + movl $ASM_PFX(gStmPsdOffset), %ebx # leal DSC_OFFSET(%edi)= , > >> %ebx > >> + movzxw (%ebx), %esi > >> + leal (%edi, %esi), %ebx > >> + > >> movw DSC_DS(%ebx),%ax > >> movl %eax, %ds > >> movw DSC_OTHERSEG(%ebx),%ax > >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm > >> index 91dc1eb..4dbe276 100644 > >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.asm > >> @@ -1,5 +1,7 @@ > >> ;-------------------------------------------------------------------- > >> ---------- ; ; Copyright (c) 2009 - 2017, Intel Corporation. All > >> rights reserved.
> >> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.
; > >> ; This program and the accompanying materials ; are licensed and > >> made available under the terms and conditions of the BSD License ; > >> which accompanies this distribution. The full text of the license may= be > found at > >> @@ -29,13 +31,14 @@ MSR_EFER_XD EQU 0800h > >> ; > >> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ; > >> -DSC_OFFSET EQU 0fb00h > >> -DSC_GDTPTR EQU 48h > >> -DSC_GDTSIZ EQU 50h > >> -DSC_CS EQU 14h > >> -DSC_DS EQU 16h > >> -DSC_SS EQU 18h > >> -DSC_OTHERSEG EQU 1Ah > >> +; DSC_OFFSET EQU 0fb00h > >> +; DSC_GDTPTR EQU 48h > >> +; DSC_GDTSIZ EQU 50h > >> +; > >> +DSC_CS EQU 14h > >> +DSC_DS EQU 16h > >> +DSC_SS EQU 18h > >> +DSC_OTHERSEG EQU 1Ah > >> > >> PROTECT_MODE_CS EQU 08h > >> PROTECT_MODE_DS EQU 20h > >> @@ -54,6 +57,9 @@ EXTERNDEF gStmSmbase:DWORD > >> EXTERNDEF gStmXdSupported:BYTE > >> EXTERNDEF FeaturePcdGet (PcdCpuSmmStackGuard):BYTE > >> EXTERNDEF gStmSmiHandlerIdtr:FWORD > >> +EXTERNDEF gStmPsdOffset:WORD > >> +EXTERNDEF gStmGdtSize:WORD > >> +EXTERNDEF gStmGdtPtr:WORD > >> > >> .code > >> > >> @@ -63,11 +69,11 @@ _StmSmiEntryPoint: > >> DB 0bbh ; mov bx, imm16 > >> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h > >> DB 2eh, 0a1h ; mov ax, cs:[offset16] > >> - DW DSC_OFFSET + DSC_GDTSIZ > >> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ > >> dec eax > >> mov cs:[edi], eax ; mov cs:[bx], ax > >> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16] > >> - DW DSC_OFFSET + DSC_GDTPTR > >> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR > >> mov cs:[edi + 2], ax ; mov cs:[bx + 2], eax > >> mov bp, ax ; ebp =3D GDT base > >> DB 66h > >> @@ -174,7 +180,10 @@ gStmXdSupported DB 1 > >> mov ebx, cr0 > >> or ebx, 080010023h ; enable paging + WP + NE + MP= + PE > >> mov cr0, ebx > >> - lea ebx, [edi + DSC_OFFSET] > >> + > >> + movzx esi, word ptr [gStmPsdOffset] ; lea ebx, [edi + DSC= _OFFSET] > >> + lea ebx, [edi + esi] ; > >> + > >> mov ax, [ebx + DSC_DS] > >> mov ds, eax > >> mov ax, [ebx + DSC_OTHERSEG] > >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm > >> index 00c0f067..023923a 100644 > >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm > >> @@ -1,5 +1,7 @@ > >> ;-------------------------------------------------------------------- > >> ---------- ; ; Copyright (c) 2016 - 2017, Intel Corporation. All > >> rights reserved.
> >> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.
; > >> ; This program and the accompanying materials ; are licensed and > >> made available under the terms and conditions of the BSD License ; > >> which accompanies this distribution. The full text of the license > >> may be found at @@ -25,17 +27,18 @@ ; ; Constants relating to > >> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 - > %define > >> DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS > >> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define > DSC_OTHERSEG > >> 0x1a > >> +; %define DSC_OFFSET 0xfb00 > >> +; %define DSC_GDTPTR 0x48 > >> +; %define DSC_GDTSIZ 0x50 > >> +; > >> +%define DSC_CS 0x14 > >> +%define DSC_DS 0x16 > >> +%define DSC_SS 0x18 > >> +%define DSC_OTHERSEG 0x1a > >> > >> %define PROTECT_MODE_CS 0x8 > >> %define PROTECT_MODE_DS 0x20 > >> -%define TSS_SEGMENT 0x40 > >> +%define TSS_SEGMENT 0x40 > >> > >> extern ASM_PFX(SmiRendezvous) > >> extern ASM_PFX(FeaturePcdGet (PcdCpuSmmStackGuard)) @@ -51,6 > >> +54,10 @@ global ASM_PFX(gStmSmbase) global > >> ASM_PFX(gStmXdSupported) extern ASM_PFX(gStmSmiHandlerIdtr) > >> > >> +extern ASM_PFX(gStmPsdOffset) > >> +global ASM_PFX(gStmGdtSize) > >> +global ASM_PFX(gStmGdtPtr) > >> + > >> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4 > >> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4 > >> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4 > >> @@ -62,10 +69,18 @@ BITS 16 > >> ASM_PFX(gcStmSmiHandlerTemplate): > >> _StmSmiEntryPoint: > >> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000 > >> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ] > >> + > >> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSE= T + > >> DSC_GDTSIZ] > >> + mov si, [cs:eax] ; > >> + mov ax, [cs:si] ; > >> + > >> dec ax > >> mov [cs:bx], ax > >> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR] > >> + > >> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFS= ET + > >> DSC_GDTPTR] > >> + mov si, [cs:eax] ; > >> + mov eax, [cs:si] ; > >> + > >> mov [cs:bx + 2], eax > >> mov ebp, eax ; ebp =3D GDT base > >> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx] > >> @@ -166,7 +181,10 @@ StmXdSupportedPatch: > >> mov ebx, cr0 > >> or ebx, 0x80010023 ; enable paging + WP + NE + MP= + PE > >> mov cr0, ebx > >> - lea ebx, [edi + DSC_OFFSET] > >> + > >> + movzx esi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [edi + > >> DSC_OFFSET] > >> + lea ebx, [edi + esi] ; > >> + > >> mov ax, [ebx + DSC_DS] > >> mov ds, eax > >> mov ax, [ebx + DSC_OTHERSEG] > >> @@ -271,5 +289,8 @@ _StmSmiHandler: > >> ; STM init finish > >> jmp CommonHandler > >> > >> +ASM_PFX(gStmGdtSize) : RESW 1 > >> +ASM_PFX(gStmGdtPtr) : RESW 1 > >> + > >> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint > >> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - > >> _StmSmiEntryPoint > >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h > >> new file mode 100644 > >> index 0000000..78b3a5b > >> --- /dev/null > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCommon.h > >> @@ -0,0 +1,48 @@ > >> +/** @file > >> + Common declarations > >> + > >> + Copyright (c) 2017, AMD Incorporated. All rights reserved.
> >> + > >> + This program and the accompanying materials are licensed and made > >> + available under the terms and conditions of the BSD License which > >> + accompanies this distribution. The full text of the license may be > >> + found at http://opensource.org/licenses/bsd-license.php. > >> + > >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > >> BASIS, > >> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > >> EXPRESS OR IMPLIED. > >> + > >> +**/ > >> + > >> +#ifndef _SMM_COMMON_H_ > >> +#define _SMM_COMMON_H_ > >> + > >> +#include > >> + > >> +// > >> +// Definitions for AMD systems are based on contents of the // AMD64 > >> +Architecture Programmer's Manual // Volume 2: System Programming, > >> +Section 10 System-Management Mode // #define > >> +AMD_SMRAM_SAVE_STATE_MAP_OFFSET 0xfe00 > >> +#define AMD_SMM_PSD_OFFSET 0xfc00 > >> + > >> +// > >> +// External global variables for SMRAM offsets // extern UINT16 > >> +gSmramStateMapOffset; extern UINT16 gSmmPsdOffset; > >> + > >> + > >> +/** > >> + Determine if the standard CPU signature is "AuthenticAMD". > >> + > >> + @retval TRUE The CPU signature matches. > >> + @retval FALSE The CPU signature does not match. > >> + > >> +**/ > >> +BOOLEAN > >> +SmmStandardSignatureIsAuthenticAMD ( > >> + VOID > >> + ); > >> + > >> +#endif > >> diff --git > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > >> index 2d2bc6d..1c12095 100644 > >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > >> @@ -1,14 +1,16 @@ > >> /** @file > >> -The CPU specific programming for PiSmmCpuDxeSmm module. > >> + The CPU specific programming for PiSmmCpuDxeSmm module. > >> > >> -Copyright (c) 2010 - 2016, Intel Corporation. All rights > >> reserved.
-This program and the accompanying materials -are > >> licensed and made available under the terms and conditions of the BSD > >> License -which accompanies this distribution. The full text of the > >> license may be found at - > >> http://opensource.org/licenses/bsd-license.php > >> + Copyright (c) 2010 - 2016, Intel Corporation. All rights > >> + reserved.
Copyright (c) 2017, AMD Incorporated. All rights > >> + reserved.
> >> > >> -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > >> BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, > EITHER > >> EXPRESS OR IMPLIED. > >> + This program and the accompanying materials are licensed and made > >> + available under the terms and conditions of the BSD License which > >> + accompanies this distribution. The full text of the license may be > >> + found at http://opensource.org/licenses/bsd-license.php > >> + > >> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" > >> BASIS, > >> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER > >> EXPRESS OR IMPLIED. > >> > >> **/ > >> > >> @@ -22,6 +24,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF > ANY KIND, > >> EITHER EXPRESS OR IMPLIED. > >> #include > >> #include > >> > >> +#include "SmmCommon.h" > >> + > >> // > >> // Machine Specific Registers (MSRs) > >> // > >> @@ -41,6 +45,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF > ANY KIND, > >> EITHER EXPRESS OR IMPLIED. > >> #define SMM_FEATURES_LIB_IA32_MCA_CAP 0x17D > >> #define SMM_CODE_ACCESS_CHK_BIT BIT58 > >> > >> + > >> /** > >> Internal worker function that is called to complete CPU initializati= on at > the > >> end of SmmCpuFeaturesInitializeProcessor(). > >> @@ -77,6 +82,13 @@ BOOLEAN mNeedConfigureMtrrs =3D TRUE; // > BOOLEAN > >> *mSmrrEnabled; > >> > >> +// > >> +// Set default value for SMRAM offset // from > >> + // > >> +UINT16 gSmramStateMapOffset =3D > SMRAM_SAVE_STATE_MAP_OFFSET; > >> + > >> + > >> /** > >> The constructor function > >> > >> @@ -99,6 +111,13 @@ SmmCpuFeaturesLibConstructor ( > >> UINTN ModelId; > >> > >> // > >> + // Override SMRAM offset for AMD > >> + // > >> + if (SmmStandardSignatureIsAuthenticAMD ()) { > >> + gSmramStateMapOffset =3D > AMD_SMRAM_SAVE_STATE_MAP_OFFSET; } > >> + > >> + // > >> // Retrieve CPU Family and Model > >> // > >> AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, &RegEdx); > @@ - > >> 224,7 +243,7 @@ SmmCpuFeaturesInitializeProcessor ( > >> // > >> // Configure SMBASE. > >> // > >> - CpuState =3D (SMRAM_SAVE_STATE_MAP > >> *)(UINTN)(SMM_DEFAULT_SMBASE + > >> SMRAM_SAVE_STATE_MAP_OFFSET); > >> + CpuState =3D (SMRAM_SAVE_STATE_MAP > >> *)(UINTN)(SMM_DEFAULT_SMBASE + > >> + gSmramStateMapOffset); > >> CpuState->x86.SMBASE =3D (UINT32)CpuHotPlugData- > >SmBase[CpuIndex]; > >> > >> // > >> @@ -630,3 +649,25 @@ SmmCpuFeaturesAllocatePageTableMemory ( > >> return NULL; > >> } > >> > >> + > >> +/** > >> + Determine if the standard CPU signature is "AuthenticAMD". > >> + > >> + @retval TRUE The CPU signature matches. > >> + @retval FALSE The CPU signature does not match. > >> + > >> +**/ > >> +BOOLEAN > >> +SmmStandardSignatureIsAuthenticAMD ( > >> + VOID > >> + ) > >> +{ > >> + UINT32 RegEbx; > >> + UINT32 RegEcx; > >> + UINT32 RegEdx; > >> + > >> + AsmCpuid (CPUID_SIGNATURE, NULL, &RegEbx, &RegEcx, &RegEdx); > >> + return (RegEbx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EBX && > >> + RegEcx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_ECX && > >> + RegEdx =3D=3D CPUID_SIGNATURE_AUTHENTIC_AMD_EDX); > >> +} > >> diff --git > >> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf > >> index 77908b0..6a39d4b 100644 > >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf > >> @@ -2,6 +2,8 @@ > >> # The CPU specific programming for PiSmmCpuDxeSmm module. > >> # > >> # Copyright (c) 2009 - 2016, Intel Corporation. All rights > >> reserved.
> >> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# > >> # This program and the accompanying materials # are licensed and > >> made available under the terms and conditions of the BSD License # > >> which accompanies this distribution. The full text of the license > >> may be found at @@ -24,6 +26,7 @@ > >> > >> [Sources] > >> SmmCpuFeaturesLib.c > >> + SmmCommon.h > >> SmmCpuFeaturesLibNoStm.c > >> > >> [Packages] > >> diff --git > >> a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf > >> index db8dcdc..a76bed6 100644 > >> --- > a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf > >> +++ > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf > >> @@ -3,6 +3,8 @@ > >> # is included. > >> # > >> # Copyright (c) 2009 - 2016, Intel Corporation. All rights > >> reserved.
> >> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# > >> # This program and the accompanying materials # are licensed and > >> made available under the terms and conditions of the BSD License # > >> which accompanies this distribution. The full text of the license > >> may be found at @@ -25,6 +27,7 @@ > >> > >> [Sources] > >> SmmCpuFeaturesLib.c > >> + SmmCommon.h > >> SmmStm.c > >> SmmStm.h > >> > >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c > >> index 45015b8..5f7c3db 100644 > >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c > >> @@ -2,6 +2,8 @@ > >> SMM STM support functions > >> > >> Copyright (c) 2015 - 2017, Intel Corporation. All rights > >> reserved.
> >> + Copyright (c) 2017, AMD Incorporated. All rights reserved.
> >> + > >> This program and the accompanying materials > >> are licensed and made available under the terms and conditions of > >> the BSD License > >> which accompanies this distribution. The full text of the license > >> may be found at @@ -28,6 +30,8 @@ #include > >> > >> #include "SmmStm.h" > >> +#include "SmmCommon.h" > >> + > >> > >> #define TXT_EVTYPE_BASE 0x400 > >> #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14) > >> @@ -97,6 +101,20 @@ extern volatile UINT8 > gcStmSmiHandlerTemplate[]; > >> extern CONST UINT16 gcStmSmiHandlerSize; > >> extern UINT16 gcStmSmiHandlerOffset; > >> extern BOOLEAN gStmXdSupported; > >> +extern UINT16 gStmGdtSize; > >> +extern UINT16 gStmGdtPtr; > >> + > >> +// > >> +// Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR // > >> +#define TXT_PSD_GDTPTR 0x48 > >> +#define TXT_PSD_GDTSIZE 0x50 > >> + > >> +// > >> +// Set default value for PSD offset in SMRAM // from > >> + // > >> +UINT16 gStmPsdOffset =3D TXT_SMM_PSD_OFFSET; > >> > >> // > >> // Variables used by SMI Handler > >> @@ -145,6 +163,19 @@ SmmCpuFeaturesLibStmConstructor ( > >> ASSERT_EFI_ERROR (Status); > >> > >> // > >> + // Override PSD offset for AMD > >> + // > >> + if (SmmStandardSignatureIsAuthenticAMD ()) { > >> + gStmPsdOffset =3D AMD_SMM_PSD_OFFSET; } > >> + > >> + // > >> + // Initialize STM global variables associated with SMI Handler // > >> + gStmGdtSize =3D gStmPsdOffset + TXT_PSD_GDTSIZE; gStmGdtPtr =3D > >> + gStmPsdOffset + TXT_PSD_GDTPTR; > >> + > >> + // > >> // Lookup the MP Services Protocol > >> // > >> Status =3D gBS->LocateProtocol ( > >> @@ -276,8 +307,8 @@ SmmCpuFeaturesInstallSmiHandler ( > >> UINT32 RegEdx; > >> EFI_PROCESSOR_INFORMATION ProcessorInfo; > >> > >> - CopyMem ((VOID *)((UINTN)SmBase + TXT_SMM_PSD_OFFSET), > &gcStmPsd, > >> sizeof (gcStmPsd)); > >> - Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID > *)((UINTN)SmBase + > >> TXT_SMM_PSD_OFFSET); > >> + CopyMem ((VOID *)((UINTN)SmBase + gStmPsdOffset), &gcStmPsd, > >> sizeof > >> + (gcStmPsd)); Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR *)(VOID > >> + *)((UINTN)SmBase + gStmPsdOffset); > >> Psd->SmmGdtPtr =3D GdtBase; > >> Psd->SmmGdtSize =3D (UINT32)GdtSize; > >> > >> @@ -416,7 +447,7 @@ SmmEndOfDxeEventNotify ( > >> } > >> > >> for (Index =3D 0; Index < gSmst->NumberOfCpus; Index++) { > >> - Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst- > >>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + > >> TXT_SMM_PSD_OFFSET); > >> + Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR > >> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset + > >> + gStmPsdOffset); > >> DEBUG ((DEBUG_INFO, "Index=3D%d Psd=3D%p Rsdp=3D%p\n", Index, Ps= d, > >> Rsdp)); > >> Psd->AcpiRsdp =3D (UINT64)(UINTN)Rsdp; > >> } > >> @@ -1266,7 +1297,7 @@ NotifyStmResourceChange ( > >> TXT_PROCESSOR_SMM_DESCRIPTOR *Psd; > >> > >> for (Index =3D 0; Index < gSmst->NumberOfCpus; Index++) { > >> - Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR *)((UINTN)gSmst- > >>> CpuSaveState[Index] - SMRAM_SAVE_STATE_MAP_OFFSET + > >> TXT_SMM_PSD_OFFSET); > >> + Psd =3D (TXT_PROCESSOR_SMM_DESCRIPTOR > >> + *)((UINTN)gSmst->CpuSaveState[Index] - gSmramStateMapOffset + > >> + gStmPsdOffset); > >> Psd->BiosHwResourceRequirementsPtr =3D > (UINT64)(UINTN)StmResource; > >> } > >> return ; > >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S > >> index 1f9f91c..5f3386a 100644 > >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.S > >> @@ -1,6 +1,8 @@ > >> #-------------------------------------------------------------------- > >> ---------- > >> # > >> # Copyright (c) 2009 - 2016, Intel Corporation. All rights > >> reserved.
> >> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# > >> # This program and the accompanying materials # are licensed and > >> made available under the terms and conditions of the BSD License # > >> which accompanies this distribution. The full text of the license > >> may be found at @@ -27,6 +29,9 @@ ASM_GLOBAL > ASM_PFX(gStmSmiStack) > >> ASM_GLOBAL > >> ASM_PFX(gStmSmbase) ASM_GLOBAL ASM_PFX(gStmXdSupported) > ASM_GLOBAL > >> ASM_PFX(gStmSmiHandlerIdtr) > >> +ASM_GLOBAL ASM_PFX(gStmPsdOffset) > >> +ASM_GLOBAL ASM_PFX(gStmGdtSize) > >> +ASM_GLOBAL ASM_PFX(gStmGdtPtr) > >> > >> .equ MSR_IA32_MISC_ENABLE, 0x1A0 > >> .equ MSR_EFER, 0xc0000080 > >> @@ -35,12 +40,13 @@ ASM_GLOBAL ASM_PFX(gStmSmiHandlerIdtr) # > # > >> Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR # > >> -.equ DSC_OFFSET, 0xfb00 > >> -.equ DSC_GDTPTR, 0x48 > >> -.equ DSC_GDTSIZ, 0x50 > >> -.equ DSC_CS, 0x14 > >> -.equ DSC_DS, 0x16 > >> -.equ DSC_SS, 0x18 > >> +# .equ DSC_OFFSET, 0xfb00 > >> +# .equ DSC_GDTPTR, 0x48 > >> +# .equ DSC_GDTSIZ, 0x50 > >> +# > >> +.equ DSC_CS, 0x14 > >> +.equ DSC_DS, 0x16 > >> +.equ DSC_SS, 0x18 > >> .equ DSC_OTHERSEG, 0x1a > >> # > >> # Constants relating to CPU State Save Area @@ -71,12 +77,12 @@ > >> _StmSmiEntryPoint: > >> # fix GDT descriptor > >> # > >> .byte 0x2e,0xa1 # mov ax, cs:[offset16] > >> - .word DSC_OFFSET + DSC_GDTSIZ > >> +ASM_PFX(gStmGdtSize): .space 2 # .word DSC_OFFSET + > DSC_GDTSIZ > >> .byte 0x48 # dec ax > >> .byte 0x2e > >> movl %eax, (%rdi) # mov cs:[bx], ax > >> .byte 0x66,0x2e,0xa1 # mov eax, cs:[offset16] > >> - .word DSC_OFFSET + DSC_GDTPTR > >> +ASM_PFX(gStmGdtPtr): .space 2 # .word DSC_OFFSET + > DSC_GDTPTR > >> .byte 0x2e > >> movw %ax, 2(%rdi) > >> .byte 0x66,0x2e > >> @@ -183,7 +189,11 @@ Base: > >> LongMode: # long mode (64-bit code) star= ts here > >> movabsq $ASM_PFX(gStmSmiHandlerIdtr), %rax > >> lidt (%rax) > >> - lea (DSC_OFFSET)(%rdi), %ebx > >> + > >> + movl $ASM_PFX(gStmPsdOffset), %ebx # lea (DSC_OFFSET)(%rd= i), > >> %ebx > >> + movzxw (%ebx), %rsi > >> + leal (%rdi, %rsi), %ebx > >> + > >> movw DSC_DS(%rbx), %ax > >> movl %eax,%ds > >> movw DSC_OTHERSEG(%rbx), %ax > >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm > >> index ad51e07..10913df 100644 > >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.asm > >> @@ -1,5 +1,7 @@ > >> ;-------------------------------------------------------------------- > >> ---------- ; ; Copyright (c) 2009 - 2016, Intel Corporation. All > >> rights reserved.
> >> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.
; > >> ; This program and the accompanying materials ; are licensed and > >> made available under the terms and conditions of the BSD License ; > >> which accompanies this distribution. The full text of the license may= be > found at > >> @@ -32,6 +34,10 @@ EXTERNDEF gStmSmiStack:DWORD > >> EXTERNDEF gStmSmbase:DWORD > >> EXTERNDEF gStmXdSupported:BYTE > >> EXTERNDEF gStmSmiHandlerIdtr:FWORD > >> +EXTERNDEF gStmPsdOffset:WORD > >> +EXTERNDEF gStmGdtSize:WORD > >> +EXTERNDEF gStmGdtPtr:WORD > >> + > >> > >> MSR_IA32_MISC_ENABLE EQU 1A0h > >> MSR_EFER EQU 0c0000080h > >> @@ -40,13 +46,14 @@ MSR_EFER_XD EQU 0800h > >> ; > >> ; Constants relating to TXT_PROCESSOR_SMM_DESCRIPTOR ; > >> -DSC_OFFSET EQU 0fb00h > >> -DSC_GDTPTR EQU 48h > >> -DSC_GDTSIZ EQU 50h > >> -DSC_CS EQU 14h > >> -DSC_DS EQU 16h > >> -DSC_SS EQU 18h > >> -DSC_OTHERSEG EQU 1ah > >> +; DSC_OFFSET EQU 0fb00h > >> +; DSC_GDTPTR EQU 48h > >> +; DSC_GDTSIZ EQU 50h > >> +; > >> +DSC_CS EQU 14h > >> +DSC_DS EQU 16h > >> +DSC_SS EQU 18h > >> +DSC_OTHERSEG EQU 1ah > >> ; > >> ; Constants relating to CPU State Save Area ; @@ -74,12 +81,12 @@ > >> _StmSmiEntryPoint: > >> DW offset _StmGdtDesc - _StmSmiEntryPoint + 8000h ; bx =3D G= dtDesc > >> offset > >> ; fix GDT descriptor > >> DB 2eh, 0a1h ; mov ax, cs:[offset16] > >> - DW DSC_OFFSET + DSC_GDTSIZ > >> +gStmGdtSize DW ? ; DSC_OFFSET + DSC_GDTSIZ > >> DB 48h ; dec ax > >> DB 2eh > >> mov [rdi], eax ; mov cs:[bx], ax > >> DB 66h, 2eh, 0a1h ; mov eax, cs:[offset16] > >> - DW DSC_OFFSET + DSC_GDTPTR > >> +gStmGdtPtr DW ? ; DSC_OFFSET + DSC_GDTPTR > >> DB 2eh > >> mov [rdi + 2], ax ; mov cs:[bx + 2], eax > >> DB 66h, 2eh > >> @@ -178,7 +185,10 @@ Base: > >> @LongMode: ; long mode (64-bit code) star= ts here > >> mov rax, offset gStmSmiHandlerIdtr > >> lidt fword ptr [rax] > >> - lea ebx, [rdi + DSC_OFFSET] > >> + > >> + movzx rsi, word ptr [gStmPsdOffset] ; lea ebx, [rdi + DSC= _OFFSET] > >> + lea ebx, [rdi + rsi] ; > >> + > >> mov ax, [rbx + DSC_DS] > >> mov ds, eax > >> mov ax, [rbx + DSC_OTHERSEG] > >> diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm > >> b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm > >> index bcac643..df4c5a2 100644 > >> --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm > >> +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm > >> @@ -1,5 +1,7 @@ > >> ;-------------------------------------------------------------------- > >> ---------- ; ; Copyright (c) 2016 - 2017, Intel Corporation. All > >> rights reserved.
> >> +; Copyright (c) 2017, AMD Incorporated. All rights reserved.
; > >> ; This program and the accompanying materials ; are licensed and > >> made available under the terms and conditions of the BSD License ; > >> which accompanies this distribution. The full text of the license > >> may be found at @@ -29,13 +31,14 @@ ; ; Constants relating to > >> TXT_PROCESSOR_SMM_DESCRIPTOR ; -%define DSC_OFFSET 0xfb00 - > %define > >> DSC_GDTPTR 0x48 -%define DSC_GDTSIZ 0x50 -%define DSC_CS > >> 0x14 -%define DSC_DS 0x16 -%define DSC_SS 0x18 -%define > DSC_OTHERSEG > >> 0x1a > >> +; %define DSC_OFFSET 0xfb00 > >> +; %define DSC_GDTPTR 0x48 > >> +; %define DSC_GDTSIZ 0x50 > >> +; > >> +%define DSC_CS 0x14 > >> +%define DSC_DS 0x16 > >> +%define DSC_SS 0x18 > >> +%define DSC_OTHERSEG 0x1a > >> ; > >> ; Constants relating to CPU State Save Area ; @@ -44,9 +47,9 @@ > >> > >> %define PROTECT_MODE_CS 0x8 > >> %define PROTECT_MODE_DS 0x20 > >> -%define LONG_MODE_CS 0x38 > >> -%define TSS_SEGMENT 0x40 > >> -%define GDT_SIZE 0x50 > >> +%define LONG_MODE_CS 0x38 > >> +%define TSS_SEGMENT 0x40 > >> +%define GDT_SIZE 0x50 > >> > >> extern ASM_PFX(SmiRendezvous) > >> extern ASM_PFX(gStmSmiHandlerIdtr) > >> @@ -61,6 +64,10 @@ global ASM_PFX(gcStmSmiHandlerTemplate) global > >> ASM_PFX(gcStmSmiHandlerSize) global > ASM_PFX(gcStmSmiHandlerOffset) > >> > >> +extern ASM_PFX(gStmPsdOffset) > >> +global ASM_PFX(gStmGdtSize) > >> +global ASM_PFX(gStmGdtPtr) > >> + > >> ASM_PFX(gStmSmbase) EQU StmSmbasePatch - 4 > >> ASM_PFX(gStmSmiStack) EQU StmSmiStackPatch - 4 > >> ASM_PFX(gStmSmiCr3) EQU StmSmiCr3Patch - 4 > >> @@ -73,10 +80,18 @@ BITS 16 > >> ASM_PFX(gcStmSmiHandlerTemplate): > >> _StmSmiEntryPoint: > >> mov bx, _StmGdtDesc - _StmSmiEntryPoint + 0x8000 > >> - mov ax,[cs:DSC_OFFSET + DSC_GDTSIZ] > >> + > >> + mov eax, ASM_PFX(gStmGdtSize) ; mov ax, [cs:DSC_OFFSE= T + > >> DSC_GDTSIZ] > >> + mov si, [cs:eax] ; > >> + mov ax, [cs:si] ; > >> + > >> dec ax > >> mov [cs:bx], ax > >> - mov eax, [cs:DSC_OFFSET + DSC_GDTPTR] > >> + > >> + mov eax, ASM_PFX(gStmGdtPtr) ; mov eax, [cs:DSC_OFFS= ET + > >> DSC_GDTPTR] > >> + mov si, [cs:eax] ; > >> + mov eax, [cs:si] ; > >> + > >> mov [cs:bx + 2], eax > >> o32 lgdt [cs:bx] ; lgdt fword ptr cs:[bx] > >> mov ax, PROTECT_MODE_CS > >> @@ -166,7 +181,10 @@ Base: > >> @LongMode: ; long mode (64-bit code) star= ts here > >> mov rax, ASM_PFX(gStmSmiHandlerIdtr) > >> lidt [rax] > >> - lea ebx, [rdi + DSC_OFFSET] > >> + > >> + movzx rsi, word [ASM_PFX(gStmPsdOffset)] ; lea ebx, [rdi + > >> DSC_OFFSET] > >> + lea ebx, [rdi + rsi] ; > >> + > >> mov ax, [rbx + DSC_DS] > >> mov ds, eax > >> mov ax, [rbx + DSC_OTHERSEG] > >> @@ -262,5 +280,8 @@ _StmSmiHandler: > >> ; STM init finish > >> jmp CommonHandler > >> > >> +ASM_PFX(gStmGdtSize) : RESW 1 > >> +ASM_PFX(gStmGdtPtr) : RESW 1 > >> + > >> ASM_PFX(gcStmSmiHandlerSize) : DW $ - _StmSmiEntryPoint > >> ASM_PFX(gcStmSmiHandlerOffset) : DW _StmSmiHandler - > >> _StmSmiEntryPoint > >> -- > >> 2.7.4 > >