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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Jeff, The new PCD is intended to be OR'ed with the address (upper bits). Leo. > -----Original Message----- > From: Fan, Jeff [mailto:jeff.fan@intel.com] > Sent: Thursday, February 09, 2017 8:23 PM > To: Duran, Leo ; edk2-devel@ml01.01.org > Cc: Tian, Feng ; Zeng, Star ; > Laszlo Ersek ; Singh, Brijesh > Subject: RE: [PATCH 3/3] UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add > support for PCD PcdPteMemoryEncryptionAddressOrMask >=20 > Hi Leo, >=20 > I want to understand your usage model. What fields are you going to updat= e > in below Page Table Entry by the new PCD? >=20 > typedef union { > struct { > UINT64 Present:1; // 0 =3D Not present in memory, 1 = =3D Present in > memory > UINT64 ReadWrite:1; // 0 =3D Read-Only, 1=3D Read/Write > UINT64 UserSupervisor:1; // 0 =3D Supervisor, 1=3DUser > UINT64 WriteThrough:1; // 0 =3D Write-Back caching, 1=3DWr= ite-Through > caching > UINT64 CacheDisabled:1; // 0 =3D Cached, 1=3DNon-Cached > UINT64 Accessed:1; // 0 =3D Not accessed, 1 =3D Access= ed (set by CPU) > UINT64 Dirty:1; // 0 =3D Not Dirty, 1 =3D written b= y processor on access > to page > UINT64 MustBe1:1; // Must be 1 > UINT64 Global:1; // 0 =3D Not global page, 1 =3D glo= bal page TLB not > cleared on CR3 write > UINT64 Available:3; // Available for use by system soft= ware > UINT64 PAT:1; // > UINT64 MustBeZero:8; // Must be zero; > UINT64 PageTableBaseAddress:31; // Page Table Base Address > UINT64 AvabilableHigh:11; // Available for use by system soft= ware > UINT64 Nx:1; // 0 =3D Execute Code, 1 =3D No Cod= e Execution > } Bits; > UINT64 Uint64; > } PAGE_TABLE_ENTRY; >=20 > I did not see any updating in SMM. Is it un-necessary? Is this feature wo= rking > on POST phase or OS runtime phase? >=20 > Thanks! > Jeff >=20 > -----Original Message----- > From: Leo Duran [mailto:leo.duran@amd.com] > Sent: Thursday, February 09, 2017 5:13 AM > To: edk2-devel@ml01.01.org > Cc: Leo Duran; Fan, Jeff; Tian, Feng; Zeng, Star; Laszlo Ersek; Brijesh S= ingh > Subject: [PATCH 3/3] UefiCpuPkg/Universal/Acpi/S3Resume2Pei: Add > support for PCD PcdPteMemoryEncryptionAddressOrMask >=20 > This PCD holds the address mask for page table entries when memory > encryption is enabled on AMD processors supporting the Secure Encrypted > Virtualization (SEV) feature. >=20 > The mask is applied when page tables are created (S3Resume.c). >=20 > CC: Jeff Fan > Cc: Feng Tian > Cc: Star Zeng > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Brijesh Singh > Signed-off-by: Leo Duran > --- > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c | 9 +++++---- > UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf | 2 ++ > 2 files changed, 7 insertions(+), 4 deletions(-) >=20 > diff --git a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > index d306fba..ee1e2cd 100644 > --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c > @@ -5,6 +5,7 @@ > control is passed to OS waking up handler. >=20 > Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
> + Copyright (c) 2017, AMD Incorporated. All rights reserved.
>=20 > This program and the accompanying materials > are licensed and made available under the terms and conditions @@ -696= ,7 > +697,7 @@ RestoreS3PageTables ( > // > // Make a PML4 Entry > // > - PageMapLevel4Entry->Uint64 =3D > (UINT64)(UINTN)PageDirectoryPointerEntry; > + PageMapLevel4Entry->Uint64 =3D > + (UINT64)(UINTN)PageDirectoryPointerEntry | PcdGet64 > + (PcdPteMemoryEncryptionAddressOrMask); > PageMapLevel4Entry->Bits.ReadWrite =3D 1; > PageMapLevel4Entry->Bits.Present =3D 1; >=20 > @@ -707,7 +708,7 @@ RestoreS3PageTables ( > // > // Fill in the Page Directory entries > // > - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress; > + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | PcdGet6= 4 > + (PcdPteMemoryEncryptionAddressOrMask); > PageDirectory1GEntry->Bits.ReadWrite =3D 1; > PageDirectory1GEntry->Bits.Present =3D 1; > PageDirectory1GEntry->Bits.MustBe1 =3D 1; @@ -724,7 +725,7 @@ > RestoreS3PageTables ( > // > // Fill in a Page Directory Pointer Entries > // > - PageDirectoryPointerEntry->Uint64 =3D > (UINT64)(UINTN)PageDirectoryEntry; > + PageDirectoryPointerEntry->Uint64 =3D > + (UINT64)(UINTN)PageDirectoryEntry | PcdGet64 > + (PcdPteMemoryEncryptionAddressOrMask); > PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; > PageDirectoryPointerEntry->Bits.Present =3D 1; >=20 > @@ -732,7 +733,7 @@ RestoreS3PageTables ( > // > // Fill in the Page Directory entries > // > - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress; > + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | PcdGet6= 4 > + (PcdPteMemoryEncryptionAddressOrMask); > PageDirectoryEntry->Bits.ReadWrite =3D 1; > PageDirectoryEntry->Bits.Present =3D 1; > PageDirectoryEntry->Bits.MustBe1 =3D 1; diff --git > a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > index 73aeca3..d514523 100644 > --- a/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > +++ b/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf > @@ -6,6 +6,7 @@ > # control is passed to OS waking up handler. > # > # Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.
> +# Copyright (c) 2017, AMD Incorporated. All rights reserved.
> # > # This program and the accompanying materials are # licensed and made > available under the terms and conditions of the BSD License @@ -91,6 +92,= 7 > @@ [FeaturePcd] >=20 > [Pcd] > gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable ## > SOMETIMES_CONSUMES > + > gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrM > ask ## CONSUMES >=20 > [Depex] > TRUE > -- > 1.9.1