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Reviewed-By: Giri Mudusuru <girimudusuru@microsoft.com>
From: devel@edk2.groups.io = <devel@edk2.groups.io> on behalf of gaoliming via groups.io <gaoli= ming=3Dbyosoft.com.cn@groups.io>
Sent: Tuesday, April 23, 2024 6:15 AM
To: 'Nong, Foster' <foster.nong@intel.com>; devel@edk2.groups.= io <devel@edk2.groups.io>; Kinney, Michael D <michael.d.kinney@int= el.com>; 'Chris Li' <chrisli@os.amperecomputing.com>
Cc: Ni, Ray <ray.ni@intel.com>
Subject: [EXTERNAL] =BB=D8=B8=B4: [edk2-devel] [PATCH v1] MdePkg: Ad= d Cxl30.h into IndustryStandard
 
[You don't often get email from gaoliming=3Dbyosof= t.com.cn@groups.io. Learn why this is important at https://aka.ms/Le= arnAboutSenderIdentification ]

Seemly, there is no other comments. I create PR https://nam06.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fgithub.= com%2Ftianocore%2Fedk2%2Fpull%2F5585&data=3D05%7C02%7CGIRIMUDUSURU%40mi= crosoft.com%7Cca57d35e58164465cebf08dc63977616%7C72f988bf86f141af91ab2d7cd0= 11db47%7C1%7C0%7C638494749393738266%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjA= wMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7C&sdata= =3Do308QhikmXPwrSFQplHJvcEopdx0xj6LjONs1aB662Y%3D&reserved=3D0 to merge it.

Thanks
Liming
> -----=D3=CA=BC=FE=D4=AD=BC=FE-----
> =B7=A2=BC=FE=C8=CB: Nong, Foster <foster.nong@intel.com>
> =B7=A2=CB=CD=CA=B1=BC=E4: 2024=C4=EA4=D4=C223=C8=D5 18:07
> =CA=D5=BC=FE=C8=CB: gaoliming <gaoliming@byosoft.com.cn>; devel@= edk2.groups.io;
> Kinney, Michael D <michael.d.kinney@intel.com>; 'Chris Li'
> <chrisli@os.amperecomputing.com>
> =B3=AD=CB=CD: Ni, Ray <ray.ni@intel.com>
> =D6=F7=CC=E2: RE: [edk2-devel] [PATCH v1] MdePkg: Add Cxl30.h into
> IndustryStandard
>
> Hi Liming,
>
> What is the patch review status? Can this patch be merged?
>
> -----Original Message-----
> From: Nong, Foster
> Sent: Wednesday, December 27, 2023 2:05 PM
> To: gaoliming <gaoliming@byosoft.com.cn>; devel@edk2.groups.io; = Kinney,
> Michael D <michael.d.kinney@intel.com>; 'Chris Li'
> <chrisli@os.amperecomputing.com>
> Cc: Ni, Ray <ray.ni@intel.com>
> Subject: RE: [edk2-devel] [PATCH v1] MdePkg: Add Cxl30.h into
> IndustryStandard
>
> Thanks Liming!
> @'Chris Li' and @Kinney, Michael D, please help comment the patch. Tha= nks!
>
> -----Original Message-----
> From: gaoliming <gaoliming@byosoft.com.cn>
> Sent: Tuesday, December 19, 2023 9:05 PM
> To: devel@edk2.groups.io; Nong, Foster <foster.nong@intel.com>; = Kinney,
> Michael D <michael.d.kinney@intel.com>; 'Chris Li'
> <chrisli@os.amperecomputing.com>
> Cc: Ni, Ray <ray.ni@intel.com>
> Subject: =BB=D8=B8=B4: [edk2-devel] [PATCH v1] MdePkg: Add Cxl30.h int= o
> IndustryStandard
>
> Foster:
>   I have no comments for this patch. Acked-by: Liming Gao > <gaoliming@byosoft.com.cn>
>
> Thanks
> Liming
> > -----=D3=CA=BC=FE=D4=AD=BC=FE-----
> > =B7=A2=BC=FE=C8=CB: devel@edk2.groups.io <devel@edk2.groups.io= > =B4=FA=B1=ED Nong,
> Foster
> > =B7=A2=CB=CD=CA=B1=BC=E4: 2023=C4=EA12=D4=C219=C8=D5 18:17
> > =CA=D5=BC=FE=C8=CB: devel@edk2.groups.io; Kinney, Michael D
> > <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byo= soft.com.cn>;
> > Chris Li <chrisli@os.amperecomputing.com>
> > =B3=AD=CB=CD: Ni, Ray <ray.ni@intel.com>
> > =D6=F7=CC=E2: Re: [edk2-devel] [PATCH v1] MdePkg: Add Cxl30.h int= o
> > IndustryStandard
> >
> > @Gao, Liming @Chris Li @Kinney, Michael D,
> >
> > Don't forget reviewing the patch. Thanks!
> >
> > -----Original Message-----
> > From: Nong, Foster <foster.nong@intel.com>
> > Sent: Wednesday, November 29, 2023 2:57 PM
> > To: devel@edk2.groups.io
> > Cc: Nong, Foster <foster.nong@intel.com>; Kinney, Michael D=
> > <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byo= soft.com.cn>;
> > Ni, Ray <ray.ni@intel.com>; Chris Li <chrisli@os.amperec= omputing.com>
> > Subject: [PATCH v1] MdePkg: Add Cxl30.h into IndustryStandard
> >
> > REF: https://nam06.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Fb= ugzilla.tianocore.org%2Fshow_bug.cgi%3Fid%3D4516&data=3D05%7C02%7CGIRIM= UDUSURU%40microsoft.com%7Cca57d35e58164465cebf08dc63977616%7C72f988bf86f141= af91ab2d7cd011db47%7C1%7C0%7C638494749393747133%7CUnknown%7CTWFpbGZsb3d8eyJ= WIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C0%7C%7C%7= C&sdata=3DBhMIlbuDbU6Dc1RhHt665Gg950WKeeBW8%2FpmksXqgIs%3D&reserved= =3D0
> >
> > 1) Add CXL 3.0 header file to comply with CXL 3.0 specification > > 2) CXL 3.0 header will embed Cxl20.h
> > 3) Updated Cxl.h to point to 3.0 header file
> >
> > Signed-off-by: Foster Nong <foster.nong@intel.com>
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Ray Ni <ray.ni@intel.com>
> > Cc: Chris Li <chrisli@os.amperecomputing.com>
> > ---
> >  MdePkg/Include/IndustryStandard/Cxl.h   | &n= bsp; 2 +-
> >  MdePkg/Include/IndustryStandard/Cxl30.h | 315
> ++++++++++++++++++++
> >  2 files changed, 316 insertions(+), 1 deletion(-)
> >
> > diff --git a/MdePkg/Include/IndustryStandard/Cxl.h
> > b/MdePkg/Include/IndustryStandard/Cxl.h
> > index 9ad3242e25..cb623a355d 100755
> > --- a/MdePkg/Include/IndustryStandard/Cxl.h
> > +++ b/MdePkg/Include/IndustryStandard/Cxl.h
> > @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #i= fndef
> > _CXL_MAIN_H_ #define _CXL_MAIN_H_ -#include
> > <IndustryStandard/Cxl20.h>+#include <IndustryStandard/Cx= l30.h> // //
> > CXL assigned new Vendor ID //diff --git
> > a/MdePkg/Include/IndustryStandard/Cxl30.h
> > b/MdePkg/Include/IndustryStandard/Cxl30.h
> > new file mode 100644
> > index 0000000000..feb6b9c52f
> > --- /dev/null
> > +++ b/MdePkg/Include/IndustryStandard/Cxl30.h
> > @@ -0,0 +1,315 @@
> > +/** @file+  CXL 3.0 Register definitions++  This file = contains the
> register
> > definitions based on the Compute Express Link+  (CXL) Specif= ication
> Revision
> > 3.0.++  Copyright (c) 2023, Intel Corporation. All rights > > reserved.<BR>++
> > SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#ifndef
> > CXL30_H_+#define CXL30_H_++#include
> <IndustryStandard/Cxl20.h>++//+//
> > CXL Cache Memory Capability IDs+// Compute Express Link Specifica= tion
> > Revision 3.0 - Chapter 8.2.4 Table 8-22+//+#define
> > CXL_CACHE_MEM_CAPABILITY_ID_TIMEOUT_AND_ISOLATION
> > 0x0009+#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED
> > 0x000A+#define CXL_CACHE_MEM_CAPABILITY_ID_BI_ROUTE_TABLE
> > 0x000B+#define CXL_CACHE_MEM_CAPABILITY_ID_BI_DECODER
> > 0x000C+#define
> > CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_ROUTE_TABLE
> > 0x000D+#define CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_DECODER
> > 0x000E+#define
> > CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_HDM_DECODER
> > 0x000F++//+// CXL_Capability_Version+// Compute Express ink
> > 0x000F++Specification
> > Revision 3.0 - Chapter 8.2.4.5+//+#define
> CXL_HDM_DECODER_VERSION_30
> > 0x3++//+// CXL CXL HDM Decoder n Control+// Compute Express Link<= br> > > Specification Revision 3.0 - 8.2.4.19.7+//+//+// Bit4..7: Interle= ave
> > Ways (IW)+//+#define CXL_HDM_16_WAY_INTERLEAVING
> > 0x4+#define CXL_HDM_3_WAY_INTERLEAVING
> > 0x8+#define CXL_HDM_6_WAY_INTERLEAVING
> > 0x9+#define CXL_HDM_12_WAY_INTERLEAVING
> > 0xA++//+// Ensure proper structure formats+//+#pragma pack(1)++//= +//
> > CXL.cachemem Extended Register Capability+// Compute Express Link=
> > Specification Revision 3.0  - Chapter 8.2.4.24+//+typedef un= ion {+
> > struct
> {+
> > UINT32        ExtendedRangesBi= tmap : 16;  // Bit 0..15+    UINT32
> > Reserved         &nb= sp;   : 16;  // Bit 16..31+  } Bits;+  UINT32
> > Uint32;+} CXL_CM_EXTENTED_REGISTER_CAPABILITY;++#define
> > CXL_CM_EXTENTED_RANGES_BITMAP    (BIT2 | BIT3 | BI= T4 | BIT5 |
> BIT6
> > | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | BIT12 | BIT13 | BIT15)++//= +//
> > | CXL
> BI
> > Route Table Capability+// Compute Express Link Specification Revi= sion
> > 3.0
> -
> > Chapter 8.2.4.25+//+typedef union {+  struct {+  &= nbsp; UINT32
> > ExplicitBiRtCommitRequired      &nb= sp;            = :1;  // bit 0+
> > UINT32  Reserved       &n= bsp;            = ;            &n= bsp;     :31; //
> bit
> > 1..31+  } Bits;+  UINT32    Uint32;+} CX= L_BI_RT_CAPABILITY;++typedef
> > union {+  struct {+    UINT32
> > BiRtCommit         &= nbsp;           &nbs= p;            &= nbsp; :1;   // bit 0+
> > UINT32  Reserved       &n= bsp;            = ;            &n= bsp;     :31;  //
> > bit 1..31+  } Bits;+  UINT32    Uint32;+= }
> CXL_BI_RT_CONTROL;++typedef
> > union {+  struct {+    UINT32
> > BiRtCommitted        &nbs= p;            &= nbsp;           :1; = // bit 0+
> > UINT32  BiRtErrorNotCommitted     &= nbsp;           &nbs= p;       :1;  // bit
> > 1+    UINT32
> Reserved1          &= nbsp;           &nbs= p;            &= nbsp; :6;
> > // bit 2..7+    UINT32
> > BiRtCommitTimeoutScale       &= nbsp;           &nbs= p;    :4;  // bit 8..11+
> > UINT32  BiRtCommitTimeoutBase     &= nbsp;           &nbs= p;       :4;  //
> bit
> > 12..15+    UINT32
> > Reserved2         &n= bsp;            = ;            &n= bsp;  :16; // bit
> 16..31+  }
> > Bits;+  UINT32    Uint32;+} CXL_BI_RT_STATUS;= ++typedef struct {+
> > CXL_BI_RT_CAPABILITY
> BiRtCap;
> > // offset 0x00+  CXL_BI_RT_CONTROL
> > BiRtControl;   // offset 0x04+  CXL_BI_RT_STATUS > > BiRtStatus;    // offset 0x08+}
> CXL_BI_ROUTE_TABLE_CAPABILITY;++//+//
> > CXL BI Decoder Capability+// Compute Express Link Specification > > Revision
> 3.0
> > - Chapter 8.2.4.26+//+typedef union {+  struct {+  = ;  UINT32
> > HdmDCapable         =             &nb= sp;            = :1;  // bit 0+
> > UINT32  ExplicitBiDecoderCommitRequired   &nb= sp;           :1;  /= / bit
> 1+
> > UINT32  Reserved       &n= bsp;            = ;            &n= bsp;     :30; //
> bit
> > 2..31+  } Bits;+  UINT32    Uint32;+} CX= L_BI_DECODER_CAP;++typedef
> > union {+  struct {+    UINT32
> > BiForward         &n= bsp;            = ;            &n= bsp;  :1;  // bit 0+
> > UINT32  BiEnable       &n= bsp;            = ;            &n= bsp;     :1;  //
> bit
> > 1+    UINT32
> BiDecoderCommit         &= nbsp;           &nbs= p;         :1;
> > // bit 2+    UINT32
> > Reserved         &nb= sp;            =             &nb= sp;   :29; // bit
> 3..31+  }
> > Bits;+  UINT32    Uint32;+} CXL_BI_DECODER_CO= NTROL;++typedef
> union
> > {+  struct {+    UINT32
> > BiDecoderCommitted        = ;            &n= bsp;       :1;  // bit 0+
> > UINT32  BiDecoderErrorNotCommitted    &n= bsp;            = ;   :1;  // bit
> > 1+    UINT32
> Reserved1          &= nbsp;           &nbs= p;            &= nbsp; :6;
> > // bit 2..7+    UINT32
> > BiDecoderCommitTimeoutScale      &n= bsp;            :4;&= nbsp; // bit 8..11+
> > UINT32  BiDecoderCommitTimeoutBase    &n= bsp;            = ;   :4;  //
> bit
> > 12..15+    UINT32
> > Reserved2         &n= bsp;            = ;            &n= bsp;  :16; // bit
> 16..31+  }
> > Bits;+  UINT32    Uint32;+} CXL_BI_DECODER_ST= ATUS;++typedef struct
> {+
> > CXL_BI_DECODER_CAP        = ;            &n= bsp;         BiDecoderCap;
> > // offset 0x00+  CXL_BI_DECODER_CONTROL
> > BiDecoderControl;        = // offset 0x04+  CXL_BI_DECODER_STATUS
> > BiDecoderStatus;        &= nbsp; // offset 0x08+}
> > CXL_BI_DECODER_CAPABILITY;++//+// CXL Cache ID Route Table
> > Capability+// Compute Express Link Specification Revision 3.0&nbs= p; -
> > Capability+Chapter
> > 8.2.4.27+//+typedef union {+  struct {+    UI= NT32
> > CacheIdTargetCount        = ;           : 5; &nb= sp; // Bit 0..4+    UINT32
> > Reserved1         &n= bsp;            = ;      : 3;   // Bit 5..7+  &n= bsp; UINT32
> > HdmDType2DeviceMaxCount       =        : 4;   // Bit 8..11+
> > UINT32        Reserved2 &= nbsp;           &nbs= p;            &= nbsp; : 4;   // Bit
> > 12..15+    UINT32     &nb= sp;  ExplicitCacheIdRtCommitRequired      : 1= ;
> > // Bit 16+    UINT32
> Reserved3          &= nbsp;           &nbs= p;     :
> > 15;  // Bit 17:31+  } Bits;+  UINT32  &n= bsp;       Uint32;+}
> > CXL_CACHE_ID_RT_CAPABILITY;++typedef union {+  struct {+&nbs= p;   UINT32
> > CacheIdRtCommit        &n= bsp;    : 1;   // Bit 0+    UINT32<= br> > > Reserved         &nb= sp;          : 31;  // Bi= t 1..31+  } Bits;+  UINT32
> > Uint32;+} CXL_CACHE_ID_RT_CONTROL;++typedef union {+  struct= {+
> > UINT32        CacheIdRtCommitt= ed          : 1;   /= / Bit 0+
> > UINT32        CacheIdRtErrNotC= ommitted    : 1;   // Bit 1+
> > UINT32        Reserved1 &= nbsp;           &nbs= p;     : 6;   // Bit 2..7+
> > UINT32        CacheIdRtCommitT= imeoutScale : 4;   // Bit 8..11+
> > UINT32        CacheIdRtCommitT= imeoutBase  : 4;   // Bit 12..15+
> > UINT32        Reserved2 &= nbsp;           &nbs= p;     : 16;  // Bit 16..31+  }
> > Bits;+  UINT32       &nbs= p;  Uint32;+}
> CXL_CACHE_ID_RT_STATUS;++typedef
> > union {+  struct {+    UINT16
> Valid           = ;            :
> > 1;  // Bit 0+    UINT16   &nbs= p;    Reserved       &nbs= p;            : 7; > //
> > Bit 1..7+    UINT16     &= nbsp;  PortNumber         = ;         : 8;  //
> Bit
> > 8..15+  } Bits;+  UINT16     &= nbsp;    Uint16;+}
> > CXL_CACHE_ID_RT_TARGET;++typedef struct {+
> > CXL_CACHE_ID_RT_CAPABILITY      &nb= sp;   CacheIdRtCap;       &nbs= p; //
> > offset 0x00+  CXL_CACHE_ID_RT_CONTROL
> > CacheIdRtControl;     // offset 0x04+  C= XL_CACHE_ID_RT_STATUS
> > CacheIdRtStatus;      // offset 0x08+&nb= sp; UINT32
> > Reserved;         &n= bsp;   // offset 0x0C+  CXL_CACHE_ID_RT_TARGET
> > CacheIdRtTarget[];    // offset 0x10+}
> > CXL_CACHE_ID_ROUTE_TABLE_CAPABILITY;++//+// CXL Cache ID Decoder<= br> > > Capability+// Compute Express Link Specification Revision 3.0&nbs= p; -
> > Capability+Chapter
> > 8.2.4.28+//+typedef union {+  struct {+    UI= NT32
> > ExplicitCacheIdDecoderCommitRequired     = ; : 1;   // Bit 0+    UINT32
> > Reserved         &nb= sp;            =             : 31;&nb= sp; // Bit 1..31+  }
> > Bits;+  UINT32       &nbs= p;  Uint32;+}
> > CXL_CACHE_ID_DECODER_CAP;++typedef union {+  struct {+ =    UINT32
> > ForwardCacheId        &nb= sp;     : 1;  // Bit 0+    UINT32 > > AssignCacheId        &nbs= p;      : 1;  // Bit 1+    UIN= T32
> > HdmDType2DevicePresent      : 1;  /= / Bit 2+    UINT32
> > CacheIdDecoderCommit        : = 1;  // Bit 3+    UINT32
> > Reserved1         &n= bsp;         : 4;  // Bit 4..7= +    UINT32
> > HdmDType2DeviceCacheId      : 4;  /= / Bit 8..11+    UINT32
> > Reserved2         &n= bsp;         : 4;  // Bit 12..= 15+    UINT32
> > LocalCacheId         = ;       : 4;  // Bit 16..19+  =   UINT32
> > Reserved3         &n= bsp;         : 4;  // Bit 20..= 23+    UINT32
> > TrustLevel         &= nbsp;        : 2;  // Bit 24..25+&n= bsp;   UINT32
> > Reserved4         &n= bsp;         : 6;  // Bit 26..= 31+  } Bits;+  UINT32
> > Uint32;+} CXL_CACHE_ID_DECODER_CONTROL;++typedef union {+  s= truct
> > {+    UINT32      &n= bsp; CacheIdDecoderCommitted        = ;      : 1;
> > // Bit 0+    UINT32     &= nbsp;  CacheIdDecoderErrorNotCommitted      :=
> 1;
> > // Bit 1+    UINT32
> Reserved1          &= nbsp;           &nbs= p;     :
> > 6;   // Bit 2..7+    UINT32
> > CacheIdDecoderCommitTimeoutScale     : 4;&nbs= p;  // Bit 8..11+    UINT32
> > CacheIdDecoderCommitTimeoutBase      : 4= ;   // Bit 12..15+
> > UINT32        Reserved2 &= nbsp;           &nbs= p;            &= nbsp; : 16;  // Bit
> > 16..31+  } Bits;+  UINT32     =      Uint32;+}
> > CXL_CACHE_ID_DECODER_STATUS;++typedef struct {+
> > CXL_CACHE_ID_DECODER_CAP       = ;     CacheIdDecoderCap;
> > // offset 0x00+  CXL_CACHE_ID_DECODER_CONTROL
> > CacheIdDecoderControl;   // offset 0x04+
> > CXL_CACHE_ID_DECODER_STATUS      &n= bsp;  CacheIdDecoderStatus;
> //
> > offset 0x08+} CXL_CACHE_ID_DECODER_CAPABILITY;++//+// CXL Timeout=
> and
> > Isolation Capability Structure+// Compute Express Link Specificat= ion
> > Revision 3.0  - Chapter 8.2.4.23+//+typedef union {+  s= truct {+
> UINT32
> > CxlmemTransactionTimeoutRangesSupported   : 4;  //= Bits 3:0+
> > UINT32 CxlmemTransactionTimeoutSupported    &= nbsp;    : 1;  // Bits 4+
> > UINT32 Reserved1        &= nbsp;           &nbs= p;            : 3;&n= bsp; // Bits
> 7:5+
> > UINT32 CxlcacheTransactionTimeoutRangesSupported : 4;  // Bi= ts 11:8+
> > UINT32 CxlcacheTransactionTimeoutSupported    = ;   : 1;  // Bits 12+
> > UINT32 Reserved2        &= nbsp;           &nbs= p;            : 3;&n= bsp; // Bits
> > 15:13+    UINT32 CxlmemIsolationSupported &nb= sp;            =     : 1;
> //
> > Bits 16+    UINT32 CxlmemIsolationLinkdownSupporte= d          : 1;
> > // Bits 17+    UINT32 CxlcacheIsolationSupported&n= bsp;            = ;   : 1;
> > // Bits 18+    UINT32 CxlcacheIsolationLinkdownSup= ported        : 1;
> > // Bits 19+    UINT32
> Reserved3          &= nbsp;           &nbs= p;          :
> > 5;  // Bits 24:20+    UINT32
> IsolationErrCorSignalingSupported      &= nbsp;  :
> > 1;  // Bits 25+    UINT32 IsolationInterruptS= upported           &= nbsp;   :
> 1;
> > // Bits 26+    UINT32 IsolationInterruptMessageNum= ber           : 5;
> > // Bits 31:27+  } Bits;+  UINT32
> > Data32;+}
> CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY;++typedef
> > union {+  struct {+    UINT32 CxlmemTransacti= onTimeoutValue    : 4;
> > // Bits 3:0+    UINT32 CxlmemTransactionTimeoutEna= ble   : 1;  // Bits
> > 4+    UINT32 Reserved1    &nbs= p;            &= nbsp;      : 3;  // Bits 7:5+
> > UINT32 CxlcacheTransactionTimeoutValue  : 4;  // Bits 1= 1:8+
> UINT32
> > CxlcacheTransactionTimeoutEnable : 1;  // Bits 12+ &nbs= p;  UINT32
> > Reserved2         &n= bsp;            = ;  : 3;  // Bits 15:13+    UINT32
> > CxlmemIsolationEnable       &n= bsp;    : 1;  // Bits 16+    UINT32
> > CxlmemIsolationLinkdownEnable    : 1;  // Bit= s 17+    UINT32
> > CxlcacheIsolationEnable       =    : 1;  // Bits 18+    UINT32
> > CxlcacheIsolationLinkdownEnable  : 1;  // Bits 19+ = ;   UINT32
> > Reserved3         &n= bsp;            = ;  : 5;  // Bits 24:20+    UINT32
> > IsolationErrCorSignalingEnable   : 1;  // Bits 25+=     UINT32
> > IsolationInterruptEnable       = ;  : 1;  // Bits 26+    UINT32
> > Reserved4         &n= bsp;            = ;  : 5;  // Bits 31:27+  } Bits;+
> > UINT32          = ;            &n= bsp;            = ; Data32;+}
> > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CONTROL;++typedef union {+
> > struct {+    UINT32 CxlmemTransactionTimeout =        : 1;   // Bits
> 0+
> > UINT32 Reserved1        &= nbsp;           &nbs= p;  : 3;   // Bits 3:1+
> > UINT32 CxlcacheTransactionTimeout      := 1;   // Bits 4+    UINT32
> > Reserved2         &n= bsp;            = ; : 3;   // Bits 7:5+    UINT32
> > CxlmemIsolationStatus       &n= bsp;   : 1;   // Bits 8+    UINT32
> > CxlmemIsolationLinkdownStatus   : 1;   // Bit= s 9+    UINT32
> > Reserved3         &n= bsp;            = ; : 2;   // Bits 11:10+    UINT32
> > CxlcacheIsolationStatus       =   : 1;   // Bits 12+    UINT32
> > CxlcacheIsolationLinkdownStatus : 1;   // Bits 13+ = ;   UINT32
> > CxlRpBusy         &n= bsp;            = ; : 1;   // Bits 14+    UINT32
> > Reserved4         &n= bsp;            = ; : 17;  // Bits 31:15+  } Bits;+
> > UINT32          = ;            &n= bsp;            Data= 32;+}
> > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS;++typedef struct {+
> > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY
> > TimeoutAndIsolationCap;+  UINT32
> > Reserved;+  CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CONTROL
> > TimeoutAndIsolationControl;+
> > CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS
> > TimeoutAndIsolationStatus;+}
> >
> CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE;++#pra
> > gma pack()++#endif--
> > 2.37.1.windows.1
> >
> >
> >
> >
> >
>
>








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