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Thread-Topic: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64. 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Customer confirmed it. -Andrew From: Kim, Andrew Sent: Thursday, January 14, 2021 10:14 AM To: Zhong, Zarcd Cc: Wu, Hao A ; Kinney, Michael D ; devel@edk2.groups.io; Ni, Ray Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. BTW, to be clear for this to try. Could you confirm if this is right update with your suggestion? if (EFI_ERROR (Status)) { PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown; return Offset + 4; } -Andrew From: Kim, Andrew Sent: Thursday, January 14, 2021 9:38 AM To: Zhong, Zarcd > Cc: Wu, Hao A >; Kinney, Mich= ael D >; deve= l@edk2.groups.io; Ni, Ray > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Hi Zarcd, Thanks for this update. Sure, I will let you know once it has been verified. -Andrew From: Zhong, Zarcd > Sent: Wednesday, January 13, 2021 10:32 PM To: Kim, Andrew > Cc: Wu, Hao A >; Kinney, Mich= ael D >; deve= l@edk2.groups.io; Ni, Ray > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Hi Kim, Ray suggests a one line patch instead of google's solution. + PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown; Could you help to verify Ray's solution on that card? From: Ni, Ray > Sent: Thursday, January 14, 2021 1:59 PM To: Zhong, Zarcd >; dev= el@edk2.groups.io Cc: Wu, Hao A >; Kinney, Mich= ael D > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Zarcd, I may not say very clearly. I prefer to just keep below line. Can you check= whether that can work? + PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown; Thanks, Ray From: Zhong, Zarcd > Sent: Thursday, January 14, 2021 10:48 AM To: Ni, Ray >; devel@edk2.groups.= io Cc: Wu, Hao A >; Kinney, Mich= ael D > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Hi Ray, Attached patch is updated with below add. Thanks for your remind. PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown; From: Ni, Ray > Sent: Wednesday, January 13, 2021 3:01 PM To: Zhong, Zarcd >; dev= el@edk2.groups.io Cc: Wu, Hao A >; Kinney, Mich= ael D > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Zarcd, I can understand that this patch is needed for some buggy pci devices whose VF bar behaves strangely. Incompatible PCI protocol can only deal with norm= al PCI bar. And this patch is just to enhance the error handling logic. Can you please use below code for error handling? + PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown I understand that your change is aligned to existing error handling in the = beginning of PciIovParseVfBar(). But that logic runs before PciIoDevice->VfPciBar[BarIndex].BarType is assig= ned. The key is to reset the BarType to PciBarTypeUnknown so that the resource s= ummary code doesn't count this bar. Thanks, Ray From: Zhong, Zarcd > Sent: Monday, January 4, 2021 5:48 PM To: devel@edk2.groups.io Cc: Ni, Ray >; Wu, Hao A > Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in = high 32bit of MEM64. >>From 7518212a85269e486d06dcea927a3d34e23372c2 Mon Sep 17 00:00:00 2001 From: Zarcd Zhong > Date: Mon, 4 Jan 2021 17:32:54 +0800 Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in = high 32bit of MEM64. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3149 Clear length and alignment for low 32bit of MEM64 BAR if sizing fail in= high 32bit. Cc: Ray Ni > Cc: Hao A Wu > --_000_DM6PR11MB27646FEF719BE10F3E8F754C85A70DM6PR11MB2764namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Hi Zarcd,

 

It works fine with this Ray’s solution. Custom= er confirmed it.

 

-Andrew

 

From: Kim, Andrew
Sent: Thursday, January 14, 2021 10:14 AM
To: Zhong, Zarcd <zarcd.zhong@intel.com>
Cc: Wu, Hao A <hao.a.wu@intel.com>; Kinney, Michael D <mich= ael.d.kinney@intel.com>; devel@edk2.groups.io; Ni, Ray <ray.ni@intel.= com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

BTW, to be clear for this to try.

Could you confirm if this is right update with your = suggestion?

 

 

      if (EFI_ERROR (Status= )) {

        PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeU= nknown;

 

        return Of= fset + 4;

      }

 

 

-Andrew

 

From: Kim, Andrew
Sent: Thursday, January 14, 2021 9:38 AM
To: Zhong, Zarcd <zarcd.= zhong@intel.com>
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>; devel@edk2.groups.io; Ni, Ray &= lt;ray.ni@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Hi Zarcd,

 

Thanks for this update.

 

Sure, I will let you know once it has been verified.=

 

-Andrew

 

From: Zhong, Zarcd <zarcd.zhong@intel.com>
Sent: Wednesday, January 13, 2021 10:32 PM
To: Kim, Andrew <andrew.k= im@intel.com>
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>; devel@edk2.groups.io; Ni, Ray &= lt;ray.ni@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Hi Kim,

 

Ray suggests  a one line patch instead of googl= e’s solution.

+        PciIoDev= ice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown;

 

Could you help to verify Ray’s solution on tha= t card?

 

 

 

 

From: Ni, Ray <ray.ni@intel.com>
Sent: Thursday, January 14, 2021 1:59 PM
To: Zhong, Zarcd <zarcd.= zhong@intel.com>; devel@edk2.groups.io
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Zarcd,

I may not say very clearly. I prefer to just keep be= low line. Can you check whether that can work?

+        PciIoDev= ice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown;

 

Thanks,
Ray

 

From: Zhong, Zarcd <zarcd.zhong@intel.com>
Sent: Thursday, January 14, 2021 10:48 AM
To: Ni, Ray <ray.ni@intel.com= >; devel@edk2.groups.io
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Hi Ray,

 

Attached patch is updated with below add. Thanks for= your remind.

 

PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBa= rTypeUnknown;

 

 

From: Ni, Ray <ray.ni@intel.com>
Sent: Wednesday, January 13, 2021 3:01 PM
To: Zhong, Zarcd <zarcd.= zhong@intel.com>; devel@edk2.groups.io
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Zarcd,

I can understand that this patch is needed for some = buggy pci devices whose
VF bar behaves strangely. Incompatible PCI protocol can only deal with norm= al
PCI bar. And this patch is just to enhance the error handling logic.

 

Can you please use below code for error handling?

+        PciIoDev= ice->VfPciBar[BarIndex].BarType     =3D PciBarTypeUn= known

 

I understand that your change is aligned to existing= error handling in the beginning
of PciIovParseVfBar().

But that logic runs before PciIoDevice->VfPciBar[= BarIndex].BarType is assigned.

The key is to reset the BarType to PciBarTypeUnknown= so that the resource summary
code doesn’t count this bar.

 

Thanks,

Ray

 

From: Zhong, Zarcd <zarcd.zhong@intel.com>
Sent: Monday, January 4, 2021 5:48 PM
To: devel@edk2.groups.io=
Cc: Ni, Ray <ray.ni@intel.com= >; Wu, Hao A <hao.a.wu@inte= l.com>
Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing f= ail in high 32bit of MEM64.

 

From 7518212a85269e486d06dcea927a3d34e23372c2 Mon Se= p 17 00:00:00 2001

From: Zarcd Zhong <zarcd.zhong@intel.com>

Date: Mon, 4 Jan 2021 17:32:54 +0800

Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Han= dle BAR sizing fail in high 32bit of MEM64.

 

    REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3149

 

    Clear length and alignment for lo= w 32bit of MEM64 BAR if sizing fail in high 32bit.

 

    Cc: Ray Ni <ray.ni@intel.com>

    Cc: Hao A Wu <hao.a.wu@intel.com>

--_000_DM6PR11MB27646FEF719BE10F3E8F754C85A70DM6PR11MB2764namp_--