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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Patch V3 addressed all my previous comments. It looks good to me. Reviewed-by: Maurice Ma Regards, Maurice > -----Original Message----- > From: Ni, Ray > Sent: Wednesday, June 17, 2020 1:41 > To: devel@edk2.groups.io > Cc: Ma, Maurice ; Dong, Guo ; > You, Benjamin > Subject: [PATCH V3 2/2] UefiPayloadPkg/Pci: Use the PCIE Base Addr stored= in > AcpiBoardInfo HOB >=20 > Today's UefiPayloadPkg always uses 0xE0000000 as the PCIE base address an= d > ignores the value set in AcpiBoardInfo HOB created by the boot loader. Th= is > makes the payload binary cannot work in environment where the PCIE base > address set by boot loader doesn't equal to 0xE0000000. >=20 > The patch enhances UefiPayloadPkg so that the PCIE base address set by bo= ot > loader in the AcpiBoardInfo HOB is used. >=20 > Signed-off-by: Ray Ni > Cc: Maurice Ma > Cc: Guo Dong > Cc: Benjamin You > --- > UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c | 13 +++- > UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf | 3 +- > .../PciSegmentInfoLibAcpiBoardInfo.c | 59 +++++++++++++++++++ > .../PciSegmentInfoLibAcpiBoardInfo.inf | 36 +++++++++++ > UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 10 ++-- > UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 11 ++-- > 6 files changed, 121 insertions(+), 11 deletions(-) create mode 100644 > UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAc > piBoardInfo.c > create mode 100644 > UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLibAc > piBoardInfo.inf >=20 > diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c > b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c > index 28dfc8fc55..a3974dcc02 100644 > --- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c > +++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c > @@ -2,7 +2,7 @@ > This driver will report some MMIO/IO resources to dxe core, extract sm= bios > and acpi tables from bootloader. - Copyright (c) 2014 - 2019, Intel Co= rporation. > All rights reserved.
+ Copyright (c) 2014 - 2020, Intel Corporation. = All rights > reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/@@ -101,= 6 > +101,7 @@ BlDxeEntryPoint ( > EFI_HOB_GUID_TYPE *GuidHob; SYSTEM_TABLE_INFO > *SystemTableInfo; EFI_PEI_GRAPHICS_INFO_HOB *GfxInfo;+ > ACPI_BOARD_INFO *AcpiBoardInfo; Status =3D EFI_SUCCESS; /= /@@ - > 153,6 +154,16 @@ BlDxeEntryPoint ( > ASSERT_EFI_ERROR (Status); } + //+ // Set PcdPciExpressBaseAddre= ss by > HOB info+ //+ GuidHob =3D GetFirstGuidHob (&gUefiAcpiBoardInfoGuid);+ = if > (GuidHob !=3D NULL) {+ AcpiBoardInfo =3D (ACPI_BOARD_INFO > *)GET_GUID_HOB_DATA (GuidHob);+ Status =3D PcdSet64S > (PcdPciExpressBaseAddress, AcpiBoardInfo->PcieBaseAddress);+ > ASSERT_EFI_ERROR (Status);+ }+ return EFI_SUCCESS; } diff --git > a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf > b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf > index 4c2b4670af..1371d5eb79 100644 > --- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf > +++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf > @@ -3,7 +3,7 @@ > # # Report some MMIO/IO resources to dxe core, extract smbios and acpi t= ables > #-# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.+# > Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
# = # SPDX- > License-Identifier: BSD-2-Clause-Patent #@@ -53,6 +53,7 @@ [Pcd] > gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution > gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution > gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution+ > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress [Depex] TRUEdiff --g= it > a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLib > AcpiBoardInfo.c > b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLib > AcpiBoardInfo.c > new file mode 100644 > index 0000000000..d37c91cc9f > --- /dev/null > +++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentIn > +++ foLibAcpiBoardInfo.c > @@ -0,0 +1,59 @@ > +/** @file+ PCI Segment Information Library that returns one segment who= se+ > segment base address is retrieved from AcpiBoardInfo HOB.++ Copyright (c= ) > 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifi= er: > BSD-2-Clause-Patent++**/++#include +#include > ++#include +#include > +#include ++STATIC > PCI_SEGMENT_INFO mPciSegment0 =3D {+ 0, // Segment number+ 0, // To b= e > fixed later+ 0, // Start bus number+ 255 // End bus number+};++/**+ R= eturn > an array of PCI_SEGMENT_INFO holding the segment information.++ Note: Th= e > returned array/buffer is owned by callee.++ @param Count Return the co= unt > of segments.++ @retval A callee owned array holding the segment > information.+**/+PCI_SEGMENT_INFO *+EFIAPI+GetPciSegmentInfo (+ UINTN > *Count+ )+{+ EFI_HOB_GUID_TYPE *GuidHob;+ ACPI_BOARD_INFO > *AcpiBoardInfo;++ ASSERT (Count !=3D NULL);+ if (Count =3D=3D NULL) {+ = return > NULL;+ }++ if (mPciSegment0.BaseAddress =3D=3D 0) {+ //+ // Find = the acpi > board information guid hob+ //+ GuidHob =3D GetFirstGuidHob > (&gUefiAcpiBoardInfoGuid);+ ASSERT (GuidHob !=3D NULL);++ AcpiBoard= Info =3D > (ACPI_BOARD_INFO *) GET_GUID_HOB_DATA (GuidHob);+ > mPciSegment0.BaseAddress =3D AcpiBoardInfo->PcieBaseAddress;+ }+ *Count= =3D > 1;+ return &mPciSegment0;+}diff --git > a/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLib > AcpiBoardInfo.inf > b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentInfoLib > AcpiBoardInfo.inf > new file mode 100644 > index 0000000000..ec4dbaaa55 > --- /dev/null > +++ b/UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/PciSegmentIn > +++ foLibAcpiBoardInfo.inf > @@ -0,0 +1,36 @@ > +## @file+# PCI Segment Information Library that returns one segment > whose+# segment base address is retrieved from AcpiBoardInfo HOB.+#+# > Copyright (c) 2020, Intel Corporation. All rights reserved.
+#+# SPDX= - > License-Identifier: BSD-2-Clause-Patent+#+#+##++[Defines]+ INF_VERSION > =3D 0x00010005+ BASE_NAME =3D PciSegmentInfoLibAcpi= BoardInfo+ > FILE_GUID =3D 0EA82AA2-6C36-4FD5-BC90-FFA3ECB5E0CE+ > MODULE_TYPE =3D BASE+ VERSION_STRING = =3D 1.0+ > LIBRARY_CLASS =3D PciSegmentInfoLib | DXE_DRIVER++#+# Th= e > following information is for reference only and not required by the build > tools.+#+# VALID_ARCHITECTURES =3D IA32 X64 EBC+#++[Sources]+ > PciSegmentInfoLibAcpiBoardInfo.c++[Packages]+ MdePkg/MdePkg.dec+ > UefiPayloadPkg/UefiPayloadPkg.dec++[LibraryClasses]+ PcdLib+ HobLib+ > DebugLibdiff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > index d52945442e..4ce1b8ef1c 100644 > --- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > +++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc > @@ -3,7 +3,7 @@ > # # Provides drivers and definitions to create uefi payload for bootload= ers. #-# > Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+# > Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
# = SPDX- > License-Identifier: BSD-2-Clause-Patent # ##@@ -40,7 +40,7 @@ [Defines] > # # PCI options #- DEFINE PCIE_BASE =3D 0xE000= 0000+ DEFINE > PCIE_BASE_SUPPORT =3D TRUE # # Serial port set up@@ -121,= 14 > +121,15 @@ [LibraryClasses] > PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf > CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf-!if $(PCIE= _BASE) > =3D=3D 0+!if $(PCIE_BASE_SUPPORT) =3D=3D FALSE > PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf > PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf !else > PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf !end= if- > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i > nf+ > PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLi > bSegmentInfo.inf+ > PciSegmentInfoLib|UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/P > ciSegmentInfoLibAcpiBoardInfo.inf > PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf > PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC > offGetEntryPointLib.inf > CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCache > MaintenanceLib.inf@@ -357,6 +358,7 @@ [PcdsDynamicDefault] > gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 > gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100+ > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0 > ############################################################# > ################### #diff --git > a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > index 0736cd9954..7388543751 100644 > --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc > @@ -3,7 +3,7 @@ > # # Provides drivers and definitions to create uefi payload for bootload= ers. #-# > Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.
+# > Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
# = SPDX- > License-Identifier: BSD-2-Clause-Patent # ##@@ -41,7 +41,7 @@ [Defines] > # # PCI options #- DEFINE PCIE_BASE =3D 0xE000= 0000+ DEFINE > PCIE_BASE_SUPPORT =3D TRUE # # Serial port set up@@ -122,= 14 > +122,15 @@ [LibraryClasses] > PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf > CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf > IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf-!if $(PCIE= _BASE) > =3D=3D 0+!if $(PCIE_BASE_SUPPORT) =3D=3D FALSE > PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf > PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf !else > PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf !end= if- > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i > nf+ > PciSegmentLib|MdePkg/Library/PciSegmentLibSegmentInfo/BasePciSegmentLi > bSegmentInfo.inf+ > PciSegmentInfoLib|UefiPayloadPkg/Library/PciSegmentInfoLibAcpiBoardInfo/P > ciSegmentInfoLibAcpiBoardInfo.inf > PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf > PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC > offGetEntryPointLib.inf > CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCache > MaintenanceLib.inf@@ -288,7 +289,6 @@ [PcdsFixedAtBuild] > gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE > gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, > 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0= x23, > 0x31 } - > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|$(PCIE_BASE) !if > $(SOURCE_DEBUG_ENABLE) > gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2@ > @ -359,6 +359,7 @@ [PcdsDynamicDefault] > gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 > gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100+ > gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0 > ############################################################# > ################### #-- > 2.26.2.windows.1