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Tue, 7 Jul 2020 02:54:11 +0000 From: "Dong, Eric" To: Garrett Kirkendall , "devel@edk2.groups.io" CC: "Ni, Ray" , Laszlo Ersek Subject: Re: [PATCH v6 4/4] UefiCpuPkg: PiSmmCpuDxeSmm skip MSR_IA32_MISC_ENABLE manipulation on AMD Thread-Topic: [PATCH v6 4/4] UefiCpuPkg: PiSmmCpuDxeSmm skip MSR_IA32_MISC_ENABLE manipulation on AMD Thread-Index: AQHWSJewsXbQ6d4Sg0ibDJ74RdTr1aj7gn6w Date: Tue, 7 Jul 2020 02:54:11 +0000 Message-ID: References: <20200622131825.1352-1-Garrett.Kirkendall@amd.com> <20200622131825.1352-5-Garrett.Kirkendall@amd.com> In-Reply-To: <20200622131825.1352-5-Garrett.Kirkendall@amd.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: amd.com; dkim=none (message not signed) header.d=none;amd.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.102.204.38] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5d3b17da-489f-4fdc-efee-08d8222106fc x-ms-traffictypediagnostic: DM6PR11MB4490: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Eric Dong > -----Original Message----- > From: Garrett Kirkendall > Sent: Monday, June 22, 2020 9:18 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Laszlo > Ersek > Subject: [PATCH v6 4/4] UefiCpuPkg: PiSmmCpuDxeSmm skip > MSR_IA32_MISC_ENABLE manipulation on AMD >=20 > AMD does not support MSR_IA32_MISC_ENABLE. Accessing that register > causes and exception on AMD processors. If Execution Disable is supporte= d, > but if the processor is an AMD processor, skip manipulating > MSR_IA32_MISC_ENABLE[34] XD Disable bit. >=20 > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Signed-off-by: Garrett Kirkendall > --- >=20 > Notes: > Tested on Intel hardware with Laszlo Ersek's help >=20 > (1) downloaded two Linux images from provided links. > (2) Test using a 32-bit guest on an Intel host (standing in your edk2= tree, > with the patches applied): >=20 > $ build -a IA32 -b DEBUG -p OvmfPkg/OvmfPkgIa32.dsc -t GCC5 -D > SMM_REQUIRE >=20 > $ qemu-system-i386 \ > -cpu coreduo,-nx \ > -machine q35,smm=3Don,accel=3Dkvm \ > -m 4096 \ > -smp 4 \ > -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ > -drive > if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild/OvmfIa32/DEB= UG_GCC > 5/FV/OVMF_CODE.fd \ > -drive > if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild/OvmfIa32/DEB= UG_GCC > 5/FV/OVMF_VARS.fd \ > -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfed= ora-30-efi- > systemd-i686.qcow2 \ > -device virtio-scsi-pci,id=3Dscsi0 \ > -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 >=20 > (Once you get a login prompt, feel free to interrupt QEMU with Ctrl-C= .) >=20 > (3) Test using a 64-bit guest on an Intel host: >=20 > $ build -a IA32 -a X64 -b DEBUG -p OvmfPkg/OvmfPkgIa32X64.dsc -t GCC5= - > D SMM_REQUIRE >=20 > $ qemu-system-x86_64 \ > -cpu host \ > -machine q35,smm=3Don,accel=3Dkvm \ > -m 4096 \ > -smp 4 \ > -global driver=3Dcfi.pflash01,property=3Dsecure,value=3Don \ > -drive > if=3Dpflash,format=3Draw,unit=3D0,readonly=3Don,file=3DBuild/Ovmf3264/DEB= UG_GCC > 5/FV/OVMF_CODE.fd \ > -drive > if=3Dpflash,format=3Draw,unit=3D1,snapshot=3Don,file=3DBuild/Ovmf3264/DEB= UG_GCC > 5/FV/OVMF_VARS.fd \ > -drive id=3Dhdd,if=3Dnone,format=3Dqcow2,snapshot=3Don,file=3Dfed= ora-31-efi- > grub2-x86_64.qcow2 \ > -device virtio-scsi-pci,id=3Dscsi0 \ > -device scsi-hd,drive=3Dhdd,bus=3Dscsi0.0,bootindex=3D1 >=20 > Tested on real AMD Hardware >=20 > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 3 +++ > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 9 ++++++++- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 19 > +++++++++++++++++-- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 20 > ++++++++++++++++++-- > 4 files changed, 46 insertions(+), 5 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h > index 43f6935cf9dc..993360a8a8c1 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h > @@ -2,6 +2,7 @@ > SMM profile internal header file. >=20 > Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
> +Copyright (c) 2020, AMD Incorporated. All rights reserved.
> SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > **/ > @@ -13,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include > > #include #include > +#include > #include >=20 > #include "SmmProfileArch.h" > @@ -99,6 +101,7 @@ extern SMM_S3_RESUME_STATE > *mSmmS3ResumeState; > extern UINTN gSmiExceptionHandlers[]; > extern BOOLEAN mXdSupported; > X86_ASSEMBLY_PATCH_LABEL gPatchXdSupported; > +X86_ASSEMBLY_PATCH_LABEL gPatchMsrIa32MiscEnableSupported; > extern UINTN *mPFEntryCount; > extern UINT64 (*mLastPFEntryValue)[MAX_PF_ENTRY_COUNT= ]; > extern UINT64 *(*mLastPFEntryPointer)[MAX_PF_ENTRY_CO= UNT]; > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > index c47b5573e366..d7ed9ab7a770 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > @@ -2,7 +2,7 @@ > Enable SMM profile. >=20 > Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
- > Copyright (c) 2017, AMD Incorporated. All rights reserved.
> +Copyright (c) 2017 - 2020, AMD Incorporated. All rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > @@ -1015,6 +1015,13 @@ CheckFeatureSupported ( > mXdSupported =3D FALSE; > PatchInstructionX86 (gPatchXdSupported, mXdSupported, 1); > } > + > + if (StandardSignatureIsAuthenticAMD ()) { > + // > + // AMD processors do not support MSR_IA32_MISC_ENABLE > + // > + PatchInstructionX86 (gPatchMsrIa32MiscEnableSupported, FALSE, 1); > + } > } >=20 > if (mBtsSupported) { > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > index f96de9bdeb43..167f5e14dbd4 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm > @@ -1,5 +1,6 @@ > ;-----------------------------------------------------------------------= ------- ; ; > Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> +; Copyright (c) 2020, AMD Incorporated. All rights reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: > @@ -59,6 +60,7 @@ global ASM_PFX(gPatchSmiStack) global > ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global > ASM_PFX(gPatchXdSupported) > +global ASM_PFX(gPatchMsrIa32MiscEnableSupported) > extern ASM_PFX(gSmiHandlerIdtr) >=20 > extern ASM_PFX(mCetSupported) > @@ -153,17 +155,30 @@ ASM_PFX(gPatchSmiCr3): > ASM_PFX(gPatchXdSupported): > cmp al, 0 > jz @SkipXd > + > +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit > + mov al, strict byte 1 ; source operand may be patched > +ASM_PFX(gPatchMsrIa32MiscEnableSupported): > + cmp al, 1 > + jz MsrIa32MiscEnableSupported > + > +; MSR_IA32_MISC_ENABLE not supported > + xor edx, edx > + push edx ; don't try to restore the XD Di= sable bit just before > RSM > + jmp EnableNxe > + > ; > ; Check XD disable bit > ; > +MsrIa32MiscEnableSupported: > mov ecx, MSR_IA32_MISC_ENABLE > rdmsr > push edx ; save MSR_IA32_MISC_ENABLE[63-32= ] > test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] > - jz .5 > + jz EnableNxe > and dx, 0xFFFB ; clear XD Disable bit if it is s= et > wrmsr > -.5: > +EnableNxe: > mov ecx, MSR_EFER > rdmsr > or ax, MSR_EFER_XD ; enable NXE > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > index 8bfba55b5d08..0e154e5db949 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm > @@ -1,5 +1,6 @@ > ;-----------------------------------------------------------------------= ------- ; ; > Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
> +; Copyright (c) 2020, AMD Incorporated. All rights reserved.
> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: > @@ -67,6 +68,7 @@ extern ASM_PFX(CpuSmmDebugExit) global > ASM_PFX(gPatchSmbase) extern ASM_PFX(mXdSupported) global > ASM_PFX(gPatchXdSupported) > +global ASM_PFX(gPatchMsrIa32MiscEnableSupported) > global ASM_PFX(gPatchSmiStack) > global ASM_PFX(gPatchSmiCr3) > global ASM_PFX(gPatch5LevelPagingNeeded) @@ -152,18 +154,32 @@ > SkipEnable5LevelPaging: > ASM_PFX(gPatchXdSupported): > cmp al, 0 > jz @SkipXd > + > +; If MSR_IA32_MISC_ENABLE is supported, clear XD Disable bit > + mov al, strict byte 1 ; source operand may be patched > +ASM_PFX(gPatchMsrIa32MiscEnableSupported): > + cmp al, 1 > + jz MsrIa32MiscEnableSupported > + > +; MSR_IA32_MISC_ENABLE not supported > + sub esp, 4 > + xor rdx, rdx > + push rdx ; don't try to restore the XD Di= sable bit just before > RSM > + jmp EnableNxe > + > ; > ; Check XD disable bit > ; > +MsrIa32MiscEnableSupported: > mov ecx, MSR_IA32_MISC_ENABLE > rdmsr > sub esp, 4 > push rdx ; save MSR_IA32_MISC_ENABLE[63-32= ] > test edx, BIT2 ; MSR_IA32_MISC_ENABLE[34] > - jz .0 > + jz EnableNxe > and dx, 0xFFFB ; clear XD Disable bit if it is s= et > wrmsr > -.0: > +EnableNxe: > mov ecx, MSR_EFER > rdmsr > or ax, MSR_EFER_XD ; enable NXE > -- > 2.27.0