Hi Laszlo,
I have fixed the issue reported by Guomin in below change.
SHA-1: 0060e0a694f3f249c3ec081b0e61287c36f64ebb
* IntelFsp2Pkg/FspSecCore: Use UefiCpuLib.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2825
UefiCpuLib has API InitializeFloatingPointUnits.
Remove internal copy of InitializeFloatingPointUnits
in FspSecCoreM, use UefiCpuLib API.
This change also avoid later potential conflict when
use UefiCpuLib for FspSecCoreM module.
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Thanks,
Eric
From: Laszlo Ersek <lersek@redhat.com>
Sent: Wednesday, June 24, 2020 4:54 PM
To: Kirkendall, Garrett <Garrett.Kirkendall@amd.com>; devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A <hao.a.wu@intel.com>; Jiang, Guomin <guomin.jiang@intel.com>
Subject: Re: [edk2-devel] [PATCH v6 0/4] AMD processor MSR_IA32_MISC_ENABLE
On 06/24/20 03:04, Kirkendall, Garrett wrote:
> [AMD Public Use]
>
> Is there anything else needed from me for this patch at this time?
I think we still have an open question here:
https://edk2.groups.io/g/devel/message/61583
To clarify: I'm not suggesting that we should fix that issue. I'm saying
that we should *understand* Guomin's report enough so we can decide
*whether* this series needs a further update, or not.
If there is no feedback (clarification) from Guomin in a few days, I
think Eric or Ray (the UefiCpuPkg maintainers) should merge v6 -- for
example, on Friday.
Thanks,
Laszlo
>
> GARRETT KIRKENDALL
> SMTS Firmware Engineer | CTE
> 7171 Southwest Parkway, Austin, TX 78735 USA
> AMD facebook | amd.com
>
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Kirkendall, Garrett via groups.io
> Sent: Monday, June 22, 2020 8:18 AM
> To: devel@edk2.groups.io
> Cc: Eric Dong <eric.dong@intel.com>; Ray Ni <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>; Hao A Wu <hao.a.wu@intel.com>
> Subject: [edk2-devel] [PATCH v6 0/4] AMD processor MSR_IA32_MISC_ENABLE
>
> [CAUTION: External Email]
>
> AMD processor does not support MSR_IA32_MISC_ENABLE register. Accessing this register on AMD causes an unhandled exception in SmmEntry.nasm and a subsequent failure to boot since this is too early in SMM path for the exception handler to be loaded.
>
> 1. Prepare PcAtChipsetPkg/PcAtChipsetPkg.dsc to move StandardSignatureIsAuthenticAMD into UefiCpuLib LibraryClass BaseUefiCpuLib in UefiCpuPkg.
>
> 2. To distinguish between AMD and other processors, refactor StandardSignatureIsAuthenticAMD into BaseUefiCpuLib. So there is only one copy in the source.
>
> 3. Skip manipulation of MSR_IA32_MISC_ENABLE register if running on an AMD processor.
>
> Tested on AMD X64 hardware.
> OvmfIa32 and OvmfIa32X64 on Intel hardware.
>
> v1: Move StandardSignatureIsAuthenticAMD. Handle MSR_IA32_MISC_ENABLE
> v2: Incorporate Laszlo's feedback
> v3: Typo, not sent
> v4: Patch in to add UefiCpuLib to PcAtChipsetPkg.dsc
> v5: Patch in to add UefiCpuLib to SourceLevelDebugPkg.dsc
> v6: Hopefully reformat patch when sending????
>
> Garrett Kirkendall (4):
> PcAtChipsetPkg: PcAtChipsetPkg.dsc add UefiCpuLib LibraryClass
> SourceLevelDebugPkg: SourceLevelDebugPkg.dsc add UefiCpuLib
> LibraryClass
> UefiCpuPkg: Move StandardSignatureIsAuthenticAMD to BaseUefiCpuLib
> UefiCpuPkg: PiSmmCpuDxeSmm skip MSR_IA32_MISC_ENABLE manipulation on
> AMD
>
> PcAtChipsetPkg/PcAtChipsetPkg.dsc | 2 ++
> SourceLevelDebugPkg/SourceLevelDebugPkg.dsc | 2 ++
> UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf | 7 ++++
> UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf | 2 ++
> UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf | 2 ++
> UefiCpuPkg/Include/Library/UefiCpuLib.h | 14 ++++++++
> UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 3 ++
> UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c | 38 ++++++++++++++++++++
> UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 25 ++-----------
> UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 25 ++-----------
> UefiCpuPkg/Library/MpInitLib/MpLib.c | 23 ------------
> UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 9 ++++-
> UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 19 ++++++++--
> UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 20 +++++++++--
> 14 files changed, 117 insertions(+), 74 deletions(-) create mode 100644 UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.c
>
> Changes at:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fgkirkendall-amd%2Fedk2%2Ftree%2Fsmmentry_nasm_skip_msr_xd_bit_on_amd_v6&data=02%7C01%7Cgarrett.kirkendall%40amd.com%7C5b2918ff7a2345a5ce7f08d816af8e23%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637284290553548804&sdata=F9ktro2rmOouJYui4jqTFK25TK6l1HBl317RW41QDM4%3D&reserved=0
>
> Pull Request:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Ftianocore%2Fedk2%2Fpull%2F716&data=02%7C01%7Cgarrett.kirkendall%40amd.com%7C5b2918ff7a2345a5ce7f08d816af8e23%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637284290553548804&sdata=FcHQc%2BzJHMAJfSWc9z%2FZ4Bxh5Ur4EnM%2BaIurKJ0iNYU%3D&reserved=0
>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Hao A Wu <hao.a.wu@intel.com>
> Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.com>
>
> --
> 2.27.0
>
>
>
>