Really sorry for the delayed response. I have some questions.

Could you help to provide more information on the issue met that leads to this proposed code change? Also, what tests have been performed for the patch?

The XHCI spec mentions that WPR (bit31 in PORTSC register) only applies to USB3 protocol ports.

Does the “PLS == 6” check ensure the port supports USB3 protocol or additional checks (Port Speed field in PORTSC register + xHCI Supported Protocol Capability) should be added before issuing a Warm Reset?

The proposed code change adds “a eSS.Inactive check and performs a Warm Reset if the check satisfies” after a Hot Reset attempt.

Does the Hot Reset attempt required to resolve the issue? How about the below flow:

if eSS.Inactive

    Warm Reset (WPR=1 in PORTSC)

else

    Hot Reset (PR=1 in PORTSC)

Best Regards,

Hao Wu

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of zhoucheng
Sent: Friday, November 4, 2022 11:16 AM
To: Pedro Falcato <pedro.falcato@gmail.com>; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v1 1/1] MdeModulePkg:Add Warm Reset for Xhc

Hi Pedro:

  //  The description here is the judgment state，we can watch to XHC PORTSC register.
  // according to Xhc Spec 5.4.8 chapter Table39.we can knowleadge more information.
  // We need to pay attention to the PED CCS and PLS bits of the PORTSC register.

+    State = XhcReadOpReg (Xhc, Offset);
+      if ((((State & 0x1e0) >> 5) == 6) && ((State & 3) == 0)) {   
                        ↓                                                   ↓
                  PLS bit                                   PED and CCS bit

//  PLS: Port Link State    PED: Port Enabled/Disabled    CCS: Current Connect Status 
//  If the CCS bit and PED are 0, the device is disconnected and the port is not enabled.
//  If PLS is 6, the controller state machine is abnormal and software intervention is required.



// According to Usb3.2 spec 7.5.2 chapter.Inactive is a state where a link has failed Enhanced SuperSpeed operation.
// The software is required to perform a warm reset operation.
// Therefore, according to the Xhc1.1 spec 5.8 chapter Table39, we can write 1 to its highest bit and perform a hot reset operation to restore the controller.


+        State |= 0x80000000;

   For the value of this block, the above explanation has been made, and the discussion can be continued at the same time.

Thanks!