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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Merged via: PR - https://github.com/tianocore/edk2/pull/3806 Commit - https://github.com/tianocore/edk2/commit/01c2fb0d2260d4de898e4e91e= 48770ffa5510153 Best Regards, Hao Wu > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Wu, Hao > A > Sent: Monday, December 19, 2022 2:16 PM > To: Rhodes, Sean ; devel@edk2.groups.io > Cc: Matt DeVillier ; Ni, Ray = ; > Rhodes, Sean > Subject: Re: [edk2-devel] [PATCH 2/3] MdeModulePkg/XhciDxe/Xhci: Don't > check for invalid PSIV >=20 > Reviewed-by: Hao A Wu >=20 > Best Regards, > Hao Wu >=20 > > -----Original Message----- > > From: Sean Rhodes > > Sent: Friday, December 16, 2022 4:58 PM > > To: devel@edk2.groups.io > > Cc: Matt DeVillier ; Wu, Hao A > > ; Ni, Ray ; Rhodes, Sean > > > > Subject: [PATCH 2/3] MdeModulePkg/XhciDxe/Xhci: Don't check for > > invalid PSIV > > > > From: Matt DeVillier > > > > PSID matching relies on comparing the PSIV against the PortSpeed > > value. This patch stops edk2 from checking for a PSIV of 0, as it is > > not valid; this reduces the number of register access by approximately > > 6 per second. > > > > Cc: Hao A Wu > > Cc: Ray Ni > > Reviewed-by: Sean Rhodes > > Signed-off-by: Matt DeVillier > > Change-Id: If15c55ab66d2e7faa832ce8576d2e5b47157cc9a > > --- > > MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c | 44 > > ++++++++++++++++------------- > > 1 file changed, 25 insertions(+), 19 deletions(-) > > > > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > > b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > > index 15fb49f28f..8dd7a8fbb7 100644 > > --- a/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c > > @@ -371,6 +371,7 @@ XhcGetRootHubPortStatus ( > > UINT32 TotalPort; > > > > UINTN Index; > > > > UINTN MapSize; > > > > + UINT8 PortSpeed; > > > > EFI_STATUS Status; > > > > USB_DEV_ROUTE ParentRouteChart; > > > > EFI_TPL OldTpl; > > > > @@ -397,32 +398,37 @@ XhcGetRootHubPortStatus ( > > > > > > State =3D XhcReadOpReg (Xhc, Offset); > > > > > > > > + PortSpeed =3D (State & XHC_PORTSC_PS) >> 10; > > > > + > > > > // > > > > // According to XHCI 1.1 spec November 2017, > > > > // Section 7.2 xHCI Support Protocol Capability > > > > // > > > > - PortStatus->PortStatus =3D XhcCheckUsbPortSpeedUsedPsic (Xhc, ((Stat= e > > & > > XHC_PORTSC_PS) >> 10)); > > > > - if (PortStatus->PortStatus =3D=3D 0) { > > > > - // > > > > - // According to XHCI 1.1 spec November 2017, > > > > - // bit 10~13 of the root port status register identifies the speed= of the > > attached device. > > > > - // > > > > - switch ((State & XHC_PORTSC_PS) >> 10) { > > > > - case 2: > > > > - PortStatus->PortStatus |=3D USB_PORT_STAT_LOW_SPEED; > > > > - break; > > > > + if (PortSpeed > 0) { > > > > + PortStatus->PortStatus =3D XhcCheckUsbPortSpeedUsedPsic (Xhc, > > PortSpeed); > > > > + // If no match found in ext cap reg, fall back to PORTSC > > > > + if (PortStatus->PortStatus =3D=3D 0) { > > > > + // > > > > + // According to XHCI 1.1 spec November 2017, > > > > + // bit 10~13 of the root port status register identifies the > > + speed of the > > attached device. > > > > + // > > > > + switch (PortSpeed) { > > > > + case 2: > > > > + PortStatus->PortStatus |=3D USB_PORT_STAT_LOW_SPEED; > > > > + break; > > > > > > > > - case 3: > > > > - PortStatus->PortStatus |=3D USB_PORT_STAT_HIGH_SPEED; > > > > - break; > > > > + case 3: > > > > + PortStatus->PortStatus |=3D USB_PORT_STAT_HIGH_SPEED; > > > > + break; > > > > > > > > - case 4: > > > > - case 5: > > > > - PortStatus->PortStatus |=3D USB_PORT_STAT_SUPER_SPEED; > > > > - break; > > > > + case 4: > > > > + case 5: > > > > + PortStatus->PortStatus |=3D USB_PORT_STAT_SUPER_SPEED; > > > > + break; > > > > > > > > - default: > > > > - break; > > > > + default: > > > > + break; > > > > + } > > > > } > > > > } > > > > > > > > -- > > 2.37.2 >=20 >=20 >=20 >=20 >=20