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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,hao.a.wu@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: DTZq2UNep3hxZbwQVGbHp2Iwx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b="o6/aJBeN"; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Hao A Wu Best Regards, Hao Wu > -----Original Message----- > From: Cheng, Gao > Sent: Tuesday, September 26, 2023 4:25 PM > To: devel@edk2.groups.io > Cc: Cheng, Gao ; Wu, Hao A ; > Ni, Ray ; Wang, Jian J ; Gao, > Liming > Subject: [PATCH v2] MdeModulePkg/Xhci: Skip size round up for TRB during > address translation >=20 > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4560 >=20 >=20 >=20 > TRB Template is 16 bytes. When boundary checking is 64 bytes for xHCI >=20 > device/host memory address, it may exceed xHCI host memory pool and >=20 > cause unwanted DXE_ASSERT. Introduce a new input parameter to indicate >=20 > whether to enforce 64byte size alignment and round up. For TRB case, >=20 > should set it to FALSE to skip the size round up. >=20 >=20 >=20 > Signed-off-by: Gao Cheng >=20 > Cc: Hao A Wu >=20 > Cc: Ray Ni >=20 > Cc: Jian J Wang >=20 > Cc: Liming Gao >=20 > --- >=20 > MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c | 24 ++++++++--- >=20 > MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h | 8 +++- >=20 > MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 54 +++++++++++++----------- >=20 > MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c | 24 ++++++++--- >=20 > MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h | 8 +++- >=20 > MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c | 48 +++++++++++---------- >=20 > 6 files changed, 103 insertions(+), 63 deletions(-) >=20 >=20 >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c > b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c >=20 > index d0ad1582e4..b54187ec22 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c >=20 > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.c >=20 > @@ -226,6 +226,7 @@ UsbHcAllocMemFromBlock ( >=20 > @param Pool The memory pool of the host controller. >=20 > @param Mem The pointer to host memory. >=20 > @param Size The size of the memory region. >=20 > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. >=20 >=20 >=20 > @return The pci memory address >=20 >=20 >=20 > @@ -234,7 +235,8 @@ EFI_PHYSICAL_ADDRESS >=20 > UsbHcGetPciAddrForHostAddr ( >=20 > IN USBHC_MEM_POOL *Pool, >=20 > IN VOID *Mem, >=20 > - IN UINTN Size >=20 > + IN UINTN Size, >=20 > + IN BOOLEAN Alignment >=20 > ) >=20 > { >=20 > USBHC_MEM_BLOCK *Head; >=20 > @@ -243,8 +245,12 @@ UsbHcGetPciAddrForHostAddr ( >=20 > EFI_PHYSICAL_ADDRESS PhyAddr; >=20 > UINTN Offset; >=20 >=20 >=20 > - Head =3D Pool->Head; >=20 > - AllocSize =3D USBHC_MEM_ROUND (Size); >=20 > + Head =3D Pool->Head; >=20 > + if (Alignment) { >=20 > + AllocSize =3D USBHC_MEM_ROUND (Size); >=20 > + } else { >=20 > + AllocSize =3D Size; >=20 > + } >=20 >=20 >=20 > if (Mem =3D=3D NULL) { >=20 > return 0; >=20 > @@ -275,6 +281,7 @@ UsbHcGetPciAddrForHostAddr ( >=20 > @param Pool The memory pool of the host controller. >=20 > @param Mem The pointer to pci memory. >=20 > @param Size The size of the memory region. >=20 > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. >=20 >=20 >=20 > @return The host memory address >=20 >=20 >=20 > @@ -283,7 +290,8 @@ EFI_PHYSICAL_ADDRESS >=20 > UsbHcGetHostAddrForPciAddr ( >=20 > IN USBHC_MEM_POOL *Pool, >=20 > IN VOID *Mem, >=20 > - IN UINTN Size >=20 > + IN UINTN Size, >=20 > + IN BOOLEAN Alignment >=20 > ) >=20 > { >=20 > USBHC_MEM_BLOCK *Head; >=20 > @@ -292,8 +300,12 @@ UsbHcGetHostAddrForPciAddr ( >=20 > EFI_PHYSICAL_ADDRESS HostAddr; >=20 > UINTN Offset; >=20 >=20 >=20 > - Head =3D Pool->Head; >=20 > - AllocSize =3D USBHC_MEM_ROUND (Size); >=20 > + Head =3D Pool->Head; >=20 > + if (Alignment) { >=20 > + AllocSize =3D USBHC_MEM_ROUND (Size); >=20 > + } else { >=20 > + AllocSize =3D Size; >=20 > + } >=20 >=20 >=20 > if (Mem =3D=3D NULL) { >=20 > return 0; >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h > b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h >=20 > index c85b0b919f..b21bf9da3e 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h >=20 > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/UsbHcMem.h >=20 > @@ -129,6 +129,7 @@ UsbHcFreeMem ( >=20 > @param Pool The memory pool of the host controller. >=20 > @param Mem The pointer to host memory. >=20 > @param Size The size of the memory region. >=20 > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. >=20 >=20 >=20 > @return The pci memory address >=20 >=20 >=20 > @@ -137,7 +138,8 @@ EFI_PHYSICAL_ADDRESS >=20 > UsbHcGetPciAddrForHostAddr ( >=20 > IN USBHC_MEM_POOL *Pool, >=20 > IN VOID *Mem, >=20 > - IN UINTN Size >=20 > + IN UINTN Size, >=20 > + IN BOOLEAN Alignment >=20 > ); >=20 >=20 >=20 > /** >=20 > @@ -146,6 +148,7 @@ UsbHcGetPciAddrForHostAddr ( >=20 > @param Pool The memory pool of the host controller. >=20 > @param Mem The pointer to pci memory. >=20 > @param Size The size of the memory region. >=20 > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. >=20 >=20 >=20 > @return The host memory address >=20 >=20 >=20 > @@ -154,7 +157,8 @@ EFI_PHYSICAL_ADDRESS >=20 > UsbHcGetHostAddrForPciAddr ( >=20 > IN USBHC_MEM_POOL *Pool, >=20 > IN VOID *Mem, >=20 > - IN UINTN Size >=20 > + IN UINTN Size, >=20 > + IN BOOLEAN Alignment >=20 > ); >=20 >=20 >=20 > /** >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c > b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c >=20 > index 53421e64a8..c2be171780 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c >=20 > +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c >=20 > @@ -588,7 +588,7 @@ XhcInitSched ( >=20 > // Some 3rd party XHCI external cards don't support single 64-bytes wi= dth > register access, >=20 > // So divide it to two 32-bytes width register access. >=20 > // >=20 > - DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries)= ; >=20 > + DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Entries, > TRUE); >=20 > XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT (DcbaaPhy)); >=20 > XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT > (DcbaaPhy)); >=20 >=20 >=20 > @@ -607,7 +607,7 @@ XhcInitSched ( >=20 > // So we set RCS as inverted PCS init value to let Command Ring empty >=20 > // >=20 > CmdRing =3D (UINT64)(UINTN)Xhc->CmdRing.RingSeg0; >=20 > - CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID > *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER); >=20 > + CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, (VOID > *)(UINTN)CmdRing, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, > TRUE); >=20 > ASSERT ((CmdRingPhy & 0x3F) =3D=3D 0); >=20 > CmdRingPhy |=3D XHC_CRCR_RCS; >=20 > // >=20 > @@ -809,7 +809,7 @@ CreateEventRing ( >=20 > EventRing->EventRingDequeue =3D (TRB_TEMPLATE *)EventRing- > >EventRingSeg0; >=20 > EventRing->EventRingEnqueue =3D (TRB_TEMPLATE *)EventRing- > >EventRingSeg0; >=20 >=20 >=20 > - DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size); >=20 > + DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, > TRUE); >=20 >=20 >=20 > // >=20 > // Software maintains an Event Ring Consumer Cycle State (CCS) bit, > initializing it to '1' >=20 > @@ -829,7 +829,7 @@ CreateEventRing ( >=20 > ERSTBase->PtrHi =3D XHC_HIGH_32BIT (DequeuePhy); >=20 > ERSTBase->RingTrbSize =3D EVENT_RING_TRB_NUMBER; >=20 >=20 >=20 > - ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size); >=20 > + ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, ERSTBase, Size, > TRUE); >=20 >=20 >=20 > // >=20 > // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) regi= ster > (5.5.2.3.1) >=20 > @@ -913,7 +913,7 @@ CreateTransferRing ( >=20 > // >=20 > EndTrb =3D (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (T= rbNum > - 1)); >=20 > EndTrb->Type =3D TRB_TYPE_LINK; >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeo= f > (TRB_TEMPLATE) * TrbNum); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeo= f > (TRB_TEMPLATE) * TrbNum, TRUE); >=20 > EndTrb->PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > EndTrb->PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > // >=20 > @@ -1045,7 +1045,7 @@ IsTransferRingTrb ( >=20 > if (CheckedTrb->Type =3D=3D TRB_TYPE_LINK) { >=20 > LinkTrb =3D (LINK_TRB *)CheckedTrb; >=20 > PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 > ((UINT64)LinkTrb->PtrHi, 32)); >=20 > - CheckedTrb =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr > (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE)); >=20 > + CheckedTrb =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr > (Xhc->MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); >=20 > ASSERT (CheckedTrb =3D=3D Urb->Ring->RingSeg0); >=20 > } >=20 > } >=20 > @@ -1154,7 +1154,7 @@ XhcCheckUrbResult ( >=20 > // Need convert pci device address to host address >=20 > // >=20 > PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 > ((UINT64)EvtTrb->TRBPtrHi, 32)); >=20 > - TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc- > >MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE)); >=20 > + TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc- > >MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); >=20 >=20 >=20 > // >=20 > // Update the status of URB including the pending URB, the URB that = is > currently checked, >=20 > @@ -1259,7 +1259,7 @@ EXIT: >=20 > High =3D XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4); >=20 > XhcDequeue =3D (UINT64)(LShiftU64 ((UINT64)High, 32) | Low); >=20 >=20 >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE), FALSE); >=20 >=20 >=20 > if ((XhcDequeue & (~0x0F)) !=3D (PhyAddr & (~0x0F))) { >=20 > // >=20 > @@ -2280,7 +2280,8 @@ XhcInitializeDeviceSlot ( >=20 > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( >=20 > Xhc->MemPool, >=20 > ((TRANSFER_RING *)(UINTN)Xhc- > >UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, >=20 > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER >=20 > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, >=20 > + TRUE >=20 > ); >=20 > InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; >=20 > InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > @@ -2298,7 +2299,7 @@ XhcInitializeDeviceSlot ( >=20 > // 7) Load the appropriate (Device Slot ID) entry in the Device Contex= t Base > Address Array (5.4.6) with >=20 > // a pointer to the Output Device Context data structure (6.2.1). >=20 > // >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, > sizeof (DEVICE_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, > sizeof (DEVICE_CONTEXT), TRUE); >=20 > // >=20 > // Fill DCBAA with PCI device address >=20 > // >=20 > @@ -2313,7 +2314,7 @@ XhcInitializeDeviceSlot ( >=20 > // >=20 > gBS->Stall (XHC_RESET_RECOVERY_DELAY); >=20 > ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE); >=20 > CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbAddr.CycleBit =3D 1; >=20 > @@ -2496,7 +2497,8 @@ XhcInitializeDeviceSlot64 ( >=20 > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( >=20 > Xhc->MemPool, >=20 > ((TRANSFER_RING *)(UINTN)Xhc- > >UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, >=20 > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER >=20 > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, >=20 > + TRUE >=20 > ); >=20 > InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; >=20 > InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > @@ -2514,7 +2516,7 @@ XhcInitializeDeviceSlot64 ( >=20 > // 7) Load the appropriate (Device Slot ID) entry in the Device Contex= t Base > Address Array (5.4.6) with >=20 > // a pointer to the Output Device Context data structure (6.2.1). >=20 > // >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, > sizeof (DEVICE_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, > sizeof (DEVICE_CONTEXT_64), TRUE); >=20 > // >=20 > // Fill DCBAA with PCI device address >=20 > // >=20 > @@ -2529,7 +2531,7 @@ XhcInitializeDeviceSlot64 ( >=20 > // >=20 > gBS->Stall (XHC_RESET_RECOVERY_DELAY); >=20 > ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64), TRUE); >=20 > CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbAddr.CycleBit =3D 1; >=20 > @@ -2964,7 +2966,8 @@ XhcInitializeEndpointContext ( >=20 > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( >=20 > Xhc->MemPool, >=20 > ((TRANSFER_RING *)(UINTN)Xhc- > >UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, >=20 > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER >=20 > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, >=20 > + TRUE >=20 > ); >=20 > PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); >=20 > PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER_R= ING > *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])- > >RingPCS; >=20 > @@ -3166,7 +3169,8 @@ XhcInitializeEndpointContext64 ( >=20 > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( >=20 > Xhc->MemPool, >=20 > ((TRANSFER_RING *)(UINTN)Xhc- > >UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, >=20 > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER >=20 > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, >=20 > + TRUE >=20 > ); >=20 > PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); >=20 > PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER_R= ING > *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])- > >RingPCS; >=20 > @@ -3248,7 +3252,7 @@ XhcSetConfigCmd ( >=20 > // configure endpoint >=20 > // >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > @@ -3339,7 +3343,7 @@ XhcSetConfigCmd64 ( >=20 > // configure endpoint >=20 > // >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > @@ -3513,7 +3517,7 @@ XhcSetTrDequeuePointer ( >=20 > // Send stop endpoint command to transit Endpoint from running to stop > state >=20 > // >=20 > ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb= - > >Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb= - > >Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); >=20 > CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS; >=20 > CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdSetTRDeq.CycleBit =3D 1; >=20 > @@ -3713,7 +3717,7 @@ XhcSetInterface ( >=20 > // 5) Issue and successfully complete a Configure Endpoint Command. >=20 > // >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > @@ -3919,7 +3923,7 @@ XhcSetInterface64 ( >=20 > // 5) Issue and successfully complete a Configure Endpoint Command. >=20 > // >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > @@ -3986,7 +3990,7 @@ XhcEvaluateContext ( >=20 > InputContext->EP[0].EPState =3D 0; >=20 >=20 >=20 > ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT), TRUE); >=20 > CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbEvalu.CycleBit =3D 1; >=20 > @@ -4047,7 +4051,7 @@ XhcEvaluateContext64 ( >=20 > InputContext->EP[0].EPState =3D 0; >=20 >=20 >=20 > ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); >=20 > CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbEvalu.CycleBit =3D 1; >=20 > @@ -4116,7 +4120,7 @@ XhcConfigHubContext ( >=20 > InputContext->Slot.MTT =3D MTT; >=20 >=20 >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > @@ -4185,7 +4189,7 @@ XhcConfigHubContext64 ( >=20 > InputContext->Slot.MTT =3D MTT; >=20 >=20 >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c > b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c >=20 > index e779a31138..88db5fe46e 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c >=20 > +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.c >=20 > @@ -190,6 +190,7 @@ UsbHcAllocMemFromBlock ( >=20 > @param Pool The memory pool of the host controller. >=20 > @param Mem The pointer to host memory. >=20 > @param Size The size of the memory region. >=20 > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. >=20 >=20 >=20 > @return The pci memory address >=20 >=20 >=20 > @@ -198,7 +199,8 @@ EFI_PHYSICAL_ADDRESS >=20 > UsbHcGetPciAddrForHostAddr ( >=20 > IN USBHC_MEM_POOL *Pool, >=20 > IN VOID *Mem, >=20 > - IN UINTN Size >=20 > + IN UINTN Size, >=20 > + IN BOOLEAN Alignment >=20 > ) >=20 > { >=20 > USBHC_MEM_BLOCK *Head; >=20 > @@ -207,8 +209,12 @@ UsbHcGetPciAddrForHostAddr ( >=20 > EFI_PHYSICAL_ADDRESS PhyAddr; >=20 > UINTN Offset; >=20 >=20 >=20 > - Head =3D Pool->Head; >=20 > - AllocSize =3D USBHC_MEM_ROUND (Size); >=20 > + Head =3D Pool->Head; >=20 > + if (Alignment) { >=20 > + AllocSize =3D USBHC_MEM_ROUND (Size); >=20 > + } else { >=20 > + AllocSize =3D Size; >=20 > + } >=20 >=20 >=20 > if (Mem =3D=3D NULL) { >=20 > return 0; >=20 > @@ -239,6 +245,7 @@ UsbHcGetPciAddrForHostAddr ( >=20 > @param Pool The memory pool of the host controller. >=20 > @param Mem The pointer to pci memory. >=20 > @param Size The size of the memory region. >=20 > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. >=20 >=20 >=20 > @return The host memory address >=20 >=20 >=20 > @@ -247,7 +254,8 @@ EFI_PHYSICAL_ADDRESS >=20 > UsbHcGetHostAddrForPciAddr ( >=20 > IN USBHC_MEM_POOL *Pool, >=20 > IN VOID *Mem, >=20 > - IN UINTN Size >=20 > + IN UINTN Size, >=20 > + IN BOOLEAN Alignment >=20 > ) >=20 > { >=20 > USBHC_MEM_BLOCK *Head; >=20 > @@ -256,8 +264,12 @@ UsbHcGetHostAddrForPciAddr ( >=20 > EFI_PHYSICAL_ADDRESS HostAddr; >=20 > UINTN Offset; >=20 >=20 >=20 > - Head =3D Pool->Head; >=20 > - AllocSize =3D USBHC_MEM_ROUND (Size); >=20 > + Head =3D Pool->Head; >=20 > + if (Alignment) { >=20 > + AllocSize =3D USBHC_MEM_ROUND (Size); >=20 > + } else { >=20 > + AllocSize =3D Size; >=20 > + } >=20 >=20 >=20 > if (Mem =3D=3D NULL) { >=20 > return 0; >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h > b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h >=20 > index 2b4c8b19fc..8f760e084e 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h >=20 > +++ b/MdeModulePkg/Bus/Pci/XhciPei/UsbHcMem.h >=20 > @@ -68,6 +68,7 @@ typedef struct _USBHC_MEM_POOL { >=20 > @param Pool The memory pool of the host controller. >=20 > @param Mem The pointer to host memory. >=20 > @param Size The size of the memory region. >=20 > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. >=20 >=20 >=20 > @return The pci memory address >=20 >=20 >=20 > @@ -76,7 +77,8 @@ EFI_PHYSICAL_ADDRESS >=20 > UsbHcGetPciAddrForHostAddr ( >=20 > IN USBHC_MEM_POOL *Pool, >=20 > IN VOID *Mem, >=20 > - IN UINTN Size >=20 > + IN UINTN Size, >=20 > + IN BOOLEAN Alignment >=20 > ); >=20 >=20 >=20 > /** >=20 > @@ -85,6 +87,7 @@ UsbHcGetPciAddrForHostAddr ( >=20 > @param Pool The memory pool of the host controller. >=20 > @param Mem The pointer to pci memory. >=20 > @param Size The size of the memory region. >=20 > + @param Alignment Alignment the size to USBHC_MEM_UNIT bytes. >=20 >=20 >=20 > @return The host memory address >=20 >=20 >=20 > @@ -93,7 +96,8 @@ EFI_PHYSICAL_ADDRESS >=20 > UsbHcGetHostAddrForPciAddr ( >=20 > IN USBHC_MEM_POOL *Pool, >=20 > IN VOID *Mem, >=20 > - IN UINTN Size >=20 > + IN UINTN Size, >=20 > + IN BOOLEAN Alignment >=20 > ); >=20 >=20 >=20 > /** >=20 > diff --git a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c > b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c >=20 > index 8400c90f7a..53272f62dd 100644 >=20 > --- a/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c >=20 > +++ b/MdeModulePkg/Bus/Pci/XhciPei/XhciSched.c >=20 > @@ -675,7 +675,7 @@ XhcPeiCheckUrbResult ( >=20 > // Need convert pci device address to host address >=20 > // >=20 > PhyAddr =3D (EFI_PHYSICAL_ADDRESS)(EvtTrb->TRBPtrLo | LShiftU64 > ((UINT64)EvtTrb->TRBPtrHi, 32)); >=20 > - TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc- > >MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE)); >=20 > + TRBPtr =3D (TRB_TEMPLATE *)(UINTN)UsbHcGetHostAddrForPciAddr (Xhc- > >MemPool, (VOID *)(UINTN)PhyAddr, sizeof (TRB_TEMPLATE), FALSE); >=20 >=20 >=20 > // >=20 > // Update the status of Urb according to the finished event regardle= ss of > whether >=20 > @@ -766,7 +766,7 @@ EXIT: >=20 > High =3D XhcPeiReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4); >=20 > XhcDequeue =3D (UINT64)(LShiftU64 ((UINT64)High, 32) | Low); >=20 >=20 >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >EventRing.EventRingDequeue, sizeof (TRB_TEMPLATE), FALSE); >=20 >=20 >=20 > if ((XhcDequeue & (~0x0F)) !=3D (PhyAddr & (~0x0F))) { >=20 > // >=20 > @@ -1213,7 +1213,8 @@ XhcPeiInitializeDeviceSlot ( >=20 > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( >=20 > Xhc->MemPool, >=20 > ((TRANSFER_RING *)(UINTN)Xhc- > >UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, >=20 > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER >=20 > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, >=20 > + TRUE >=20 > ); >=20 > InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; >=20 > InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > @@ -1231,7 +1232,7 @@ XhcPeiInitializeDeviceSlot ( >=20 > // 7) Load the appropriate (Device Slot ID) entry in the Device Contex= t Base > Address Array (5.4.6) with >=20 > // a pointer to the Output Device Context data structure (6.2.1). >=20 > // >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, > sizeof (DEVICE_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, > sizeof (DEVICE_CONTEXT), TRUE); >=20 > // >=20 > // Fill DCBAA with PCI device address >=20 > // >=20 > @@ -1246,7 +1247,7 @@ XhcPeiInitializeDeviceSlot ( >=20 > // >=20 > MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); >=20 > ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT), TRUE); >=20 > CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbAddr.CycleBit =3D 1; >=20 > @@ -1427,7 +1428,8 @@ XhcPeiInitializeDeviceSlot64 ( >=20 > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( >=20 > Xhc->MemPool, >=20 > ((TRANSFER_RING *)(UINTN)Xhc- > >UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0, >=20 > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER >=20 > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, >=20 > + TRUE >=20 > ); >=20 > InputContext->EP[0].PtrLo =3D XHC_LOW_32BIT (PhyAddr) | BIT0; >=20 > InputContext->EP[0].PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > @@ -1445,7 +1447,7 @@ XhcPeiInitializeDeviceSlot64 ( >=20 > // 7) Load the appropriate (Device Slot ID) entry in the Device Contex= t Base > Address Array (5.4.6) with >=20 > // a pointer to the Output Device Context data structure (6.2.1). >=20 > // >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, > sizeof (DEVICE_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, OutputContext, > sizeof (DEVICE_CONTEXT_64), TRUE); >=20 > // >=20 > // Fill DCBAA with PCI device address >=20 > // >=20 > @@ -1460,7 +1462,7 @@ XhcPeiInitializeDeviceSlot64 ( >=20 > // >=20 > MicroSecondDelay (XHC_RESET_RECOVERY_DELAY); >=20 > ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >UsbDevContext[SlotId].InputContext, sizeof (INPUT_CONTEXT_64), TRUE); >=20 > CmdTrbAddr.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbAddr.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbAddr.CycleBit =3D 1; >=20 > @@ -1882,7 +1884,8 @@ XhcPeiSetConfigCmd ( >=20 > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( >=20 > Xhc->MemPool, >=20 > ((TRANSFER_RING *)(UINTN)Xhc- > >UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, >=20 > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER >=20 > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, >=20 > + TRUE >=20 > ); >=20 > PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); >=20 > PhyAddr |=3D (EFI_PHYSICAL_ADDRESS)((TRANSFER= _RING > *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])- > >RingPCS; >=20 > @@ -1901,7 +1904,7 @@ XhcPeiSetConfigCmd ( >=20 > // configure endpoint >=20 > // >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > @@ -2108,7 +2111,8 @@ XhcPeiSetConfigCmd64 ( >=20 > PhyAddr =3D UsbHcGetPciAddrForHostAddr ( >=20 > Xhc->MemPool, >=20 > ((TRANSFER_RING *)(UINTN)Xhc- > >UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0, >=20 > - sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER >=20 > + sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER, >=20 > + TRUE >=20 > ); >=20 >=20 >=20 > PhyAddr &=3D ~((EFI_PHYSICAL_ADDRESS)0x0F); >=20 > @@ -2129,7 +2133,7 @@ XhcPeiSetConfigCmd64 ( >=20 > // configure endpoint >=20 > // >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > @@ -2184,7 +2188,7 @@ XhcPeiEvaluateContext ( >=20 > InputContext->EP[0].MaxPacketSize =3D MaxPacketSize; >=20 >=20 >=20 > ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT), TRUE); >=20 > CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbEvalu.CycleBit =3D 1; >=20 > @@ -2239,7 +2243,7 @@ XhcPeiEvaluateContext64 ( >=20 > InputContext->EP[0].MaxPacketSize =3D MaxPacketSize; >=20 >=20 >=20 > ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); >=20 > CmdTrbEvalu.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbEvalu.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbEvalu.CycleBit =3D 1; >=20 > @@ -2308,7 +2312,7 @@ XhcPeiConfigHubContext ( >=20 > InputContext->Slot.MTT =3D MTT; >=20 >=20 >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > @@ -2377,7 +2381,7 @@ XhcPeiConfigHubContext64 ( >=20 > InputContext->Slot.MTT =3D MTT; >=20 >=20 >=20 > ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, > InputContext, sizeof (INPUT_CONTEXT_64), TRUE); >=20 > CmdTrbCfgEP.PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdTrbCfgEP.CycleBit =3D 1; >=20 > @@ -2522,7 +2526,7 @@ XhcPeiSetTrDequeuePointer ( >=20 > // Send stop endpoint command to transit Endpoint from running to stop > state >=20 > // >=20 > ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq)); >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb= - > >Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER)); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Urb= - > >Ring->RingEnqueue, sizeof (CMD_SET_TR_DEQ_POINTER), TRUE); >=20 > CmdSetTRDeq.PtrLo =3D XHC_LOW_32BIT (PhyAddr) | Urb->Ring->RingPCS; >=20 > CmdSetTRDeq.PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > CmdSetTRDeq.CycleBit =3D 1; >=20 > @@ -2682,7 +2686,7 @@ XhcPeiCreateEventRing ( >=20 > ASSERT (((UINTN)Buf & 0x3F) =3D=3D 0); >=20 > ZeroMem (Buf, Size); >=20 >=20 >=20 > - DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size); >=20 > + DequeuePhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, > TRUE); >=20 >=20 >=20 > EventRing->EventRingSeg0 =3D Buf; >=20 > EventRing->TrbNumber =3D EVENT_RING_TRB_NUMBER; >=20 > @@ -2707,7 +2711,7 @@ XhcPeiCreateEventRing ( >=20 > ERSTBase->PtrHi =3D XHC_HIGH_32BIT (DequeuePhy); >=20 > ERSTBase->RingTrbSize =3D EVENT_RING_TRB_NUMBER; >=20 >=20 >=20 > - ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size); >=20 > + ERSTPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, Size, TRUE)= ; >=20 >=20 >=20 > // >=20 > // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) regi= ster > (5.5.2.3.1) >=20 > @@ -2855,7 +2859,7 @@ XhcPeiCreateTransferRing ( >=20 > // >=20 > EndTrb =3D (LINK_TRB *)((UINTN)Buf + sizeof (TRB_TEMPLATE) * (T= rbNum > - 1)); >=20 > EndTrb->Type =3D TRB_TYPE_LINK; >=20 > - PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeo= f > (TRB_TEMPLATE) * TrbNum); >=20 > + PhyAddr =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Buf, sizeo= f > (TRB_TEMPLATE) * TrbNum, TRUE); >=20 > EndTrb->PtrLo =3D XHC_LOW_32BIT (PhyAddr); >=20 > EndTrb->PtrHi =3D XHC_HIGH_32BIT (PhyAddr); >=20 > // >=20 > @@ -2988,7 +2992,7 @@ XhcPeiInitSched ( >=20 > // Some 3rd party XHCI external cards don't support single 64-bytes wi= dth > register access, >=20 > // So divide it to two 32-bytes width register access. >=20 > // >=20 > - DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size); >=20 > + DcbaaPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Dcbaa, Size, > TRUE); >=20 > XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT > (DcbaaPhy)); >=20 > XhcPeiWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT > (DcbaaPhy)); >=20 >=20 >=20 > @@ -3006,7 +3010,7 @@ XhcPeiInitSched ( >=20 > // Transfer Ring it checks for a Cycle bit transition. If a transition= detected, > the ring is empty. >=20 > // So we set RCS as inverted PCS init value to let Command Ring empty >=20 > // >=20 > - CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER); >=20 > + CmdRingPhy =3D UsbHcGetPciAddrForHostAddr (Xhc->MemPool, Xhc- > >CmdRing.RingSeg0, sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER, > TRUE); >=20 > ASSERT ((CmdRingPhy & 0x3F) =3D=3D 0); >=20 > CmdRingPhy |=3D XHC_CRCR_RCS; >=20 > // >=20 > -- >=20 > 2.42.0.windows.2 >=20 >=20 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109097): https://edk2.groups.io/g/devel/message/109097 Mute This Topic: https://groups.io/mt/101591675/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-