* [PATCH] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size support both 32/64 bit
@ 2021-10-22 9:15 ian.chiu
2021-10-26 6:35 ` Wu, Hao A
0 siblings, 1 reply; 2+ messages in thread
From: ian.chiu @ 2021-10-22 9:15 UTC (permalink / raw)
To: devel; +Cc: Ian Chiu, Ian Chiu, Maggie Chu, Ray Ni, Hao A Wu
From: Ian Chiu <Ian.chiu@intel.com>
https://bugzilla.tianocore.org/show_bug.cgi?id=3703
MMIO base address size will overflow while finding two or more Host
controller in the system. Correct it and support 32 and 64 bits address
space.
Signed-off-by: Ian Chiu <ian.chiu@intel.com>
Cc: Maggie Chu <maggie.chu@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
---
MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | 37 ++++++++++++++++++++++++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
index 447a05b5b2..69a19c60a2 100644
--- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
+++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
@@ -76,6 +76,7 @@ InitializeUfsHcPeim (
UINT16 Device;
UINT16 Function;
UINT32 Size;
+ UINT64 MmioSize;
UINT8 SubClass;
UINT8 BaseClass;
UFS_HC_PEI_PRIVATE_DATA *Private;
@@ -119,16 +120,48 @@ InitializeUfsHcPeim (
PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF);
Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET));
+
+ switch (Size & 0x07) {
+ case 0x0:
+ //
+ // Memory space: anywhere in 32 bit address space
+ //
+ MmioSize = (~(Size & 0xFFFFFFF0)) + 1;
+ break;
+ case 0x4:
+ //
+ // Memory space: anywhere in 64 bit address space
+ //
+ MmioSize = Size & 0xFFFFFFF0;
+
+ //
+ // Fix the length to support some spefic 64 bit BAR
+ //
+ Size |= ((UINT32)(-1) << HighBitSet32 (Size));
+
+ //
+ // Calculate the size of 64bit bar
+ //
+ MmioSize |= LShiftU64 ((UINT64) Size, 32);
+ MmioSize = (~(MmioSize)) + 1;
+ break;
+ default:
+ //
+ // Unknown BAR type
+ //
+ ASSERT (FALSE);
+ continue;
+ };
//
// Assign resource to the Ufs Pci host controller's MMIO BAR.
// Enable the Ufs Pci host controller by setting BME and MSE bits of PCI_CMD register.
//
- PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs));
+ PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32 (PcdUfsPciHostControllerMmioBase) + MmioSize * Private->TotalUfsHcs));
PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER | EFI_PCI_COMMAND_MEMORY_SPACE));
//
// Record the allocated Mmio base address.
//
- Private->UfsHcPciAddr[Private->TotalUfsHcs] = PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs;
+ Private->UfsHcPciAddr[Private->TotalUfsHcs] = PcdGet32 (PcdUfsPciHostControllerMmioBase) + (UINTN) MmioSize * Private->TotalUfsHcs;
Private->TotalUfsHcs++;
ASSERT (Private->TotalUfsHcs < MAX_UFS_HCS);
}
--
2.16.2.windows.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size support both 32/64 bit
2021-10-22 9:15 [PATCH] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size support both 32/64 bit ian.chiu
@ 2021-10-26 6:35 ` Wu, Hao A
0 siblings, 0 replies; 2+ messages in thread
From: Wu, Hao A @ 2021-10-26 6:35 UTC (permalink / raw)
To: Chiu, Ian, devel@edk2.groups.io; +Cc: Chu, Maggie, Ni, Ray
> -----Original Message-----
> From: Chiu, Ian <Ian.chiu@intel.com>
> Sent: Friday, October 22, 2021 5:15 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Ian <Ian.chiu@intel.com>; Chiu, Ian <Ian.chiu@intel.com>; Chu,
> Maggie <maggie.chu@intel.com>; Ni, Ray <ray.ni@intel.com>; Wu, Hao A
> <hao.a.wu@intel.com>
> Subject: [PATCH] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size
> support both 32/64 bit
>
> From: Ian Chiu <Ian.chiu@intel.com>
>
> https://bugzilla.tianocore.org/show_bug.cgi?id=3703
> MMIO base address size will overflow while finding two or more Host
> controller in the system. Correct it and support 32 and 64 bits address
> space.
Could you help to provide the information on what tests have been performed for this patch? Thanks.
Some additional inline comments below:
>
> Signed-off-by: Ian Chiu <ian.chiu@intel.com>
> Cc: Maggie Chu <maggie.chu@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Hao A Wu <hao.a.wu@intel.com>
> ---
> MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | 37
> ++++++++++++++++++++++++--
> 1 file changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
> b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
> index 447a05b5b2..69a19c60a2 100644
> --- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
> +++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c
> @@ -76,6 +76,7 @@ InitializeUfsHcPeim (
> UINT16 Device;
>
> UINT16 Function;
>
> UINT32 Size;
>
> + UINT64 MmioSize;
>
> UINT8 SubClass;
>
> UINT8 BaseClass;
>
> UFS_HC_PEI_PRIVATE_DATA *Private;
>
> @@ -119,16 +120,48 @@ InitializeUfsHcPeim (
> PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function,
> PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER |
> EFI_PCI_COMMAND_MEMORY_SPACE));
>
> PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function,
> PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF);
>
> Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function,
> PCI_BASE_ADDRESSREG_OFFSET));
>
> +
>
> + switch (Size & 0x07) {
>
> + case 0x0:
>
> + //
>
> + // Memory space: anywhere in 32 bit address space
>
> + //
>
> + MmioSize = (~(Size & 0xFFFFFFF0)) + 1;
>
> + break;
>
> + case 0x4:
>
> + //
>
> + // Memory space: anywhere in 64 bit address space
>
> + //
>
> + MmioSize = Size & 0xFFFFFFF0;
>
For 64-bit BAR, I think you also need to write 0xFFFFFFFF to the high 32-bit of the BAR and read the return value as well during the calculation of the request MMIO size.
> +
>
> + //
>
> + // Fix the length to support some spefic 64 bit BAR
Typo: spefic -> specific
>
> + //
>
> + Size |= ((UINT32)(-1) << HighBitSet32 (Size));
>
> +
>
> + //
>
> + // Calculate the size of 64bit bar
>
> + //
>
> + MmioSize |= LShiftU64 ((UINT64) Size, 32);
>
> + MmioSize = (~(MmioSize)) + 1;
With the above 64-bit BAR size change, I think you need to clean the high 32bits of this 64bit BAR to 0, since 32bit BAR address will be used in PEI phase.
>
> + break;
>
> + default:
>
> + //
>
> + // Unknown BAR type
>
> + //
>
> + ASSERT (FALSE);
>
> + continue;
>
> + };
>
> //
>
> // Assign resource to the Ufs Pci host controller's MMIO BAR.
>
> // Enable the Ufs Pci host controller by setting BME and MSE bits of
> PCI_CMD register.
>
> //
>
> - PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function,
> PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32
> (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs));
>
> + PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function,
> PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32
> (PcdUfsPciHostControllerMmioBase) + MmioSize * Private->TotalUfsHcs));
I think the above line can be refined, the driver currently assumes that every UFS HC will have the same request MMIO size (using MmioSize * Private->TotalUfsHcs).
But I do not think this assumption will always be true, it is possible that UFS HCs will have different request MMIO size.
>
> PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function,
> PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER |
> EFI_PCI_COMMAND_MEMORY_SPACE));
>
> //
>
> // Record the allocated Mmio base address.
>
> //
>
> - Private->UfsHcPciAddr[Private->TotalUfsHcs] = PcdGet32
> (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs;
>
> + Private->UfsHcPciAddr[Private->TotalUfsHcs] = PcdGet32
> (PcdUfsPciHostControllerMmioBase) + (UINTN) MmioSize * Private-
> >TotalUfsHcs;
Please update the above line accordingly (not assuming UFS HCs having the same request MMIO size).
Best Regards,
Hao Wu
>
> Private->TotalUfsHcs++;
>
> ASSERT (Private->TotalUfsHcs < MAX_UFS_HCS);
>
> }
>
> --
> 2.16.2.windows.1
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