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charset="us-ascii" Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Chiu, Ian > Sent: Friday, October 22, 2021 5:15 PM > To: devel@edk2.groups.io > Cc: Chiu, Ian ; Chiu, Ian ; Chu, > Maggie ; Ni, Ray ; Wu, Hao A > > Subject: [PATCH] MdeModulePkg\UfsBlockIoPei: UFS MMIO address size > support both 32/64 bit >=20 > From: Ian Chiu >=20 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D3703 > MMIO base address size will overflow while finding two or more Host > controller in the system. Correct it and support 32 and 64 bits address > space. Could you help to provide the information on what tests have been performed= for this patch? Thanks. Some additional inline comments below: >=20 > Signed-off-by: Ian Chiu > Cc: Maggie Chu > Cc: Ray Ni > Cc: Hao A Wu > --- > MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c | 37 > ++++++++++++++++++++++++-- > 1 file changed, 35 insertions(+), 2 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c > b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c > index 447a05b5b2..69a19c60a2 100644 > --- a/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c > +++ b/MdeModulePkg/Bus/Pci/UfsPciHcPei/UfsPciHcPei.c > @@ -76,6 +76,7 @@ InitializeUfsHcPeim ( > UINT16 Device; >=20 > UINT16 Function; >=20 > UINT32 Size; >=20 > + UINT64 MmioSize; >=20 > UINT8 SubClass; >=20 > UINT8 BaseClass; >=20 > UFS_HC_PEI_PRIVATE_DATA *Private; >=20 > @@ -119,16 +120,48 @@ InitializeUfsHcPeim ( > PciAnd16 (PCI_LIB_ADDRESS (Bus, Device, Function, > PCI_COMMAND_OFFSET), (UINT16)~(EFI_PCI_COMMAND_BUS_MASTER | > EFI_PCI_COMMAND_MEMORY_SPACE)); >=20 > PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, > PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF); >=20 > Size =3D PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, > PCI_BASE_ADDRESSREG_OFFSET)); >=20 > + >=20 > + switch (Size & 0x07) { >=20 > + case 0x0: >=20 > + // >=20 > + // Memory space: anywhere in 32 bit address space >=20 > + // >=20 > + MmioSize =3D (~(Size & 0xFFFFFFF0)) + 1; >=20 > + break; >=20 > + case 0x4: >=20 > + // >=20 > + // Memory space: anywhere in 64 bit address space >=20 > + // >=20 > + MmioSize =3D Size & 0xFFFFFFF0; >=20 For 64-bit BAR, I think you also need to write 0xFFFFFFFF to the high 32-bi= t of the BAR and read the return value as well during the calculation of th= e request MMIO size. > + >=20 > + // >=20 > + // Fix the length to support some spefic 64 bit BAR Typo: spefic -> specific >=20 > + // >=20 > + Size |=3D ((UINT32)(-1) << HighBitSet32 (Size)); >=20 > + >=20 > + // >=20 > + // Calculate the size of 64bit bar >=20 > + // >=20 > + MmioSize |=3D LShiftU64 ((UINT64) Size, 32); >=20 > + MmioSize =3D (~(MmioSize)) + 1; With the above 64-bit BAR size change, I think you need to clean the high 3= 2bits of this 64bit BAR to 0, since 32bit BAR address will be used in PEI p= hase. >=20 > + break; >=20 > + default: >=20 > + // >=20 > + // Unknown BAR type >=20 > + // >=20 > + ASSERT (FALSE); >=20 > + continue; >=20 > + }; >=20 > // >=20 > // Assign resource to the Ufs Pci host controller's MMIO BAR. >=20 > // Enable the Ufs Pci host controller by setting BME and MSE b= its of > PCI_CMD register. >=20 > // >=20 > - PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, > PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32 > (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs)); >=20 > + PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, > PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32 > (PcdUfsPciHostControllerMmioBase) + MmioSize * Private->TotalUfsHcs)); I think the above line can be refined, the driver currently assumes that ev= ery UFS HC will have the same request MMIO size (using MmioSize * Private->= TotalUfsHcs). But I do not think this assumption will always be true, it is possible that= UFS HCs will have different request MMIO size. >=20 > PciOr16 (PCI_LIB_ADDRESS (Bus, Device, Function, > PCI_COMMAND_OFFSET), (EFI_PCI_COMMAND_BUS_MASTER | > EFI_PCI_COMMAND_MEMORY_SPACE)); >=20 > // >=20 > // Record the allocated Mmio base address. >=20 > // >=20 > - Private->UfsHcPciAddr[Private->TotalUfsHcs] =3D PcdGet32 > (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs; >=20 > + Private->UfsHcPciAddr[Private->TotalUfsHcs] =3D PcdGet32 > (PcdUfsPciHostControllerMmioBase) + (UINTN) MmioSize * Private- > >TotalUfsHcs; Please update the above line accordingly (not assuming UFS HCs having the s= ame request MMIO size). Best Regards, Hao Wu >=20 > Private->TotalUfsHcs++; >=20 > ASSERT (Private->TotalUfsHcs < MAX_UFS_HCS); >=20 > } >=20 > -- > 2.16.2.windows.1