From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web11.1663.1605256585100899596 for ; Fri, 13 Nov 2020 00:36:25 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=tckgUQSl; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: ashraf.javeed@intel.com) IronPort-SDR: TyCURrKR6tSMbi6PkrDlLwuFjjJKcBjHUUYPcJl2IrQmuWmXJqktubVzH+sJSpvSA8K8WzZS22 jzJ2GuTfDWMQ== X-IronPort-AV: E=McAfee;i="6000,8403,9803"; a="158221751" X-IronPort-AV: E=Sophos;i="5.77,475,1596524400"; d="scan'208";a="158221751" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Nov 2020 00:36:21 -0800 IronPort-SDR: GqPbw0Ip3BLZQv1gdMhAAPhkhUgpWbtdZgFNS9tDo3wJlDj4bGTcpf0HVI/CzS40/0d7x78nRu hFUHFxBOb5oA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,475,1596524400"; d="scan'208";a="542585763" Received: from orsmsx605.amr.corp.intel.com ([10.22.229.18]) by orsmga005.jf.intel.com with ESMTP; 13 Nov 2020 00:36:20 -0800 Received: from orsmsx605.amr.corp.intel.com (10.22.229.18) by ORSMSX605.amr.corp.intel.com (10.22.229.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 13 Nov 2020 00:36:20 -0800 Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx605.amr.corp.intel.com (10.22.229.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Fri, 13 Nov 2020 00:36:20 -0800 Received: from NAM02-CY1-obe.outbound.protection.outlook.com (104.47.37.51) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.1713.5; Fri, 13 Nov 2020 00:36:19 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CRm7mpo39JxXxt0DgEOsQDfIFzEzI4Z2Tx5OnNaqsp+HOuXGYWI7pZWrOp+9Eime2LwLVsycIvJ073KJTX2PsKBO23IKXCFE/zTJGLNdDikBE5Hk/Bff3zX9gMhV19RbyVe/4TO6JmzBHOk7p1PnOwAcON4h9y1RymLbNJrjmfPUn/SSQchRM1NCAY/mWKYaDnn83NHsjis3GO2sKCAbkJmb6QUgJ25FWb2z9LGni/8rztv/LQ6LgAYaq+Wibbubc2ysM0YnvvsLb5D41zBLOH3wIz96HG7ApAK1PzjyLRaZQIxitFbaW38+cDKodxmD4DBn/L84uYCtEmXZCtEIZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VAnBU2vvL0pLy4z81AyW64dSrdwd9EopURPyCU6lq8c=; b=Qsag06jWF3xiCLSHjZKCO1cpeE6grXd5h4hUfOWmgB6BaZTPVUBUUbzXQozEbLuVEPZrkE+PuZ/traf7ZFhSj5TXL9aoRwe4xa5GjAffxybAptAfx4wQbAKbCAggmbDNMDRBdaO1RZ2Xu66quAipok+M8HM7N4N5GhBsJWsvfEfOBUgAwcMHfZf4LN0P1AztIDb4dk7cetGtGxmyBZYJt/XLclhlo7RMr6+tVPlzSsEvA416GUhz7iVpml82pIwwd6xs88Apa+VJrOe9D4WgYpmnMUFLiMQpDqEpPrl6ywuh8Ea01F/1yjcZEHstoe8a5QIlrWt5l9s9RwSoqjiwgA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=VAnBU2vvL0pLy4z81AyW64dSrdwd9EopURPyCU6lq8c=; b=tckgUQSlouJfchswwkX+5OA0n2jbIj7jATX+hwhGR9a8EEZLMk/c3B2skEcKUpkbB8fe0J29DYCDY2L4OM8LzNjty2+bcjC2UHE4yp0xmdvJUTJPcXCgBBWUGV+ooC9wLp7BAd6OATg5cUuDLdGVLI6g8bZx1oLZOPY/vJd1DIo= Received: from DM6PR11MB4076.namprd11.prod.outlook.com (2603:10b6:5:197::17) by DM6PR11MB4329.namprd11.prod.outlook.com (2603:10b6:5:201::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3541.25; Fri, 13 Nov 2020 08:36:18 +0000 Received: from DM6PR11MB4076.namprd11.prod.outlook.com ([fe80::e1e4:f159:daa9:fbf5]) by DM6PR11MB4076.namprd11.prod.outlook.com ([fe80::e1e4:f159:daa9:fbf5%7]) with mapi id 15.20.3541.025; Fri, 13 Nov 2020 08:36:18 +0000 From: "Javeed, Ashraf" To: "Liu, Zhiguang" , "Kinney, Michael D" , "devel@edk2.groups.io" CC: Liming Gao Subject: Re: [Patch 1/1] MdePkg/IndustryStandard: Fix CXL 1.1 structure layout issues Thread-Topic: [Patch 1/1] MdePkg/IndustryStandard: Fix CXL 1.1 structure layout issues Thread-Index: AQHWuUjDQkw5zHwUkE2iTDZryIMTY6nFTCAAgABxKlA= Date: Fri, 13 Nov 2020 08:36:18 +0000 Message-ID: References: <20201112230821.1157-1-michael.d.kinney@intel.com> In-Reply-To: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.5.1.3 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [49.207.218.143] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2d1b475b-52b2-451e-ce4f-08d887af3107 x-ms-traffictypediagnostic: DM6PR11MB4329: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1923; x-ms-exchange-senderadcheck: 1 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: HqvuttnZsDEXnr+PGXKdxDs7VixbRoEfVDY7I4uO1fl3dFHmBXWxuDa6rO6IHje+7dDs7nd9yD9ydNjHS3EWBWgZt/zCNy8S5xzWixx9q2pvgJFo9K47fh6nLV0uIuYpuk+zMeWbClELkHg2ygGTzUEfkIEgQ+FTHDNR7XaR1c7dobI/Dw+4qgAWcPWM9X/mdV8JWweUWBLLnbpbAxWSLNRV2IfW68mmKyZ05nAwtBLeixwnMB9d6bPYeQORwX5xtRzYxSUbg2uTJw2GrZ6rWfX00TTD5y2YlomYE/9nGNNJlMITwY43e7/mKuGFczaKuzND0rsumWPjyoZt/h7ka4pacHAVp9CUYMNuyZpEPqjLJIFT+S6XjXup1sIq9lYEYUK08v8TjinmQwhR6ZUYjA== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM6PR11MB4076.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(4636009)(39860400002)(376002)(346002)(136003)(396003)(366004)(52536014)(316002)(66446008)(66476007)(55016002)(2906002)(64756008)(4326008)(71200400001)(33656002)(66556008)(9686003)(66946007)(8676002)(110136005)(966005)(76116006)(26005)(478600001)(86362001)(19627235002)(186003)(8936002)(5660300002)(83380400001)(53546011)(6506007)(55236004)(7696005);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata: /8pq6ZEZ35IdD7T50trEn3eT5Qy1vB5ym6MP88oscpsowIJ4zq8wgGGWObwCVg/s/IipBlG3vjVdg6M1FDtRFMKfIZWno8GbREtix7VKjUGULy9j9zh82VD3oJuNkxshZnGmhvu4lFUjloddR/GkvHj8gSBYwvU8mmChmQTiwVwJ7L0wLluORkPjvObHyp8r59yAAGvGtmqV7VYoTV/h8nDr2tGpqccfTTZDUMhHdRmZvfptKj5ssraH88HR/K/Z1HdhR6uOCUCj248+Muj71z8d+5PYThleZGrgBUFJ7o08OOityqnELZjmECI4MkEW4QudOcLO3g2ZRdnp0cm/t0yrMlZadd0ZU0qxHjqVwKll/zYe563LKHgQknXvOxriieq3WI+tZnZySy7g8eWk0YAj7bp+vLvy/SLLQjHoOfi84Zu6DLJGQim9KcN4KErfiRBOgl63cA1LF6q7DcmXs8yZTZYTVkOezJ3Rx6b0vO+ZE4IB6TFqDSWC04NBL/v7pHjG2V7BsH4ixTb8k2z9XthAo0Fgr6Gf09BlLLKNMOwX4F88QssOx6SUI5i7+8pYUanelI0/4Ud8OQMjEqy2liXhqTCTgOV1lvXlUvJbzm8gLrb9/VuI1dXlnYR8mp8hebOrVEi0c9ggziPMO5vNQ/8RaKw719czEDRA84+BxzVhPgdhgd8aEgAmHtoHfqzQFjp09v9JtlGLK+3ps9vypS3vGlkaC/vJwhX2g/JM8W4wuhlbt0D+VBJyHEpzy91SaoZeYYkf3zBjhDMSZcdmmFltIneAIoHpyAd3pttWVly5n5btZ52bVXJCX6RdTeVHPtcydDDAzLBUv+6394VgnyNdAdfhauVwb0+MyN7mSfC9aSutfBpeVjxE8nJSwRN/3qh/tDQ8BTn5ZKHUh0D2cw== MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB4076.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d1b475b-52b2-451e-ce4f-08d887af3107 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Nov 2020 08:36:18.2707 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 4vzBWvNBoeebafoB2zL8446Xuqg4opzmlioBeLcqKRxZI9TuaRm+UjUXteBg5FSAPQr74EgebhzcQFCxiODdLw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4329 Return-Path: ashraf.javeed@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Bugs fixed! Changes looks good to me. Reviewed-by: Ashraf Javeed > -----Original Message----- > From: Liu, Zhiguang > Sent: Friday, November 13, 2020 7:20 AM > To: Kinney, Michael D ; devel@edk2.groups.io > Cc: Liming Gao ; Javeed, Ashraf > > Subject: RE: [Patch 1/1] MdePkg/IndustryStandard: Fix CXL 1.1 structure > layout issues >=20 > Reviewed-by: Zhiguang Liu >=20 > > -----Original Message----- > > From: Michael D Kinney > > Sent: Friday, November 13, 2020 7:08 AM > > To: devel@edk2.groups.io > > Cc: Liming Gao ; Liu, Zhiguang > > ; Javeed, Ashraf > > Subject: [Patch 1/1] MdePkg/IndustryStandard: Fix CXL 1.1 structure > > layout issues > > > > https://bugzilla.tianocore.org/show_bug.cgi?id=3D3074 > > > > * Fix offset of LinkLayerControlAndStatus in the > > CXL_1_1_LINK_CAPABILITY_STRUCTURE structure > > * Fix offset of LinkLayerAckTimerControl in the > > CXL_1_1_LINK_CAPABILITY_STRUCTURE structure > > * Fix offset of LinkLayerDefeature in > > the CXL_1_1_LINK_CAPABILITY_STRUCTURE structure > > * Add CXL_11_SIZE_ASSERT() macro to verify the size of > > a register layout structure at compile time and use > > it to verify the sizes of the CXL 1.1 register structures. > > * Add CXL_11_OFFSET_ASSERT() macro to verify the offset of > > fields in a register layout structure at compiler time and > > use it to verify the offset of fields in CXL 1.1 > > register structures. > > > > Cc: Liming Gao > > Cc: Zhiguang Liu > > Cc: Ashraf Javeed > > Signed-off-by: Michael D Kinney > > --- > > MdePkg/Include/IndustryStandard/Cxl11.h | 96 > > ++++++++++++++++++++++++- > > 1 file changed, 93 insertions(+), 3 deletions(-) > > > > diff --git a/MdePkg/Include/IndustryStandard/Cxl11.h > > b/MdePkg/Include/IndustryStandard/Cxl11.h > > index 933c1ab817e8..46cb271d3c74 100644 > > --- a/MdePkg/Include/IndustryStandard/Cxl11.h > > +++ b/MdePkg/Include/IndustryStandard/Cxl11.h > > @@ -32,6 +32,40 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // > > #pragma pack(1) > > > > +/** > > + Macro used to verify the size of a data type at compile time and > > +trigger a > > + STATIC_ASSERT() with an error message if the size of the data type > > +does not > > + match the expected size. > > + > > + @param TypeName Type name of data type to verify. > > + @param ExpectedSize The expected size, in bytes, of the data type > specified > > + by TypeName. > > +**/ > > +#define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize) \ > > + STATIC_ASSERT ( \ > > + sizeof (TypeName) =3D=3D ExpectedSize, \ > > + "Size of " #TypeName \ > > + " does not meet CXL 1.1 Specification requirements." \ > > + ) > > + > > +/** > > + Macro used to verify the offset of a field in a data type at > > +compile time and > > + trigger a STATIC_ASSERT() with an error message if the offset of > > +the field in > > + the data type does not match the expected offset. > > + > > + @param TypeName Type name of data type to verify. > > + @param FieldName Field name in the data type specified by > TypeName > > to > > + verify. > > + @param ExpectedOffset The expected offset, in bytes, of the field > specified > > + by TypeName and FieldName. > > +**/ > > +#define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset) > \ > > + STATIC_ASSERT ( \ > > + OFFSET_OF (TypeName, FieldName) =3D=3D ExpectedOffset, = \ > > + "Offset of " #TypeName "." #FieldName \ > > + " does not meet CXL 1.1 Specification requirements." \ > > + ) > > + > > /// > > /// The PCIe DVSEC for Flex Bus Device ///@{ @@ -201,6 +235,25 @@ > > typedef struct { > > CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH > > DeviceRange2BaseHigh; // offset 48 > > CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW > > DeviceRange2BaseLow; // offset 52 > > } CXL_1_1_DVSEC_FLEX_BUS_DEVICE; > > + > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > Header , 0x00); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > +DesignatedVendorSpecificHeader1, 0x04); CXL_11_OFFSET_ASSERT > > (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, > > 0x08); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceCapability , 0x0A); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceControl , 0x0C); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceStatus , 0x0E); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceControl2 , 0x10); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceStatus2 , 0x12); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceLock , 0x14); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceRange1SizeHigh , 0x18); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceRange1SizeLow , 0x1C); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceRange1BaseHigh , 0x20); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceRange1BaseLow , 0x24); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceRange2SizeHigh , 0x28); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceRange2SizeLow , 0x2C); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceRange2BaseHigh , 0x30); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, > > DeviceRange2BaseLow , 0x34); > > +CXL_11_SIZE_ASSERT > > (CXL_1_1_DVSEC_FLEX_BUS_DEVICE , 0x38); > > ///@} > > > > /// > > @@ -265,6 +318,14 @@ typedef struct { > > CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortCo= ntrol; > > // offset 12 > > CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortSt= atus; > > // offset 14 > > } CXL_1_1_DVSEC_FLEX_BUS_PORT; > > + > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, > > Header , 0x00); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, > > +DesignatedVendorSpecificHeader1, 0x04); CXL_11_OFFSET_ASSERT > > (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, > 0x08); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, > > PortCapability , 0x0A); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, > > PortControl , 0x0C); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, > > PortStatus , 0x0E); > > +CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT > , > > 0x10); > > ///@} > > > > /// > > @@ -423,6 +484,15 @@ typedef struct { > > UINT32 Header= Log[16]; > > } CXL_1_1_RAS_CAPABILITY_STRUCTURE; > > > > +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, > > UncorrectableErrorStatus , 0x00); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, > > UncorrectableErrorMask , 0x04); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, > > UncorrectableErrorSeverity , 0x08); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, > > CorrectableErrorStatus , 0x0C); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, > > CorrectableErrorMask , 0x10); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, > > ErrorCapabilitiesAndControl, 0x14); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, > > HeaderLog , 0x18); > > +CXL_11_SIZE_ASSERT > > (CXL_1_1_RAS_CAPABILITY_STRUCTURE , 0x58); > > + > > typedef union { > > struct { > > UINT32 DeviceTrustLevel : 2; = // bit 0..1 > > @@ -435,6 +505,9 @@ typedef struct { > > CXL_1_1_SECURITY_POLICY Securi= tyPolicy; > > } CXL_1_1_SECURITY_CAPABILITY_STRUCTURE; > > > > +CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, > > SecurityPolicy, 0x0); > > +CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, > > 0x4); > > + > > typedef union { > > struct { > > UINT64 CxlLinkVersionSupported : 4; = // bit 0..3 > > @@ -460,7 +533,7 @@ typedef union { > > UINT16 LlRetryBufferConsumed : 8; = // bit 5..12 > > UINT16 Reserved : 3; = // bit 13..15 > > } Bits; > > - UINT16 Uint16= ; > > + UINT64 Uint64= ; > > } CXL_LINK_LAYER_CONTROL_AND_STATUS; > > > > typedef union { > > @@ -501,7 +574,7 @@ typedef union { > > UINT32 AckForceThreshold : 8; = // bit 0..7 > > UINT32 AckFLushRetimer : 10; = // bit 8..17 > > } Bits; > > - UINT32 Uint32= ; > > + UINT64 Uint64= ; > > } CXL_LINK_LAYER_ACK_TIMER_CONTROL; > > > > typedef union { > > @@ -509,7 +582,7 @@ typedef union { > > UINT32 MdhDisable : 1; = // bit 0..0 > > UINT32 Reserved : 31; = // bit 1..31 > > } Bits; > > - UINT32 Uint32= ; > > + UINT64 Uint64= ; > > } CXL_LINK_LAYER_DEFEATURE; > > > > typedef struct { > > @@ -522,6 +595,15 @@ typedef struct { > > CXL_LINK_LAYER_DEFEATURE LinkLa= yerDefeature; > > } CXL_1_1_LINK_CAPABILITY_STRUCTURE; > > > > +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, > > LinkLayerCapability , 0x00); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, > > LinkLayerControlStatus , 0x08); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, > > LinkLayerRxCreditControl , 0x10); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, > > LinkLayerRxCreditReturnStatus, 0x18); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, > > LinkLayerTxCreditStatus , 0x20); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, > > LinkLayerAckTimerControl , 0x28); > > +CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, > > LinkLayerDefeature , 0x30); > > +CXL_11_SIZE_ASSERT > > (CXL_1_1_LINK_CAPABILITY_STRUCTURE , 0x38= ); > > + > > #define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180 > > typedef union { > > struct { > > @@ -532,6 +614,8 @@ typedef union { > > UINT32 Uint32= ; > > } CXL_IO_ARBITRATION_CONTROL; > > > > +CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4); > > + > > #define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET > > 0x1C0 > > typedef union { > > struct { > > @@ -541,6 +625,9 @@ typedef union { > > } Bits; > > UINT32 Uint32= ; > > } CXL_CACHE_MEMORY_ARBITRATION_CONTROL; > > + > > +CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, > 0x4); > > + > > ///@} > > > > /// The CXL.RCRB base register definition @@ -554,6 +641,9 @@ typedef > > union { > > } Bits; > > UINT64 Uint64= ; > > } CXL_RCRB_BASE; > > + > > +CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8); > > + > > ///@} > > > > #pragma pack() > > -- > > 2.29.2.windows.2