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From: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>
To: "Luo, Heng" <heng.luo@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>
Subject: Re: [Patch V2 6/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add DSC and build files
Date: Wed, 10 Feb 2021 00:29:52 +0000	[thread overview]
Message-ID: <DM6PR11MB44760C470938194F457DFF09B68D9@DM6PR11MB4476.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210209084549.4417-6-heng.luo@intel.com>

Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com> 

-----Original Message-----
From: Luo, Heng <heng.luo@intel.com> 
Sent: Tuesday, February 09, 2021 12:46 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
Subject: [Patch V2 6/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add DSC and build files

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Adds the DSC and build files necessary to build the
TigerlakeURvp board instance.

Key files:
  * build_config.cfg - Board-specific build configuration file.
  * OpenBoardPkg.dsc - The TigerlakeURvp board description file.
  * OpenBoardPkgPcd.dsc - Used for other PCD customization.
  * OpenBoardPkg.fdf - The TigerlakeURvp board flash file.
  * OpenBoardPkgBuildOption.dsc - Sets build options Based on PCD values.

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc            | 347 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf            | 702 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgBuildOption.dsc | 141 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc         | 392 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg            |  34 ++++++++++++++++++++++++++++++++++
 5 files changed, 1616 insertions(+)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
new file mode 100644
index 0000000000..a4265a839c
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc
@@ -0,0 +1,347 @@
+## @file

+#  The main build description file for the TigerlakeURvp board.

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+  DEFINE      PLATFORM_PACKAGE          = MinPlatformPkg

+  DEFINE      PLATFORM_SI_PACKAGE       = TigerlakeSiliconPkg

+  DEFINE      PLATFORM_SI_BIN_PACKAGE   = TigerlakeSiliconBinPkg

+  DEFINE      PLATFORM_FSP_BIN_PACKAGE  = TigerLakeFspBinPkg/Client

+  DEFINE      PLATFORM_BOARD_PACKAGE    = TigerlakeOpenBoardPkg

+  DEFINE      BOARD                     = TigerlakeURvp

+  DEFINE      PROJECT                   = $(PLATFORM_BOARD_PACKAGE)/$(BOARD)

+  DEFINE      PEI_ARCH                  = IA32

+  DEFINE      DXE_ARCH                  = X64

+  DEFINE      TOP_MEMORY_ADDRESS        = 0x0

+

+  #

+  # Default value for OpenBoardPkg.fdf use

+  #

+  DEFINE BIOS_SIZE_OPTION = SIZE_120

+

+[Defines]

+  PLATFORM_NAME                         = $(PLATFORM_BOARD_PACKAGE)

+  PLATFORM_GUID                         = 465B0A0B-7AC1-443b-8F67-7B8DEC145F90

+  PLATFORM_VERSION                      = 0.1

+  DSC_SPECIFICATION                     = 0x00010005

+  OUTPUT_DIRECTORY                      = Build/$(PROJECT)

+  SUPPORTED_ARCHITECTURES               = IA32|X64

+  BUILD_TARGETS                         = DEBUG|RELEASE

+  SKUID_IDENTIFIER                      = ALL

+

+  FLASH_DEFINITION                      = $(PROJECT)/OpenBoardPkg.fdf

+  FIX_LOAD_TOP_MEMORY_ADDRESS           = 0x0

+

+  #

+  # Include PCD configuration for this board.

+  #

+  !include OpenBoardPkgPcd.dsc

+

+################################################################################

+#

+# SKU Identification section - list of all SKU IDs supported by this board.

+#

+################################################################################

+[SkuIds]

+  0|DEFAULT              # 0|DEFAULT is reserved and always required.

+  0x01|SkuIdTglU

+

+

+################################################################################

+#

+# Includes section - other DSC file contents included for this board build.

+#

+################################################################################

+

+#######################################

+# Library Includes

+#######################################

+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc

+!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc

+!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc

+

+[LibraryClasses.common]

+

+  PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf

+  ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiReportFvLib.inf

+

+  PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/PciHostBridgeLibSimple.inf

+  PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf

+  PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf

+

+  PlatformHookLib|$(PLATFORM_BOARD_PACKAGE)/Library/BasePlatformHookLib/BasePlatformHookLib.inf

+

+  FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf

+  PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf

+  PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.inf

+

+  FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf

+  FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf

+

+  ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf

+

+  BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf

+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf

+

+  PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf

+  PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf

+  ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf

+

+  #

+  # Silicon Init Package

+  #

+  !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc

+

+  #

+  # Shell

+  #

+  ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf

+  HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf

+  BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf

+

+[LibraryClasses.IA32]

+ FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapperPlatformLib/PeiFspWrapperPlatformLib.inf

+!if $(TARGET) == DEBUG

+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf

+!endif

+  TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointLib.inf

+  MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf

+  BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/PeiMultiBoardInitSupportLib.inf

+

+  #

+  # Silicon Init Package

+  #

+  !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc

+

+  #

+  # Use Null library instance to skip MTRR initialization from MinPlatformPkg PlatformInit modules.

+  # MTRR configuration will be done by FSP or PlatformInitAdvanced modules.

+  #

+  SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.inf

+

+  #

+  # SmmAccess

+  #

+  SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf

+

+  SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf

+  SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf

+

+  #######################################

+  # Board-specific

+  #######################################

+  PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf

+

+!if $(TARGET) == DEBUG

+  GpioCheckConflictLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf

+!else

+  GpioCheckConflictLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf

+!endif

+

+[LibraryClasses.IA32.SEC]

+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf

+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf

+  SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf

+

+[LibraryClasses.X64]

+  #

+  # DXE phase common

+  #

+  FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapperPlatformLib/DxeFspWrapperPlatformLib.inf

+!if $(TARGET) == DEBUG

+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/DxeTestPointCheckLib.inf

+!endif

+  TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf

+  MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf

+  BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupportLib/DxeMultiBoardInitSupportLib.inf

+  MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf

+  BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/DxeMultiBoardAcpiSupportLib.inf

+  AslUpdateLib|$(PLATFORM_PACKAGE)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf

+

+  SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf

+  SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf

+  BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf

+  BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBootManagerLib.inf

+

+  #

+  # Silicon Init Package

+  #

+  !include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc

+

+[LibraryClasses.X64.DXE_SMM_DRIVER]

+  SpiFlashCommonLib|$(PLATFORM_BOARD_PACKAGE)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf

+!if $(TARGET) == DEBUG

+  TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf

+!endif

+  BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf

+  MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupportLib/SmmMultiBoardAcpiSupportLib.inf

+  TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointLib.inf

+

+[LibraryClasses.X64.DXE_RUNTIME_DRIVER]

+  ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf

+

+[Components.IA32]

+

+  #

+  # Common

+  #

+  !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc

+

+  #

+  # FSP wrapper SEC Core

+  #

+  UefiCpuPkg/SecCore/SecCore.inf {

+    <LibraryClasses>

+      PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf

+  }

+

+  #

+  # Silicon

+  #

+  !include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc

+

+  #

+  # Platform

+  #

+  $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf

+  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {

+    <LibraryClasses>

+      NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf

+  }

+  IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf {

+    <LibraryClasses>

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0

+      SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyInitLibNull/SiliconPolicyInitLibNull.inf

+      SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf

+!endif

+  }

+

+  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {

+    <LibraryClasses>

+      NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf

+  }

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0

+  $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf  {

+    <LibraryClasses>

+      NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicyInitLib.inf

+  }

+  $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf {

+    <LibraryClasses>

+      NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf

+      #

+      # In FSP Dispatch mode below dummy library should be linked to bootloader PEIM

+      # to build all DynamicEx PCDs that FSP consumes into bootloader PCD database.

+      #

+      NULL|$(PLATFORM_FSP_BIN_PACKAGE)/Library/FspPcdListLib/FspPcdListLibNull.inf

+  }

+!endif

+  $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf

+  $(PLATFORM_PACKAGE)/Services/StallServicePei/StallServicePei.inf

+

+  IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf

+

+  #

+  MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf

+  # Security

+  #

+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE

+  $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf

+!endif

+ MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf {

+   <LibraryClasses>

+     ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/BaseResetSystemLib.inf

+ }

+

+[Components.X64]

+

+  #

+  # Common

+  #

+  !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc

+

+  #

+  #UEFI Shell

+  #

+  ShellPkg/Application/Shell/Shell.inf {

+    <LibraryClasses>

+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf

+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf

+

+    <PcdsFixedAtBuild>

+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE

+  }

+

+  UefiCpuPkg/CpuDxe/CpuDxe.inf

+  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf

+

+  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf

+  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf

+  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf

+  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf

+  MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf

+

+  BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf

+

+  #

+  # Silicon

+  #

+  !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc

+  $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf

+

+  #

+  # SmmAccess

+  #

+  IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf

+

+  #

+  # Platform

+  #

+  $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf

+  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1

+  IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf

+!endif

+  $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf

+

+  $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf

+  $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf

+

+  #

+  # OS Boot

+  #

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE

+  $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf

+  $(PLATFORM_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf

+  $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {

+    <LibraryClasses>

+      NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf

+  }

+

+  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf

+  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf

+

+  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {

+    <LibraryClasses>

+      SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf

+  }

+!endif

+

+  #

+  # Security

+  #

+  $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf

+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE

+  $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf

+!endif

+

+  !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc

+  !include OpenBoardPkgBuildOption.dsc

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
new file mode 100644
index 0000000000..0f645ed63e
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf
@@ -0,0 +1,702 @@
+## @file

+#  FDF file of Platform.

+#

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[Defines]

+   !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf

+

+################################################################################

+#

+# FD Section

+# The [FD] Section is made up of the definition statements and a

+# description of what goes into  the Flash Device Image.  Each FD section

+# defines one flash "device" image.  A flash device image may be one of

+# the following: Removable media bootable image (like a boot floppy

+# image,) an Option ROM image (that would be "flashed" into an add-in

+# card,) a System "Flash"  image (that would be burned into a system's

+# flash) or an Update ("Capsule") image that will be used to update and

+# existing system flash.

+#

+################################################################################

+[FD.TigerlakeURvp]

+#

+# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be

+# assigned with PCD values. Instead, it uses the definitions for its variety, which

+# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.

+#

+BaseAddress   = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress  #The base address of the FLASH Device.

+Size          = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize             #The size in bytes of the FLASH Device

+ErasePolarity = 1

+BlockSize     = $(FLASH_BLOCK_SIZE)

+NumBlocks     = $(FLASH_NUM_BLOCKS)

+

+DEFINE SIPKG_DXE_SMM_BIN  = INF

+DEFINE SIPKG_PEI_BIN      = INF

+

+# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.

+# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.

+SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)

+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)

+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x1000

+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)

+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)

+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)

+SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)

+SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress)

+SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize)

+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset)

+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress

+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize    = gSiPkgTokenSpaceGuid.PcdBiosSize

+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)

+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)

+SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase    = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize    = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset  = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress    = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize           = gSiPkgTokenSpaceGuid.PcdBiosSize

+################################################################################

+#

+# Following are lists of FD Region layout which correspond to the locations of different

+# images within the flash device.

+#

+# Regions must be defined in ascending order and may not overlap.

+#

+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by

+# the pipe "|" character, followed by the size of the region, also in hex with the leading

+# "0x" characters. Like:

+# Offset|Size

+# PcdOffsetCName|PcdSizeCName

+# RegionType <FV, DATA, or FILE>

+# Fv Size can be adjusted

+#

+################################################################################

+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize

+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize

+#NV_VARIABLE_STORE

+DATA = {

+  ## This is the EFI_FIRMWARE_VOLUME_HEADER

+  # ZeroVector []

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  # FileSystemGuid

+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,

+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,

+  # FvLength: 0x60000

+  0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00,

+  #Signature "_FVH"       #Attributes

+  0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,

+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision

+  #

+  # Be careful on CheckSum field.

+  #

+  0x48, 0x00, 0x2E, 0x09, 0x00, 0x00, 0x00, 0x02,

+  #Blockmap[0]: 6 Blocks  0x10000 Bytes / Block

+  0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,

+  #Blockmap[1]: End

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  ## This is the VARIABLE_STORE_HEADER

+!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE

+  #  Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}

+  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,

+  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,

+!else

+  #  Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}

+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,

+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,

+!endif

+  #Size: 0x2E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x2DFB8

+  # This can speed up the Variable Dispatch a bit.

+  0xB8, 0xDF, 0x02, 0x00,

+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32

+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

+}

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize

+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize

+#NV_FTW_WORKING

+DATA = {

+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid         =

+  #  { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95 }}

+  0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,

+  0xa0, 0xce, 0x65,  0x0, 0xfd, 0x9f, 0x1b, 0x95,

+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved

+  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,

+  # WriteQueueSize: UINT64

+  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

+}

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize

+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize

+#NV_FTW_SPARE

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize

+FV = FvAdvanced

+

+gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize

+gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize

+FV = FvOptional

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize

+FV = FvOsBoot

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize

+FV = FvUefiBoot

+

+gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize

+gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize

+FV = FvFwBinaries

+

+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize

+gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize

+#Microcode

+FV = FvMicrocode

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize

+FV = FvPostMemory

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize

+# FSP_S Section

+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize

+# FSP_M Section

+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize

+# FSP_T Section

+FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize

+FV = FvSecurityPreMemory

+

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize

+gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize

+FV = FvPreMemory

+

+################################################################################

+#

+# FV Section

+#

+# [FV] section is used to define what components or modules are placed within a flash

+# device file.  This section also defines order the components and modules are positioned

+# within the image.  The [FV] section consists of define statements, set statements and

+# module statements.

+#

+################################################################################

+[FV.FvMicrocode]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+

+INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf

+

+[FV.FvPreMemory]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D

+

+INF  UefiCpuPkg/SecCore/SecCore.inf

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1

+INF  MdeModulePkg/Core/Pei/PeiMain.inf

+!endif

+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf

+

+INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf

+INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf

+

+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf

+INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf

+INF MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0

+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf

+# Provide gEfiPeiStallPpiGuid for FSP dispatch mode

+INF $(PLATFORM_PACKAGE)/Services/StallServicePei/StallServicePei.inf

+!endif

+

+[FV.FvPostMemoryUncompact]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7

+

+!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf

+

+# Init Board Config PCD

+INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf

+INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0

+INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf

+

+!endif

+

+!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE

+FILE FREEFORM = PCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid) {

+  SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin

+  SECTION UI  = "Vbt"

+}

+FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {

+  SECTION RAW = MdeModulePkg/Logo/Logo.bmp

+}

+!endif # PcdPeiDisplayEnable

+INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf

+

+[FV.FvPostMemory]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 9DFE49DB-8EF0-4D9C-B273-0036144DE917

+

+FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {

+      SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {

+        SECTION FV_IMAGE = FvPostMemoryUncompact

+      }

+      SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {

+        SECTION FV_IMAGE = FvSecurityPostMemory

+      }

+      SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {

+        SECTION FV_IMAGE = FvSecurityLate

+      }

+}

+

+[FV.FvUefiBootUncompact]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = A881D567-6CB0-4eee-8435-2E72D33E45B5

+

+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf

+

+INF  UefiCpuPkg/CpuDxe/CpuDxe.inf

+INF  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf

+

+INF  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf

+INF  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf

+INF  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf

+INF  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf

+INF  MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf

+INF  BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf

+

+#

+#UEFI Shell

+#

+# Note : gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell.inf/Shell.inf.

+#        The GUID has to be changed according to the change you make to override MinUefiShell.inf/UefiShell.inf/Shell.inf FILE_GUID.

+#

+FILE APPLICATION = 7C04A583-9E3E-4F1C-AD65-E05268D0B4D1 {

+!if $(TARGET) == DEBUG

+  SECTION PE32 = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/ShellPkg/Application/Shell/Shell/OUTPUT/Shell.efi

+!else

+  SECTION PE32 = $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/ShellPkg/Application/Shell/Shell/OUTPUT/Shell.efi

+!endif

+  SECTION UI = "EdkShell"

+}

+

+INF  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1

+INF  IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf

+!endif

+INF  $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf

+

+FILE FV_IMAGE = C6CE361E-4554-41E5-AF27-C3FADBA6DA9C {

+  SECTION FV_IMAGE = $(PLATFORM_FSP_BIN_PACKAGE)/FvLateSilicon.fv

+}

+

+[FV.FvUefiBoot]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 0496D33D-EA79-495C-B65D-ABF607184E3B

+

+FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {

+       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {

+         SECTION FV_IMAGE = FvUefiBootUncompact

+       }

+     }

+

+[FV.FvOsBootUncompact]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC

+

+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE

+INF  $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf

+INF  $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf

+INF  $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf

+

+INF  UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf

+INF  $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf

+INF  $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf

+

+INF  RuleOverride = DRIVER_ACPITABLE $(PLATFORM_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf

+INF  $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf

+

+!endif

+

+[FV.FvLateSilicon]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE

+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeTgl.inf

+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf

+

+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf

+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf

+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf

+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf

+

+!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE

+INF  RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf

+INF  RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/AcpiTables/IgfxSsdt.inf

+!endif

+!endif #PcdBootToShellOnly

+

+$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Smm/SaLateInitSmm.inf

+

+[FV.FvOsBoot]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 13BF8810-75FD-4B1A-91E6-E16C4201F80A

+

+FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {

+       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {

+         SECTION FV_IMAGE = FvOsBootUncompact

+       }

+     }

+

+FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {

+       SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {

+         SECTION FV_IMAGE = FvLateSilicon

+       }

+     }

+

+[FV.FvSecurityPreMemory]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16         #FV alignment and FV attributes setting.

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B

+

+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf

+

+[FV.FvSecurityPostMemory]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16         #FV alignment and FV attributes setting.

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 4199E560-54AE-45E5-91A4-F7BC3804E14A

+

+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE

+INF $(CLIENT_COMMON_PACKAGE)/Universal/Tcg2PlatformPei/Tcg2PlatformPei.inf

+!endif

+

+[FV.FvSecurityLate]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = F753FE9A-EEFD-485B-840B-E032D538102C

+

+!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE

+

+INF  $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE

+INF  $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf

+!endif

+

+!endif

+INF  IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf

+

+#

+# Do not use nested FV in PEI phase as current FMMT cannot handle it properly when deleting modules.

+#

+#[FV.FvSecurity]

+#BlockSize          = $(FLASH_BLOCK_SIZE)

+#FvAlignment        = 16

+#ERASE_POLARITY     = 1

+#MEMORY_MAPPED      = TRUE

+#STICKY_WRITE       = TRUE

+#LOCK_CAP           = TRUE

+#LOCK_STATUS        = TRUE

+#WRITE_DISABLED_CAP = TRUE

+#WRITE_ENABLED_CAP  = TRUE

+#WRITE_STATUS       = TRUE

+#WRITE_LOCK_CAP     = TRUE

+#WRITE_LOCK_STATUS  = TRUE

+#READ_DISABLED_CAP  = TRUE

+#READ_ENABLED_CAP   = TRUE

+#READ_STATUS        = TRUE

+#READ_LOCK_CAP      = TRUE

+#READ_LOCK_STATUS   = TRUE

+#FvNameGuid         = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF

+

+#FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {

+#       SECTION FV_IMAGE = FvSecurityPreMemory

+#     }

+

+

+[FV.FvAdvanced]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = B23E7388-9953-45C7-9201-0473DDE5487A

+

+

+[FV.FvFwBinaries]

+BlockSize     = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 8B98AB22-E354-42f0-88B9-049810F0FDAA

+

+

+

+

+

+[FV.FvOptional]

+BlockSize          = $(FLASH_BLOCK_SIZE)

+FvAlignment        = 16

+ERASE_POLARITY     = 1

+MEMORY_MAPPED      = TRUE

+STICKY_WRITE       = TRUE

+LOCK_CAP           = TRUE

+LOCK_STATUS        = TRUE

+WRITE_DISABLED_CAP = TRUE

+WRITE_ENABLED_CAP  = TRUE

+WRITE_STATUS       = TRUE

+WRITE_LOCK_CAP     = TRUE

+WRITE_LOCK_STATUS  = TRUE

+READ_DISABLED_CAP  = TRUE

+READ_ENABLED_CAP   = TRUE

+READ_STATUS        = TRUE

+READ_LOCK_CAP      = TRUE

+READ_LOCK_STATUS   = TRUE

+FvNameGuid         = 9574B1CE-EE93-451E-B500-3E5F564244DE

+################################################################################

+#

+# Rules are use with the [FV] section's module INF type to define

+# how an FFS file is created for a given INF file. The following Rule are the default

+# rules for the different module type. User can add the customized rules to define the

+# content of the FFS file.

+#

+################################################################################

+

+!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgBuildOption.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgBuildOption.dsc
new file mode 100644
index 0000000000..b72329846a
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgBuildOption.dsc
@@ -0,0 +1,141 @@
+## @file

+# platform build option configuration file.

+#

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+[BuildOptions]

+# Define Build Options both for EDK and EDKII drivers.

+

+

+  DEFINE DSC_S3_BUILD_OPTIONS =

+

+!if gSiPkgTokenSpaceGuid.PcdAcpiEnable == TRUE

+  DEFINE DSC_ACPI_BUILD_OPTIONS = -DACPI_SUPPORT=1

+!else

+  DEFINE DSC_ACPI_BUILD_OPTIONS =

+!endif

+

+  DEFINE BIOS_GUARD_BUILD_OPTIONS =

+

+  DEFINE OVERCLOCKING_BUILD_OPTION =

+

+  DEFINE FSP_BINARY_BUILD_OPTIONS =

+

+  DEFINE FSP_WRAPPER_BUILD_OPTIONS = -DFSP_WRAPPER_FLAG

+

+  DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =

+

+!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable == FALSE

+  DEFINE OPTIMIZE_DISABLE_OPTIONS = -Od -GL-

+!else

+  DEFINE OPTIMIZE_DISABLE_OPTIONS =

+!endif

+

+  DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =

+

+

+  DEFINE TPM_BUILD_OPTION =

+

+  DEFINE TPM2_BUILD_OPTION =

+

+  DEFINE DSC_TBT_BUILD_OPTIONS =

+

+  DEFINE DSC_DCTT_BUILD_OPTIONS =

+

+  DEFINE EMB_BUILD_OPTIONS =

+

+  DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS = -DMEM_DOWN_FLAG=1

+

+  DEFINE DSC_KBCEMUL_BUILD_OPTIONS =

+

+  DEFINE BOOT_GUARD_BUILD_OPTIONS =

+

+  DEFINE SECURE_BOOT_BUILD_OPTIONS =

+

+  DEFINE USBTYPEC_BUILD_OPTION =

+

+  DEFINE CAPSULE_BUILD_OPTIONS =

+

+  DEFINE PERFORMANCE_BUILD_OPTION =

+

+  DEFINE DEBUGUSEUSB_BUILD_OPTION =

+

+  DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION = -DDISABLE_NEW_DEPRECATED_INTERFACES=1

+

+  DEFINE SINITBIN_BUILD_OPTION =

+

+  DEFINE MINTREE_FLAG_BUILD_OPTION = -DMINTREE_FLAG=1

+

+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)  $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS)

+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGUSEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS)

+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS)

+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION)

+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)

+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYPEC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)

+DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+

+[BuildOptions.Common.EDKII]

+

+#

+# For IA32 Global Build Flag

+#

+       *_*_IA32_CC_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI

+       *_*_IA32_VFRPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+       *_*_IA32_APP_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+       *_*_IA32_ASLPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+       *_*_IA32_ASLCC_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+       *_*_IA32_NASM_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+

+#

+# For IA32 Specific Build Flag

+#

+GCC:   *_*_IA32_PP_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+MSFT:  *_*_IA32_ASM_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+MSFT:  *_*_IA32_CC_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015 -DASF_PEI

+MSFT:  *_*_IA32_VFRPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)

+MSFT:  *_*_IA32_APP_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)

+MSFT:  *_*_IA32_ASLPP_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)

+MSFT:  *_*_IA32_ASLCC_FLAGS   = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)

+

+#

+# For X64 Global Build Flag

+#

+       *_*_X64_CC_FLAGS       = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015

+       *_*_X64_VFRPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+       *_*_X64_APP_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+       *_*_X64_ASLPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+       *_*_X64_ASLCC_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+       *_*_X64_NASM_FLAGS     = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+

+

+#

+# For X64 Specific Build Flag

+#

+GCC:   *_*_X64_PP_FLAGS       = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+MSFT:  *_*_X64_ASM_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+MSFT:  *_*_X64_CC_FLAGS       = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=0x00010015

+MSFT:  *_*_X64_VFRPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)

+MSFT:  *_*_X64_APP_FLAGS      = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OPTIMIZE_DISABLE_OPTIONS)

+MSFT:  *_*_X64_ASLPP_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+MSFT:  *_*_X64_ASLCC_FLAGS    = $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)

+

+

+# Force PE/COFF sections to be aligned at 4KB boundaries to support page level protection

+[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]

+  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096

+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000

+

+# Force PE/COFF sections to be aligned at 4KB boundaries to support MemoryAttribute table

+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]

+  MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096

+  GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000

+

+# Force PE/COFF sections to be aligned at 4KB boundaries to support NX protection

+[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE, BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPLICATION]

+  #MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096

+  #GCC:*_*_*_DLINK_FLAGS = -z common-page-size=0x1000

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
new file mode 100644
index 0000000000..a048efcc18
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
@@ -0,0 +1,392 @@
+## @file

+#  PCD configuration build description file for the TigerlakeURvp board.

+#

+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+#  SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+##

+

+################################################################################

+#

+# Pcd Section - list of all PCD Entries used by this board.

+#

+################################################################################

+

+[PcdsFixedAtBuild.common]

+  ######################################

+  # Key Boot Stage and FSP configuration

+  ######################################

+  #

+  # Please select the Boot Stage here.

+  # Stage 1 - enable debug (system deadloop after debug init)

+  # Stage 2 - mem init (system deadloop after mem init)

+  # Stage 3 - boot to shell only

+  # Stage 4 - boot to OS

+  # Stage 5 - boot to OS with security boot enabled

+  # Stage 6 - boot with advanced features enabled

+  #

+  gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4

+

+  #

+  # 0: FSP Wrapper is running in Dispatch mode.

+  # 1: FSP Wrapper is running in API mode.

+  # Note: Dispatch mode is currently NOT supported for this board.

+  #

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0

+

+  #

+  # FALSE: The board is not a FSP wrapper (FSP binary not used)

+  # TRUE:  The board is a FSP wrapper (FSP binary is used)

+  #

+  gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE

+

+  #

+  # FSP Base address PCD will be updated in FDF basing on flash map.

+  #

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0

+

+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000

+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00080000

+  gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000

+  gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000

+  gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000

+

+  #

+  # PCD declared for TigerlakeSiliconPkg Fru

+  #

+  gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|FALSE

+  gSiPkgTokenSpaceGuid.PcdCpuPcieEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0

+  gSiPkgTokenSpaceGuid.PcdThcEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported|TRUE

+

+  ######################################

+  # Silicon Configuration

+  ######################################

+  # Build switches

+  gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE

+

+  # CPU

+  gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE

+

+  # SA

+  gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE

+

+  # ME

+  gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE

+  gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE

+

+  # Others

+  gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE

+  gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE

+  gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE

+  gSiPkgTokenSpaceGuid.PcdFspWrapperEnable|TRUE

+

+  #

+  # When sharing stack with boot loader, FSP only needs a small temp ram for heap

+  #

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1

+  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00020000

+!else

+      #

+      # FSP Dispatch mode will not establish separate Stack or Heap.

+      #

+  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0

+!endif

+

+  #

+  # Boot loader stack size has to be large enough for FSP execution

+  #

+  gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000

+

+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xC0000000

+#!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1

+  gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000

+#!endif

+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000

+[PcdsFeatureFlag.common]

+  ######################################

+  # Edk2 Configuration

+  ######################################

+  gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE

+

+  ######################################

+  # Platform Configuration

+  ######################################

+  gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE

+  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE

+  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE

+  gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE

+  gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE

+  gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE

+  gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|TRUE

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1

+  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE

+!endif

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2

+  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE

+  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE

+!endif

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3

+  gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE

+  gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE

+!endif

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4

+  gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE

+!endif

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5

+  gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE

+  gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE

+!endif

+

+!if $(TARGET) == DEBUG

+  gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE

+!else

+  gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE

+!endif

+

+  ######################################

+  # Board Configuration

+  ######################################

+  gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE

+

+[PcdsFixedAtBuild.common]

+  ######################################

+  # Edk2 Configuration

+  ######################################

+!if $(TARGET) == RELEASE

+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0

+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3

+!else

+  gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F

+  gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07

+!endif

+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE

+  gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1

+!endif

+

+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE

+!if $(TARGET) == RELEASE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE

+!else

+  gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE

+!endif

+  gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01

+  gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0

+  gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800

+  gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)

+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400

+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140

+!endif

+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000

+  gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE

+!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1

+!endif

+  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE

+!if $(TARGET) == DEBUG

+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE

+!endif

+

+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80

+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00

+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0

+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F

+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44

+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2

+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800

+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC

+  gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08

+

+  # Specifies timeout value in microseconds for the BSP to detect all APs for the first time.

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x0

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000

+

+  #

+  # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild

+  # (They will be DynamicEx in FSP Dispatch mode)

+  #

+

+  ## Specifies the size of the microcode Region.

+  # @Prompt Microcode Region size.

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0

+

+  ## Specifies the AP wait loop state during POST phase.

+  #  The value is defined as below.

+  #  1: Place AP in the Hlt-Loop state.

+  #  2: Place AP in the Mwait-Loop state.

+  #  3: Place AP in the Run-Loop state.

+  # @Prompt The AP wait loop state.

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2

+

+  ######################################

+  # Platform Configuration

+  ######################################

+  gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1

+  gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8

+  gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2

+

+  gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase|0xA0000000

+  gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xDFFFFFFF

+  #

+  # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags

+  #

+  # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.

+  # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \

+  #       that lie entirely within the expected fixed memory regions.

+  # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.

+  # BIT3-31: Reserved

+  #

+  gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07

+

+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0xCC

+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA2

+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x3100

+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x2A

+  gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xC4

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1

+  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

+!endif

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2

+  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

+!endif

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3

+  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

+!endif

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4

+  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

+!endif

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5

+  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

+!endif

+

+!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6

+  gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}

+!endif

+

+[PcdsFixedAtBuild.IA32]

+  ######################################

+  # Edk2 Configuration

+  ######################################

+  gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0

+  gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148

+  gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000

+

+  ######################################

+  # Platform Configuration

+  ######################################

+  gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000

+

+[PcdsFixedAtBuild.X64]

+  ######################################

+  # Edk2 Configuration

+  ######################################

+

+  # Default platform supported RFC 4646 languages: (American) English

+  gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"

+

+[PcdsPatchableInModule.common]

+  ######################################

+  # Edk2 Configuration

+  ######################################

+  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0301

+  gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046

+

+  ######################################

+  # Silicon Configuration

+  ######################################

+!if $(TARGET) == DEBUG

+  gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1

+!endif

+

+[PcdsDynamicDefault]

+  ######################################

+  # Edk2 Configuration

+  ######################################

+  gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE

+  gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE

+  ######################################

+  # Silicon Configuration

+  ######################################

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1

+  gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength

+!endif

+

+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0

+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0

+  #gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0

+

+  #

+  #  Set video to native resolution as Windows 8 WHCK requirement.

+  #

+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0

+  gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0

+

+  gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00

+

+  #

+  # FSP Base address PCD will be updated in FDF basing on flash map.

+  #

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0

+

+  # Platform will pre-allocate UPD buffer and pass it to FspWrapper

+  # Those dummy address will be patched before FspWrapper executing

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0

+  gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0

+

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0

+  gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16

+

+[PcdsDynamicHii.X64.DEFAULT]

+  ######################################

+  # Edk2 Configuration

+  ######################################

+  gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"

+!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE

+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"

+!else

+  gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"

+!endif

+

+[PcdsDynamicExDefault]

+  gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0

+

+!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0

+  #

+  # Include FSP PCD settings.

+  #

+  !include $(PLATFORM_FSP_BIN_PACKAGE)/TigerLakeFspPcds.dsc

+!endif

+

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg
new file mode 100644
index 0000000000..f8047701f8
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg
@@ -0,0 +1,34 @@
+# @ build_config.cfg

+# This is the WhiskeylakeURvp board specific build settings

+#

+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+# SPDX-License-Identifier: BSD-2-Clause-Patent

+#

+

+

+[CONFIG]

+WORKSPACE_PLATFORM_BIN =

+EDK_SETUP_OPTION =

+openssl_path =

+PLATFORM_BOARD_PACKAGE = TigerlakeOpenBoardPkg

+PROJECT = TigerlakeOpenBoardPkg/TigerlakeURvp

+BOARD = TigerlakeURvp

+FLASH_MAP_FDF = TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf

+PROJECT_DSC = TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc

+BOARD_PKG_PCD_DSC = TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc

+PrepRELEASE = DEBUG

+SILENT_MODE = FALSE

+EXT_CONFIG_CLEAR =

+CapsuleBuild = FALSE

+EXT_BUILD_FLAGS =

+CAPSULE_BUILD = 0

+TARGET = DEBUG

+TARGET_SHORT = D

+PERFORMANCE_BUILD = FALSE

+FSP_WRAPPER_BUILD = TRUE

+FSP_BIN_PKG = TigerLakeFspBinPkg/Client

+FSP_PKG_NAME = TigerlakeSiliconPkg

+FSP_BINARY_BUILD = FALSE

+FSP_TEST_RELEASE = FALSE

+SECURE_BOOT_ENABLE = FALSE

+BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807

-- 
2.24.0.windows.2


  reply	other threads:[~2021-02-10  0:30 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-09  8:45 [Patch V2 1/8] TigerlakeOpenBoardPkg: Add package and headers Heng Luo
2021-02-09  8:45 ` [Patch V2 2/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add fdf and header file Heng Luo
2021-02-09 23:42   ` Chaganty, Rangasai V
2021-02-09  8:45 ` [Patch V2 3/8] TigerlakeOpenBoardPkg: Add library instances Heng Luo
2021-02-09 23:45   ` Chaganty, Rangasai V
2021-02-09  8:45 ` [Patch V2 4/8] TigerlakeOpenBoardPkg/TigerlakeURvp: " Heng Luo
2021-02-10  0:38   ` Chaganty, Rangasai V
2021-02-10  3:58     ` Heng Luo
2021-02-09  8:45 ` [Patch V2 5/8] TigerlakeOpenBoardPkg: Add modules Heng Luo
2021-02-10  0:22   ` Chaganty, Rangasai V
2021-02-10  0:27   ` Chaganty, Rangasai V
2021-02-09  8:45 ` [Patch V2 6/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add DSC and build files Heng Luo
2021-02-10  0:29   ` Chaganty, Rangasai V [this message]
2021-02-09  8:45 ` [Patch V2 7/8] Enable build for TigerlakeOpenBoardPkg Heng Luo
2021-02-10  0:30   ` Chaganty, Rangasai V
2021-02-09  8:45 ` [Patch V2 8/8] Update Maintainers.txt " Heng Luo
2021-02-10  0:31   ` Chaganty, Rangasai V
2021-02-09 23:41 ` [Patch V2 1/8] TigerlakeOpenBoardPkg: Add package and headers Chaganty, Rangasai V

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