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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Sai Chaganty =20 -----Original Message----- From: Luo, Heng =20 Sent: Thursday, February 04, 2021 12:49 AM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Desimone, Nathani= el L Subject: [Patch V2 01/40] TigerlakeSiliconPkg: Add package and Include/Conf= igBlock headers REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Create the TigerlakeSiliconPkg to provide an initial package for silicon initialization code for Tiger Lake (TGL) products. * Major areas of functionality are categorized into CPU, IpBlock, Fru, Platform Controller Hub (PCH), and System Agent subdirectories. * Common libraries and headers are kept at the root of the package. Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h = | 67 ++++++++++++++++++++++++++++++++++++++++++++++++= ++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPreMemC= onfig.h | 86 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPc= ieConfig.h | 498 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h = | 72 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h = | 61 ++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h = | 170 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h = | 33 +++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h = | 31 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h= | 37 ++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Graph= icsConfig.h | 211 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig.h = | 227 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBridg= eConfig.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hybri= dGraphicsConfig.h | 66 ++++++++++++++++++++++++++++++++++++++++++++++++= + Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/Hybrid= StorageConfig.h | 36 +++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h = | 34 ++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h = | 134 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig= .h | 58 ++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig.h = | 60 +++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h = | 117 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryCo= nfig.h | 478 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Overclo= ckingConfig.h | 236 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h = | 34 ++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.= h | 44 +++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/Pch= PcieRpConfig.h | 368 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= + Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h = | 217 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h = | 86 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h = | 391 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h = | 32 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h = | 82 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h = | 38 +++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h = | 168 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h = | 139 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoCon= fig.h | 32 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h = | 152 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h = | 67 ++++++++++++++++++++++++++++++++++++++++++++++++= ++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h = | 50 ++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h = | 43 ++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h= | 145 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h = | 73 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalConfi= g.h | 153 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHubCon= fig.h | 101 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig.h = | 81 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfig.h= | 138 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h = | 149 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/Cpu= PowerMgmtVrConfig.h | 114 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h = | 64 ++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h= | 31 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec = | 1207 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++ 48 files changed, 6973 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/Cnv= iConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/Cnvi= Config.h new file mode 100644 index 0000000000..de1f4159f0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig= .h @@ -0,0 +1,67 @@ +/** @file + CNVi policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CNVI_CONFIG_H_ +#define _CNVI_CONFIG_H_ + +#define CNVI_CONFIG_REVISION 1 +extern EFI_GUID gCnviConfigGuid; + +#pragma pack (push,1) + +/** + CNVi Mode options +**/ +typedef enum { + CnviModeDisabled =3D 0, + CnviModeAuto +} CNVI_MODE; + + +/** + CNVi signals pin muxing settings. If signal can be enable only on a sing= le pin + then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* in G= pioPins*.h + for supported settings on a given platform +**/ +typedef struct { + UINT32 RfReset; ///< RF_RESET# Pin mux configuration. Refer to GPIO_*_MU= XING_CNVI_RF_RESET_* + UINT32 Clkreq; ///< CLKREQ Pin mux configuration. Refer to GPIO_*_MUXIN= G_CNVI_*_CLKREQ_* +} CNVI_PIN_MUX; + +/** + The CNVI_CONFIG block describes the expected configuration of the CNVi I= P. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This option allows for automatic detection of Connectivity Solution. + Auto Detection assumes that CNVi will be enabled when available; + Disable allows for disabling CNVi. + CnviModeDisabled =3D Disabled, + CnviModeAuto =3D Auto Detection + **/ + UINT32 Mode : 1; + UINT32 BtCore : 1; ///< The option to turn ON or OFF the= BT Core. 0: Disabled, 1: Enabled + /** + The option to enable or disable BT Audio Offload. + 0: Disabled, 1: Enabled + @note This feature only support with Intel(R) Wireless-AX 22560 + **/ + UINT32 BtAudioOffload : 1; + UINT32 RsvdBits : 29; + /** + CNVi PinMux Configuration + RESET#/CLKREQ to CRF, can have two alternative mappings, depending on = board routing requirements. + **/ + CNVI_PIN_MUX PinMux; +} CNVI_CONFIG; + +#pragma pack (pop) + +#endif // _CNVI_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/C= puDmiPreMemConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock= /CpuDmi/CpuDmiPreMemConfig.h new file mode 100644 index 0000000000..527febb0a4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPr= eMemConfig.h @@ -0,0 +1,86 @@ +/** @file + DMI policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_DMI_PREMEM_CONFIG_H_ +#define _CPU_DMI_PREMEM_CONFIG_H_ + +#include +#include + +#define DMI_CONFIG_REVISION 1 + +#define CPU_DMI_HWEQ_COEFFS_MAX 8 + +#pragma pack (push,1) +/// +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature +/// +typedef enum { + DmiAspmDisabled, + DmiAspmL0s, + DmiAspmL1, + DmiAspmL0sL1, + DmiAspmAutoConfig, + DmiAspmMax +} DMI_ASPM; + + +/** + The CPU_DMI_CONFIG block describes the expected configuration of the CPU= for DMI. + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + +/** + - Auto (0x0) : Maximum possible link speed (Default) + - Gen1 (0x1) : Limit Link to Gen1 Speed + - Gen2 (0x2) : Limit Link to Gen2 Speed CpuDmiPreMemConfig + - Gen3 (0x3) : Limit Link to Gen3 Speed + **/ + UINT8 DmiMaxLinkSpeed; + /** + (Test) DMI Equalization Phase 2 Enable Control + - Disabled (0x0) : Disable phase 2 + - Enabled (0x1) : Enable phase 2 + - Auto (0x2) : Use the current default method (Default) + **/ + UINT8 DmiGen3EqPh2Enable; + /** + (Test) Selects the method for performing Phase3 of Gen3 Equaliza= tion on DMI + - Auto (0x0) : Use the current default method (Default) + - HwEq (0x1) : Use Adaptive Hardware Equalization + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented i= n BIOS Reference Code) + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPre= set array for Phase1 AND Phase3 (Instead of just Phase1) + - Disabled (0x4) : Bypass Equalization Phase 3 + **/ + UINT8 DmiGen3EqPh3Method; + /** + (Test) Program DMI Gen3 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT8 DmiGen3ProgramStaticEq; + UINT8 DmiDeEmphasis; ///<= DeEmphasis control for DMI (-6 dB and -3.5 dB are the options) + UINT8 DmiAspm; + UINT8 DmiAspmCtrl; ///<= ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiA= spmAutoConfig + UINT8 DmiAspmL1ExitLatency; ///<= ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiA= spmAutoConfig + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///<= Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is def= ault for each lane + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///<= Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is def= ault for each lane + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///<= Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default f= or each lane + + /** + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15)= . This setting + has to be specified based upon platform design and must follow the guid= eline. Default is 12. + **/ + + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]; +} CPU_DMI_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_DMI_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieR= p/Gen4/CpuPcieConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBl= ock/CpuPcieRp/Gen4/CpuPcieConfig.h new file mode 100644 index 0000000000..f18cd0352a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/= CpuPcieConfig.h @@ -0,0 +1,498 @@ +/** @file + Pcie root port policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PCIE_CONFIG_H_ +#define _CPU_PCIE_CONFIG_H_ + +#include +#include +#include +#include +#include + +#pragma pack(push, 1) + +#define CPU_PCIE_PEI_PREMEM_CONFIG_REVISION 1 +#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 4 + +/** + Making any setup structure change after code frozen + will need to maintain backward compatibility, bump up + structure revision and update below history table\n + Revision 1: - Initial version. + Revision 2: - Add Gen3TxOverride and Gen4TxOverride + Revision 3: - Deprecate Dekel Suqelch Workaround Setup Variable + Revision 4: - Add FOMS Control Policy Setup Variable + Revision 5: - Add Gen3HwEqOverride and Gen4HwEqOverride + Revision 6: - Align revision with CPU_PCIE_RP_CONFIG_REVISION va= lue +**/ + +#define CPU_PCIE_RP_CONFIG_REVISION 6 + +#define L0_SET BIT0 +#define L1_SET BIT1 + + + + +/** + PCI Express and DMI controller configuration\n + @note Optional. These policies will be ignored if there is no PEG = port present on board. + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///<= Offset 0-27 Config Block Header + /** + Offset 28:0 : + (Test) DMI Link Speed Control + - Auto (0x0) : Maximum possible link speed (Default) + - Gen1 (0x1) : Limit Link to Gen1 Speed + - Gen2 (0x2) : Limit Link to Gen2 Speed + - Gen3 (0x3) : Limit Link to Gen3 Speed + **/ + UINT32 DmiMaxLinkSpeed : 2; + /** + Offset 28:2 : + (Test) DMI Equalization Phase 2 Enable Control + - Disabled (0x0) : Disable phase 2 + - Enabled (0x1) : Enable phase 2 + - Auto (0x2) : Use the current default method (Default) + **/ + UINT32 DmiGen3EqPh2Enable : 2; + /** + Offset 28:4 : + (Test) Selects the method for performing Phase3 of Gen3 Equaliza= tion on DMI + - Auto (0x0) : Use the current default method (Default) + - HwEq (0x1) : Use Adaptive Hardware Equalization + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented i= n BIOS Reference Code) + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPre= set array for Phase1 AND Phase3 (Instead of just Phase1) + - Disabled (0x4) : Bypass Equalization Phase 3 + **/ + UINT32 DmiGen3EqPh3Method : 3; + /** + Offset 28:7 : + (Test) Program DMI Gen3 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT32 DmiGen3ProgramStaticEq : 1; + UINT32 RsvdBits0 : 24; ///= < Offset 28:8 :Reserved for future use + + /** + Offset 32:0 : + Select when PCIe ASPM programming will happen in relation to the Oprom + - Before (0x0) : Do PCIe ASPM programming before Oprom. (Default) + - After (0x1) : Do PCIe ASPM programming after Oprom. This will = require an SMI handler to save/restore ASPM settings. + **/ + UINT32 InitPcieAspmAfterOprom : 1; + UINT32 RsvdBits1 : 31; ///< Offset 32:1 :Reserved= for future use + + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///<= Offset 36 Used for programming DMI Gen3 preset values per lane. Range: 0-9= , 8 is default for each lane + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///<= Offset 40/44 Used for programming DMI Gen3 preset values per lane. Range: = 0-9, 7 is default for each lane + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///<= Offset 44/52 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2= is default for each lane + /** + Offset 48/60 : + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15)= . This setting + has to be specified based upon platform design and must follow the guid= eline. Default is 12. + **/ + + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]; + + UINT8 DmiDeEmphasis; ///<= Offset 64 This field is used to describe the DeEmphasis control for DMI (-= 6 dB and -3.5 dB are the options) + UINT8 Rsvd0[3]; ///<= Offset 65 +} PCIE_PEI_PREMEM_CONFIG; + + +/** + CPU PCIe Root Port Pre-Memory Configuration + Contains Root Port settings and capabilities + Revision 1: - Initial version. + Revision 2: - Adding Dekel Suqelch Workaround Setup Variable + Revision 3: - Deprecate Dekel Suqelch Workaround Setup Variable + Revision 4: - Adding CDR Relock Setup Variable +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config= Block Header + /** + Root Port enabling mask. + Bit0 presents RP1, Bit1 presents RP2, and so on. + 0: Disable; 1: Enable. + **/ + UINT32 RpEnabledMask; + /** + Assertion on Link Down GPIOs + - Disabled (0x0) : Disable assertion on Link Down GPIOs(Default) + - Enabled (0x1) : Enable assertion on Link Down GPIOs + **/ + UINT8 LinkDownGpios; + /** + Enable ClockReq Messaging + - Disabled (0x0) : Disable ClockReq Messaging(Default) + - Enabled (0x1) : Enable ClockReq Messaging + **/ + UINT8 ClkReqMsgEnable; + /** + Dekel Recipe Workaround + 2 + 1=3DMinimal, 9=3DMaximum, + **/ + UINT8 DekelSquelchWa; // Deprecated variable + UINT8 Rsvd0[1]; + /** + Determines each PCIE Port speed capability. + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED) + **/ + UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS]; + /** + To Enable/Disable CDR Relock + 0: Disable; 1: Enable + **/ + UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS]; + /** + This policy is used while programming DEKEL Recipe + 0: Disable; 1: Enable + **/ + UINT8 Xl1el[CPU_PCIE_MAX_ROOT_PORTS]; + +} CPU_PCIE_RP_PREMEM_CONFIG; + +typedef enum { + CpuPcieOverrideDisabled =3D 0, + CpuPcieL1L2Override =3D 0x01, + CpuPcieL1SubstatesOverride =3D 0x02, + CpuPcieL1L2AndL1SubstatesOverride =3D 0x03, + CpuPcieLtrOverride =3D 0x04 +} CPU_PCIE_OVERRIDE_CONFIG; + +/** + PCIe device table entry entry + + The PCIe device table is being used to override PCIe device ASPM setting= s. + To take effect table consisting of such entries must be instelled as PPI + on gPchPcieDeviceTablePpiGuid. + Last entry VendorId must be 0. +**/ +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card= ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Exp= ress card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Expr= ess card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: CPU= _PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideC= onfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (se= e: CPU_PCIE_OVERRIDE_CONFIG). + /** + The L1Substates Capability Offset Override. (applicable if bit 2 is se= t in OverrideConfig) + This field can be zero if only the L1 Substate value is going to be ov= erride. + **/ + UINT16 L1SubstatesCapOffset; + /** + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideCo= nfig) + Set to zero then the L1 Substate Capability [3:0] is ignored, and only= L1s values are override. + Only bit [3:0] are applicable. Other bits are ignored. + **/ + UINT8 L1SubstatesCapMask; + /** + L1 Substate Port Common Mode Restore Time Override. (applicable if bit= 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sCommonModeRestoreTime; + /** + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnScale; + /** + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnValue; + + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be mul= tiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be= multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 NonSnoopLatency; + + /** + Forces LTR override to be permanent + The default way LTR override works is: + rootport uses LTR override values provided by BIOS until connected d= evice sends an LTR message, then it will use values from the message + This settings allows force override of LTR mechanism. If it's enabled,= then: + rootport will use LTR override values provided by BIOS forever; LTR = messages sent from connected device will be ignored + **/ + UINT8 ForceLtrOverride; + UINT8 Reserved[3]; +} CPU_PCIE_DEVICE_OVERRIDE; + +enum CPU_PCIE_SPEED { + CpuPcieAuto, + CpuPcieGen1, + CpuPcieGen2, + CpuPcieGen3, + CpuPcieGen4, + CpuPcieGen5 +}; + +/// +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature +/// +typedef enum { + CpuPcieAspmDisabled, + CpuPcieAspmL0s, + CpuPcieAspmL1, + CpuPcieAspmL0sL1, + CpuPcieAspmAutoConfig, + CpuPcieAspmMax +} CPU_PCIE_ASPM_CONTROL; + +/** + Refer to SA EDS for the SA implementation values corresponding + to below PCI-E spec defined ranges +**/ +typedef enum { + CpuPcieL1SubstatesDisabled, + CpuPcieL1SubstatesL1_1, + CpuPcieL1SubstatesL1_1_2, + CpuPcieL1SubstatesMax +} CPU_PCIE_L1SUBSTATES_CONTROL; + +enum CPU_PCIE_MAX_PAYLOAD { + CpuPcieMaxPayload128 =3D 0, + CpuPcieMaxPayload256, + CpuPcieMaxPayload512, + CpuPcieMaxPayloadMax +}; + +enum CPU_PCIE_COMPLETION_TIMEOUT { + CpuPcieCompletionTO_Default, + CpuPcieCompletionTO_50_100us, + CpuPcieCompletionTO_1_10ms, + CpuPcieCompletionTO_16_55ms, + CpuPcieCompletionTO_65_210ms, + CpuPcieCompletionTO_260_900ms, + CpuPcieCompletionTO_1_3P5s, + CpuPcieCompletionTO_4_13s, + CpuPcieCompletionTO_17_64s, + CpuPcieCompletionTO_Disabled +}; + + +enum CPU_PCIE_GEN3_PRESET_COEFF_SELECTION { + CpuPcieGen3PresetSelection, + CpuPcieGen3CoefficientSelection +}; + +enum CPU_PCIE_GEN4_PRESET_COEFF_SELECTION { + CpuPcieGen4PresetSelection, + CpuPcieGen4CoefficientSelection +}; + +typedef enum { + CpuPcieEqDefault =3D 0, ///< @deprecated since revision 3. Behaves= as PchPcieEqHardware. + CpuPcieEqHardware =3D 1, ///< Hardware equalization + CpuPcieEqStaticCoeff =3D 4 ///< Fixed equalization (requires Coeffici= ent settings per lane) +} CPU_PCIE_EQ_METHOD; + + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 PegGen3RootPortPreset; ///< (Test) Us= ed for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is defaul= t for each lane + UINT8 PegGen3EndPointPreset; ///< (Test) Us= ed for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is defaul= t for each lane + UINT8 PegGen3EndPointHint; ///< (Test) Hi= nt value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for = each lane + UINT8 PegGen4RootPortPreset; ///< (Test) Us= ed for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is defaul= t for each lane + UINT8 PegGen4EndPointPreset; ///< (Test) Us= ed for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is defaul= t for each lane + UINT8 PegGen4EndPointHint; ///< (Test) Hi= nt value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for = each lane +} CPU_PCIE_EQ_LANE_PARAM; + +/** + The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each= CPU PCIe root port. +**/ +typedef struct { + + UINT32 ExtSync : 1; ///< Indicate whether th= e extended synch is enabled. 0: Disable; 1: Enable. + UINT32 VcEnabled : 1; ///< Virtual Channel. 0:= Disable; 1: Enable + UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Ch= annel. 0: Disable; 1: Enable + UINT32 PeerToPeer : 1; ///< Peer to Peer Mode. = 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 28; ///< Reserved bits + /** + PCIe Gen4 Equalization Method + - HwEq (0x1) : Hardware Equalization (Default) + - StaticEq (0x2) : Static Equalization + **/ + UINT8 Gen4EqPh3Method; + UINT8 FomsCp; ///< FOM Score Board Con= trol Policy + UINT8 RsvdBytes0[2]; ///< Reserved bytes + + // + // Gen3 Equalization settings + // + UINT32 Gen3Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen3 Link Equalization. Used for al= l lanes. Default is 7. + UINT32 Gen3Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen3 Link Equalization. Used for a= ll lanes. Default is 7. + // + // Gen4 Equalization settings + // + UINT32 Gen4Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen4 Link Equalization. Used for al= l lanes. Default is 7. + UINT32 Gen4Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen4 Link Equalization. Used for a= ll lanes. Default is 7. + // + // Gen5 Equalization settings + // + UINT32 Gen5Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen5 Link Equalization. Used for al= l lanes. Default is 7. + UINT32 Gen5Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen5 Link Equalization. Used for a= ll lanes. Default is 7. + UINT32 RsvdBits1 : 8; ///< Reserved Bits + + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; = ///< (Test) Includes policies which are common to = both SA and PCH RootPort + +} CPU_PCIE_ROOT_PORT_CONFIG; + +typedef struct { + UINT8 PcieGen3PresetCoeffSelection; ///Revision 1< / b>: + -Initial version. + Revision 2: + - SlotSelection policy added + Revision 3 + - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq + Revision 4: + - Deprecating SetSecuredRegisterLock + Revision 5: + - Adding Serl +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config = Block Header + /// + /// These members describe the configuration of each SA PCIe root port. + /// + CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS]; + /// + /// Gen3 Equalization settings for physical PCIe lane, index 0 represent= s PCIe lane 1, etc. + /// Corresponding entries are used when root port EqPh3Method is PchPcie= EqStaticCoeff (default). + /// + CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE]; + /// + /// List of coefficients used during equalization (applicable to both so= ftware and hardware EQ) + /// + PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX= ]; // Deprecated Policy + + PCIE_COMMON_CONFIG PcieCommonConfig; /// < (Test) Includes policies which are common to both SA and PCH PCIe + + UINT32 FiaProgramming : 1; /// < Skip Fia Conf= iguration and lock if enable + /// + /// This member describes whether the PCI Express Clock Gating for each = root port + /// is enabled by platform modules. 0: Disable; 1: Enable. + /// + UINT32 ClockGating : 1; + /// + /// This member describes whether the PCI Express Power Gating for each = root port + /// is enabled by platform modules. 0: Disable; 1: Enable. + /// + UINT32 PowerGating : 1; + // Deprecated Policy + /** + (Test) Program PEG Gen3 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT32 PegGen3ProgramStaticEq : 1; + + // Deprecated Policy + /** + (Test) Program PEG Gen4 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT32 PegGen4ProgramStaticEq : 1; + /** + (Test) Cpu Pcie Secure Register Lock + - Disabled (0x0) + - Enabled (0x1) + **/ + UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy + /// + /// This member allows to select between the PCI Express M2 or CEMx4 slo= t 1: PCIe M2; 0: CEMx4 slot. + /// + UINT32 SlotSelection : 1; + /// + /// Set/Clear Serl(Secure Equalization Register Lock) + /// + UINT32 Serl : 1; + + UINT32 RsvdBits0 : 24; + + /** + PCIe device override table + The PCIe device table is being used to override PCIe device ASPM setti= ngs. + This is a pointer points to a 32bit address. And it's only used in Pos= tMem phase. + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. + Last entry VendorId must be 0. + The prototype of this policy is: + CPU_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr; + **/ + UINT32 PcieDeviceOverrideTablePtr; + CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS]; + PCIE_COMMON_CONFIG2 PcieCommonConfig2; +} CPU_PCIE_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_PCIE_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConf= ig.h new file mode 100644 index 0000000000..445642da1f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h @@ -0,0 +1,72 @@ +/** @file + Dci policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _DCI_CONFIG_H_ +#define _DCI_CONFIG_H_ + +#define DCI_PREMEM_CONFIG_REVISION 2 +extern EFI_GUID gDciPreMemConfigGuid; + +#pragma pack (push,1) + +typedef enum { + DciDbcDisabled =3D 0x0, + DciDbcUsb2 =3D 0x1, + DciDbcUsb3 =3D 0x2, + DciDbcBoth =3D 0x3, + DciDbcNoChange =3D 0x4, + DciDbcMax +} DCI_DBC_MODE; + +typedef enum { + Usb3TcDbgDisabled =3D 0x0, + Usb3TcDbgEnabled =3D 0x1, + Usb3TcDbgNoChange =3D 0x2, + Usb3TcDbgMax +} DCI_USB3_TYPE_C_DEBUG_MODE; + +/** + The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Con= nection Interface (DCI) + + Revision 1: + - Initial version. + Revision 2: + - Added DciModphyPg + - change to use data in byte unit rather than bit-field +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + DCI enable. + Determine if to enable DCI debug from host. + 0:Disabled; 1:Enabled + **/ + UINT8 DciEn; + /** + USB DbC enable mode. + Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set USB3D= BCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value + Refer to definition of DCI_USB_DBC_MODE for supported settings. + 0:Disabled; 1:USB2; 2:USB3; 3:Both; 4:No Change + **/ + UINT8 DciDbcMode; + /** + Enable Modphy power gate when DCI is enable. It must be disabled for 4= -wire DCI OOB. Set default to HW default : Disabled + 0:Disabled; 1:Enabled + **/ + UINT8 DciModphyPg; + /** + USB3 Type-C UFP2DFP kenel / platform debug support. No change will do = nothing to UFP2DFP configuration. + When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP= (downstream-facing port) for first connection. + It must be enabled for USB3 kernel(kernel mode debug) and platform deb= ug(DFx, DMA, Trace) over UFP Type-C receptacle. + Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported setting= s. + 0:Disabled; 1:Enabled; 2:No Change + **/ + UINT8 DciUsb3TypecUfpDbg; +} PCH_DCI_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _DCI_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/Esp= iConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/Espi= Config.h new file mode 100644 index 0000000000..260b582702 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig= .h @@ -0,0 +1,61 @@ +/** @file + Espi policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _ESPI_CONFIG_H_ +#define _ESPI_CONFIG_H_ + +#define ESPI_CONFIG_REVISION 2 +extern EFI_GUID gEspiConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to ESPI. + + Revision 1: + - Initial revision + Revision 2: + - Added LockLinkConfiguration field to config block +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range + specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI). + 0: FALSE, 1: TRUE + **/ + UINT32 LgmrEnable : 1; + /** + eSPI Master and Slave BME settings. + When TRUE, then the BME bit enabled in eSPI Master and Slave. + 0: FALSE, 1: TRUE + **/ + UINT32 BmeMasterSlaveEnabled : 1; + /** + Master HOST_C10 (Virtual Wire) to Slave Enable (VWHC10OE) + 0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is ign= ored) + 1b: Enable HOST_C10 reporting to Slave via eSPI Virtual Wire (upon rec= eiving a HOST_C10 indication from PMC) + **/ + UINT32 HostC10ReportEnable : 1; + /** + eSPI Link Configuration Lock (SBLCL) + If set to TRUE then communication through SET_CONFIG/GET_CONFIG + to eSPI slaves addresses from range 0x0 - 0x7FF + 1: TRUE, 0: FALSE + **/ + UINT32 LockLinkConfiguration : 1; + /** + Hardware Autonomous Enable (HAE) + If set to TRUE, then the IP may request a PG whenever it is idle + **/ + UINT32 EspiPmHAE : 1; + UINT32 RsvdBits : 27; ///< Reserved bits +} PCH_ESPI_CONFIG; + +#pragma pack (pop) + +#endif // _ESPI_CONFIG_H_ + diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/Fiv= rConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/Fivr= Config.h new file mode 100644 index 0000000000..0df2755280 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig= .h @@ -0,0 +1,170 @@ +/** @file + PCH FIVR policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _FIVR_CONFIG_H_ +#define _FIVR_CONFIG_H_ + +#define FIVR_CONFIG_REVISION 1 +extern EFI_GUID gFivrConfigGuid; + +#pragma pack (push,1) + +/** + Rail support in S0ix and Sx + Settings other than FivrRailDisabled can be OR'ed +**/ +typedef enum { + FivrRailDisabled =3D 0, + FivrRailInS0i1S0i2 =3D BIT0, + FivrRailInS0i3 =3D BIT1, + FivrRailInS3 =3D BIT2, + FivrRailInS4 =3D BIT3, + FivrRailInS5 =3D BIT4, + FivrRailInS0ix =3D FivrRailInS0i1S0i2 | FivrRailInS0i3, + FivrRailInSx =3D FivrRailInS3 | FivrRailInS4 | FivrRailInS5, + FivrRailAlwaysOn =3D FivrRailInS0ix | FivrRailInSx +} FIVR_RAIL_SX_STATE; + +typedef enum { + FivrRetentionActive =3D BIT0, + FivrNormActive =3D BIT1, + FivrMinActive =3D BIT2, + FivrMinRetention =3D BIT3 +} FIVR_RAIL_SUPPORTED_VOLTAGE; + +/** + Structure for V1p05/Vnn VR rail configuration +**/ +typedef struct { + /** + Mask to enable the usage of external VR rail in specific S0ix or Sx st= ates + Use values from FIVR_RAIL_SX_STATE + The default is FivrRailDisabled. + **/ + UINT32 EnabledStates : 5; + + /** + VR rail voltage value that will be used in S0i2/S0i3 states. + This value is given in 2.5mV increments (0=3D0mV, 1=3D2.5mV, 2=3D5mV..= .) + The default for Vnn is set to 420 - 1050 mV. + **/ + UINT32 Voltage : 11; + /** + @deprecated + THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD + VR rail Icc Max Value + Granularity of this setting is 1mA and maximal possible value is 500mA + The default is 0mA . + **/ + UINT32 IccMax : 8; + + /** + This register holds the control hold off values to be used when + changing the rail control for external bypass value in us + **/ + UINT32 CtrlRampTmr : 8; + + /** + Mask to set the supported configuration in VR rail. + Use values from FIVR_RAIL_SUPPORTED_VOLTAGE + **/ + UINT32 SupportedVoltageStates : 4; + + /** + VR rail Icc Maximum Value + Granularity of this setting is 1mA and maximal possible value is 500mA + The default is 0mA . + **/ + UINT32 IccMaximum : 16; + + UINT32 RsvdBits1 : 12; + +} FIVR_EXT_RAIL_CONFIG; + + +/** + Structure for VCCIN_AUX voltage rail configuration +**/ +typedef struct { + /** + Transition time in microseconds from Low Current Mode Voltage to High Cu= rrent Mode Voltage. + Voltage transition time required by motherboard voltage regulator when P= CH changes + the VCCIN_AUX regulator set point from the low current mode voltage and = high current mode voltage. + This field has 1us resolution. + When value is 0 PCH will not transition VCCIN_AUX to low current mode vo= ltage. + The default is 0xC . + **/ + UINT8 LowToHighCurModeVolTranTime; + + /** + Transition time in microseconds from Retention Mode Voltage to High Curr= ent Mode Voltage. + Voltage transition time required by motherboard voltage regulator when P= CH changes + the VCCIN_AUX regulator set point from the retention mode voltage to hig= h current mode voltage. + This field has 1us resolution. + When value is 0 PCH will not transition VCCIN_AUX to retention voltage. + The default is 0x36 . + **/ + UINT8 RetToHighCurModeVolTranTime; + + /** + Transition time in microseconds from Retention Mode Voltage to Low Curre= nt Mode Voltage. + Voltage transition time required by motherboard voltage regulator when P= CH changes + the VCCIN_AUX regulator set point from the retention mode voltage to low= current mode voltage. + This field has 1us resolution. + When value is 0 PCH will not transition VCCIN_AUX to retention voltage. + The default is 0x2B . + **/ + UINT8 RetToLowCurModeVolTranTime; + UINT8 RsvdByte1; + /** + Transition time in microseconds from Off (0V) to High Current Mode Volta= ge. + Voltage transition time required by motherboard voltage regulator when P= CH changes + the VCCIN_AUX regulator set point from 0V to the high current mode volta= ge. + This field has 1us resolution. + 0 =3D Transition to 0V is disabled + Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on + in all S0 & Sx power states after initial start up on G3 exit + The default is 0x96 . + **/ + UINT32 OffToHighCurModeVolTranTime : 11; + UINT32 RsvdBits1 : 21; +} FIVR_VCCIN_AUX_CONFIG; + +/** + The PCH_FIVR_CONFIG block describes FIVR settings. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + External V1P05 VR rail configuration. + **/ + FIVR_EXT_RAIL_CONFIG ExtV1p05Rail; + /** + External Vnn VR rail configuration. + **/ + FIVR_EXT_RAIL_CONFIG ExtVnnRail; + /** + Additional External Vnn VR rail configuration that will get applied + in Sx entry SMI callback. Required only if External Vnn VR + needs different settings for Sx than those specified in ExtVnnRail. + **/ + FIVR_EXT_RAIL_CONFIG ExtVnnRailSx; + /** + VCCIN_AUX voltage rail configuration. + **/ + FIVR_VCCIN_AUX_CONFIG VccinAux; + + /** + Enable/Disable FIVR Dynamic Power Management + Default is 1 . + **/ + UINT32 FivrDynPm : 1; + UINT32 RsvdBits2 : 31; +} PCH_FIVR_CONFIG; + +#pragma pack (pop) + +#endif // _FIVR_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConf= ig.h new file mode 100644 index 0000000000..cb9411f9e8 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h @@ -0,0 +1,33 @@ +/** @file + Gigabit Ethernet policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GBE_CONFIG_H_ +#define _GBE_CONFIG_H_ + +#define GBE_CONFIG_REVISION 1 +extern EFI_GUID gGbeConfigGuid; + +#pragma pack (push,1) + +/** + PCH intergrated GBE controller configuration settings. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Determines if enable PCH internal GBE, 0: Disable; 1: Enable. + When Enable is changed (from disabled to enabled or from enabled to di= sabled), + it needs to set LAN Disable regsiter, which might be locked by FDSWL r= egister. + So it's recommendated to issue a global reset when changing the status= for PCH Internal LAN. + **/ + UINT32 Enable : 1; + UINT32 LtrEnable : 1; ///< 0: Disable; 1: Enable LTR cap= abilty of PCH internal LAN. + UINT32 RsvdBits0 : 30; ///< Reserved bits +} GBE_CONFIG; + +#pragma pack (pop) + +#endif // _GBE_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConf= ig.h new file mode 100644 index 0000000000..87649253c6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h @@ -0,0 +1,31 @@ +/** @file + Policy definition for GNA Config Block + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GNA_CONFIG_H_ +#define _GNA_CONFIG_H_ +#pragma pack(push, 1) + +#define GNA_CONFIG_REVISION 1 +/** + GNA config block for configuring GNA.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 C= onfig Block Header + /** + Offset 28:0 + This policy enables the GNA Device (SA Device 8) if supported. + If FALSE, all other policies in this config block will be ignored. + 1=3DTRUE; + 0=3DFALSE. + **/ + UINT32 GnaEnable : 1; + UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved f= or future use +} GNA_CONFIG; +#pragma pack(pop) + +#endif // _GNA_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/Gpi= oDevConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/G= pioDevConfig.h new file mode 100644 index 0000000000..1a724f14da --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevCon= fig.h @@ -0,0 +1,37 @@ +/** @file + GPIO device policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GPIO_DEV_CONFIG_H_ +#define _GPIO_DEV_CONFIG_H_ + +extern EFI_GUID gGpioDxeConfigGuid; + +#define GPIO_DXE_CONFIG_REVISION 1 + +#pragma pack (push,1) + +/** + This structure contains the DXE policies which are related to GPIO devic= e. + + Revision 1: + - Inital version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + If GPIO ACPI device is not used by OS it can be hidden. In such case + no other device exposed to the system can reference GPIO device in one + of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors. + 0: Disable; 1: Enable + **/ + UINT32 HideGpioAcpiDevice : 1; + UINT32 RsvdBits : 31; ///< Reserved bits + +} GPIO_DXE_CONFIG; + +#pragma pack (pop) + +#endif // _GPIO_DEV_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics= /Gen12/GraphicsConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigB= lock/Graphics/Gen12/GraphicsConfig.h new file mode 100644 index 0000000000..c3b134b830 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/= GraphicsConfig.h @@ -0,0 +1,211 @@ +/** @file + Policy definition for Internal Graphics Config Block. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _GRAPHICS_CONFIG_H_ +#define _GRAPHICS_CONFIG_H_ +#pragma pack(push, 1) + +#define GRAPHICS_PEI_PREMEM_CONFIG_REVISION 3 +#define GRAPHICS_PEI_CONFIG_REVISION 7 +#define GRAPHICS_DXE_CONFIG_REVISION 1 + +#define DDI_DEVICE_NUMBER 4 +#define MAX_BCLM_ENTRIES 20 + + +// +// DDI defines +// +typedef enum { + DdiDisable =3D 0x00, + DdiDdcEnable =3D 0x01, +} DDI_DDC_TBT_VAL; + +typedef enum { + DdiHpdDisable =3D 0x00, + DdiHpdEnable =3D 0x01, +} DDI_HPD_VAL; + +typedef enum { + DdiPortDisabled =3D 0x00, + DdiPortEdp =3D 0x01, + DdiPortMipiDsi =3D 0x02, +} DDI_PORT_SETTINGS; + +/** + This structure configures the Native GPIOs for DDI port per VBT settings= . +**/ +typedef struct { + UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings= must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPor= tA, DdiPortEdp - Set DdiPortA to eDP, DdiPortMipiDsi - Set DdiPortA = to MIPI DSI + UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings= must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPor= tB, DdiPortEdp - Set DdiPortB to eDP, DdiPortMipiDsi - Set DdiPortB = to MIPI DSI + UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - En= able HPD + UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD + UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enabl= e DDC + UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC + UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC +} DDI_CONFIGURATION; + +/** + This Configuration block is to configure GT related PreMem data/variable= s.\n + Revision 1: + - Initial version. + Revision 2: + - Added DfdRestoreEnable. + Revision 3: + - Added DdiConfiguration. + Revision 4: + - Added GmAdr64 and made GmAdr obselete +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config = Block Header + /** + Offset 28 + Selection of the primary display device: 0=3DiGFX, 1=3DPEG, 2=3DPCIe G= raphics on PCH, 3=3DAUTO, 4=3DSwitchable Graphics\n + When AUTO mode selected, the priority of display devices is: PCIe Grap= hics on PCH > PEG > iGFX + **/ + UINT8 PrimaryDisplay; + /** + Offset 29 + Intel Gfx Support. It controls enabling/disabling iGfx device. + When AUTO mode selected, iGFX will be turned off when external graphic= s detected. + If FALSE, all other polices can be ignored. + 2 =3D AUTO; + 0 =3D FALSE; + 1 =3D TRUE. + **/ + UINT8 InternalGraphics; + /** + Offset 30 + Pre-allocated memory for iGFX\n + 0 =3D 0MB,1 or 247 =3D 32MB,\n + 2 =3D 64MB,\n + 240 =3D 4MB, 241 =3D 8MB,\n + 242 =3D 12MB, 243 =3D 16MB,\n + 244 =3D 20MB, 245 =3D 24MB,\n + 246 =3D 28MB, 248 =3D 36MB,\n + 249 =3D 40MB, 250 =3D 44MB,\n + 251 =3D 48MB, 252 =3D 52MB,\n + 253 =3D 56MB, 254 =3D 60MB,\n + Note: enlarging pre-allocated memory for iGFX may need to reduce Mm= ioSize because of 4GB boundary limitation + **/ + UINT16 IgdDvmt50PreAlloc; + UINT8 PanelPowerEnable; ///< Offset 32 :(Test) = Control for enabling/disabling VDD force bit (Required only for early enabl= ing of eDP panel): 0=3DFALSE, 1=3DTRUE + UINT8 ApertureSize; ///< Offset 33 :Graphics apert= ure size (256MB is the recommended size as per BWG) : 0=3D128MB, 1=3D256= MB, 3=3D512MB, 7=3D1024MB, 15=3D2048MB. + UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support O= n/Off: 0=3DFALSE, 1=3DTRUE + UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region si= ze: 0=3D32MB, 1=3D288MB, 2=3D544MB, 3=3D800MB, 4=3D1056MB + UINT8 DismSize; ///< Offset 36 :DiSM Size for = 2LM Sku: 0=3D0GB, 1=3D1GB, 2=3D2GB, 3=3D3GB, 4=3D4GB, 5=3D5GB, 6=3D6= GB, 7=3D7GB + UINT8 DfdRestoreEnable; ///< Offset 37 :Display memory= map programming for DFD Restore 0- Disable, 1- Enable + UINT16 GttSize; ///< Offset 38 :Selection of i= GFX GTT Memory size: 1=3D2MB, 2=3D4MB, 3=3D8MB + /** + Offset 40 + Temp Address of System Agent GTTMMADR: Default is 0xAF000000 + **/ + UINT32 GttMmAdr; + UINT32 GmAdr; ///< Offset 44 Obsolete not to= be used, use GmAdr64 + DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI configurati= on, need to match with VBT settings. + + UINT8 GtClosEnable; ///< Offset 50 Gt ClOS + UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 = bytes of alignment + /** + Offset 58 + Temp Address of System Agent GMADR: Default is 0xB0000000 + **/ + UINT64 GmAdr64; +} GRAPHICS_PEI_PREMEM_CONFIG; + +/** + This configuration block is to configure IGD related variables used in P= ostMem PEI. + If Intel Gfx Device is not supported, all policies can be ignored. + Revision 1: + - Initial version. + Revision 2: + - Removed DfdRestoreEnable. + Revision 3: + - Removed DdiConfiguration. + Revision 4: + - Added new CdClock frequency + Revision 5: + - Added GT Chicket bits + Revision 6: + - Added LogoPixelHeight and LogoPixelWidth + Revision 7: + - Added SkipFspGop + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT8 RenderStandby; ///< Offset 28 :(Test)= This field is used to enable or disable RC6 (Render Standby): 0=3DFALSE, <= b>1=3DTRUE + UINT8 PmSupport; ///< Offset 29 :(Test)= IGD PM Support TRUE/FALSE: 0=3DFALSE, 1=3DTRUE + /** + Offset 30 + CdClock Frequency select\n + 0xFF =3D Auto. Max CdClock freq based on Reference Clk \n + 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 55= 2 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz + + **/ + UINT16 CdClock; + UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy = is used to enable/disable Intel Gfx PEIM.0- Disable, 1- Enable + UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy = is used to enable/disable CDynmax Clamping Feature (CCF) 1- Enable, = 0- Disable + UINT16 GtFreqMax; ///< Offset 34 : (Test) Max GT frequency limited by user in multiples of 50MHz: Default value whi= ch indicates normal frequency is 0xFF + UINT8 DisableTurboGt; ///< Offset 36 : This policy = is used to enable/disable DisableTurboGt 0- Disable, 1- Enable + UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD= clock initialization. 0- Disable, 1- Enable + UINT8 RC1pFreqEnable; ///< Offset 38 : This policy = is used to enable/disable RC1p Frequency. 0- Disable, 1- Enable + UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE= /FALSE: 0=3DFALSE, 1=3DTRUE + VOID* LogoPtr; ///< Offset 40 Address of Int= el Gfx PEIM Logo to be displayed + UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM= Logo Size + VOID* GraphicsConfigPtr; ///< Offset 48 Address of the= Graphics Configuration Table + VOID* BltBufferAddress; ///< Offset 52 Address of Blt= buffer for PEIM Logo use + UINT32 BltBufferSize; ///< Offset 56 The size for B= lt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of E= FI_GRAPHICS_OUTPUT_BLT_PIXEL) + UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chi= cket bits in GTTMMADR + 0xD00 BITS [3:1]. + UINT8 SkipFspGop; ///< Offset 61 This policy is= used to skip PEIM GOP in FSP.0- Use FSP provided GOP driver, 1- Ski= p FSP provided GOP driver + UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4= bytes alignment + UINT32 LogoPixelHeight; ///< Offset 64 Address of Log= oPixelHeight for PEIM Logo use + UINT32 LogoPixelWidth; ///< Offset 68 Address of Log= oPixelWidth for PEIM Logo use +} GRAPHICS_PEI_CONFIG; + +/** + This configuration block is to configure IGD related variables used in D= XE. + If Intel Gfx Device is not supported or disabled, all policies will be i= gnored. + The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config= Block Header + UINT32 Size; ///< Offset 28 - 31: Thi= s field gives the size of the GOP VBT Data buffer + EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: Thi= s field points to the GOP VBT data buffer + UINT8 PlatformConfig; ///< Offset 40: This fie= ld gives the Platform Configuration Information (0=3DPlatform is S0ix Capab= le for ULT SKUs only, 1=3DPlatform is not S0ix Capable, 2=3DForce Pl= atform is S0ix Capable for All SKUs) + UINT8 AlsEnable; ///< Offset 41: Ambient = Light Sensor Enable: 0=3DDisable, 2=3DEnable + UINT8 BacklightControlSupport; ///< Offset 42: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal + UINT8 IgdBootType; ///< Offset 43: IGD Boot= Type CMOS option: 0=3DDefault, 0x01=3DCRT, 0x04=3DEFP, 0x08=3DLFP, = 0x20=3DEFP3, 0x40=3DEFP2, 0x80=3DLFP2 + UINT32 IuerStatusVal; ///< Offset 44 - 47: Off= set 16 This field holds the current status of all the supported Ultrabook e= vents (Intel(R) Ultrabook Event Status bits) + CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This= field holds the GOP Driver Version. It is an Output Protocol and updated b= y the Silicon code + /** + Offset 80: IGD Panel Type CMOS option\n + 0=3DDefault, 1=3D640X480LVDS, 2=3D800X600LVDS, 3=3D1024X768LVDS= , 4=3D1280X1024LVDS, 5=3D1400X1050LVDS1\n + 6=3D1400X1050LVDS2, 7=3D1600X1200LVDS, 8=3D1280X768LVDS, 9=3D1680X1050= LVDS, 10=3D1920X1200LVDS, 13=3D1600X900LVDS\n + 14=3D1280X800LVDS, 15=3D1280X600LVDS, 16=3D2048X1536LVDS, 17=3D1366X76= 8LVDS + **/ + UINT8 IgdPanelType; + UINT8 IgdPanelScaling; ///< Offset 81: IGD Pane= l Scaling: 0=3DAUTO, 1=3DOFF, 6=3DForce scaling + UINT8 IgdBlcConfig; ///< Offset 82: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal + UINT8 IgdDvmtMemSize; ///< Offset 83: IGD DVMT= Memory Size: 1=3D128MB, 2=3D256MB, 3=3DMAX + UINT8 GfxTurboIMON; ///< Offset 84: IMON Cur= rent Value: 14=3DMinimal, 31=3DMaximum + UINT8 Reserved[3]; ///< Offset 85: Reserved= for DWORD alignment. + UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Back= light Brightness Level Duty cycle Mapping Table. +} GRAPHICS_DXE_CONFIG; +#pragma pack(pop) + +#endif // _GRAPHICS_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAu= dioConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdA= udioConfig.h new file mode 100644 index 0000000000..a2e0a65e45 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConf= ig.h @@ -0,0 +1,227 @@ +/** @file + HDAUDIO policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _HDAUDIO_CONFIG_H_ +#define _HDAUDIO_CONFIG_H_ + +#include +#include + +#define HDAUDIO_PREMEM_CONFIG_REVISION 2 +#define HDAUDIO_CONFIG_REVISION 1 +#define HDAUDIO_DXE_CONFIG_REVISION 1 + +extern EFI_GUID gHdAudioPreMemConfigGuid; +extern EFI_GUID gHdAudioConfigGuid; +extern EFI_GUID gHdAudioDxeConfigGuid; + +#pragma pack (push,1) + +/// +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of t= he Intel HD Audio feature. +/// + +#define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) (UINT32)((= UINT16)Vid | ((UINT16)Did << 16)) +#define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) (UINT32)((= UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16)) +#define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof (= VerbTable) - sizeof (HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32))) + +/// +/// Use this macro to create HDAUDIO_VERB_TABLE and populate size automati= cally +/// +#define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \ +{ \ + { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }= , \ + { __VA_ARGS__ } \ +} + + +/** + Azalia verb table header + Every verb table should contain this defined header and followed by azal= ia verb commands. +**/ +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matche= s any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs following the h= eader. +} HDA_VERB_TABLE_HEADER; + +#ifdef _MSC_VER +// +// Disable "zero-sized array in struct/union" extension warning. +// Used for neater verb table definitions. +// +#pragma warning (push) +#pragma warning (disable: 4200) +#endif +typedef struct { + HDA_VERB_TABLE_HEADER Header; + UINT32 Data[]; +} HDAUDIO_VERB_TABLE; +#ifdef _MSC_VER +#pragma warning (pop) +#endif + +typedef struct { + UINT32 ClkA; ///< Pin mux configuration. Refer to GPIO_*_M= UXING_DMIC*_CLKA_* + UINT32 ClkB; ///< Pin mux configuration. Refer to GPIO_*_M= UXING_DMIC*_CLKB_* + UINT32 Data; ///< Pin mux configuration. Refer to GPIO_*_M= UXING_DMIC*_DATA_* +} HDA_DMIC_PIN_MUX; + +/** + HD Audio Link Policies +**/ +typedef struct { + UINT32 Enable : 1; ///< HDA interface enable. When enabled related= pins will be switched to native mode: 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 31; + UINT8 SdiEnable[PCH_MAX_HDA_SDI]; ///< HDA SDI signal enable. When en= abled related SDI pins will be switched to appropriate native mode: 0: D= isable; 1: Enable + UINT8 Reserved[(4 - (PCH_MAX_HDA_SDI % 4)) % 4]; ///< Padding for SDI= enable table. +} HDA_LINK_HDA; + +/** + HD Audio DMIC Interface Policies +**/ +typedef struct { + UINT32 Enable : 1; ///< HDA DMIC interface enable= . When enabled related pins will be switched to native mode: 0: Disable<= /b>; 1: Enable. + UINT32 DmicClockSelect : 2; ///< DMIC link clock select: <= b>0: Both, 1: ClkA, 2: ClkB; default is "Both" + UINT32 RsvdBits0 : 29; + HDA_DMIC_PIN_MUX PinMux; ///< Pin mux configuration. +} HDA_LINK_DMIC; + +/** + HD Audio SSP Interface Policies +**/ +typedef struct { + UINT32 Enable : 1; ///< HDA SSP interface enable. When = enabled related pins will be switched to native mode: 0: Disable; 1:= Enable. + UINT32 RsvdBits0 : 31; +} HDA_LINK_SSP; + +/** + HD Audio SNDW Interface Policies +**/ +typedef struct { + UINT32 Enable : 1; ///< HDA SNDW interface enable. When= enabled related pins will be switched to native mode: 0: Disable; 1= : Enable. + UINT32 RsvdBits0 : 31; +} HDA_LINK_SNDW; + + +/** + This structure contains the policies which are related to HD Audio devic= e (cAVS). + + Revision 1: + - Inital version. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0: D= isable; 1: Enable + UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake in= itiated by a codec in Sx (eg by modem codec), 0: Disable; 1: Enable + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAU= DIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz + UINT32 RsvdBits0 : 26; ///< Reserved bits 0 + /** + Number of the verb table entry defined in VerbTablePtr. + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE st= ructure and verb command blocks. + **/ + UINT8 VerbTableEntryNum; + UINT8 Rsvd0[3]; ///< Reserved bytes, align to = multiple 4 + /** + Pointer to a verb table array. + This pointer points to 32bits address, and is only eligible and consum= ed in post mem phase. + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE st= ructure and verb command blocks. + The prototype of this is: + HDAUDIO_VERB_TABLE **VerbTablePtr; + **/ + UINT32 VerbTablePtr; +} HDAUDIO_CONFIG; + +/** + This structure contains the premem policies which are related to HD Audi= o device (cAVS). + + Revision 1: + - Inital version. + Revision 2: + - Add DmicClockSelect +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Enable : 1; ///< Intel HD Audio (Azalia) enab= lement: 0: Disable, 1: Enable + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; = 1: Enable + UINT32 VcType : 1; ///< Virtual Channel Type Select:= 0: VC0, 1: VC1 + /** + Universal Audio Architecture compliance for DSP enabled system: + 0: Not-UAA Compliant (Intel SST driver supported only), + 1: UAA Compliant (HDA Inbox driver or SST driver supported) + **/ + UINT32 DspUaaCompliance : 1; + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HD= AUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz + UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode (PCH_HDAUD= IO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: 16T + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconn= ection, 0: Not disconnected, enumerable; 1: Disconnected SDI, not en= umerable + UINT32 PowerGatingSupported : 1; ///< Power Gating supported: 0= : Not supported, 1: Supported + UINT32 RsvdBits : 19; ///< Reserved bits 0 + + /** + Audio Link Mode configuration bitmask. + Allows to configure enablement of the following interfaces: HDA-Link, = DMIC, SSP, SoundWire. + **/ + + HDA_LINK_HDA AudioLinkHda; ///< HDA-Link enablement: 0: Disa= ble; 1: Enable. + /** + DMIC link enablement: 0: Disable; 1: Enable. + DMIC0 LKF: Muxed with SNDW2/SNDW4. + **/ + HDA_LINK_DMIC AudioLinkDmic [2]; + /** + I2S/SSP link enablement: 0: Disable; 1: Enable. + SSP0/1 LKF: Muxed with HDA. + @note Since the I2S/SSP2 pin set contains pads which are also used for= CNVi purpose, enabling AudioLinkSsp2 + is exclusive with CNVi is present. + **/ + HDA_LINK_SSP AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM]; + /** + SoundWire link enablement: 0: Disable; 1: Enable. + SNDW2 LKF: Muxed with DMIC0/DMIC1. + SNDW3 LKF: Muxed with DMIC1. + SNDW4 LKF: Muxed with DMIC0. + **/ + HDA_LINK_SNDW AudioLinkSndw [PCH_MAX_HDA_SNDW_LINK_NUM]; + + + UINT16 ResetWaitTimer; ///< (Test) The delay t= imer after Azalia reset, the value is number of microseconds. Default is 600. + UINT8 Rsvd0[2]; ///< Reserved bytes, align to = multiple 4 + +} HDAUDIO_PREMEM_CONFIG; + +typedef struct { + UINT32 AutonomousClockStop : 1; ///< SoundWire1 link autonom= ous clock stop capability: 0: Disable; 1: Enable + UINT32 DataOnActiveIntervalSelect : 2; ///< SoundWire1 link data on= active interval select 0: 3 clock periods; 1: 4 clock periods; 2: 5= clock periods; 3: 6 clock periods + UINT32 DataOnDelaySelect : 1; ///< SoundWire1 link data on= delay select 0: 2 clock periods; 1: 3 clock periods + UINT32 RsvdBits1 : 28; ///< Reserved bits 1 +} HDAUDIO_SNDW_CONFIG; + +/** + This structure contains the DXE policies which are related to HD Audio d= evice (cAVS). + Revision 1: + - Inital version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + SNDW configuration for exposed via SNDW ACPI tables: + **/ + HDAUDIO_SNDW_CONFIG SndwConfig[PCH_MAX_HDA_SNDW_LINK_NUM]; + /** + Bitmask of supported DSP features: + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT In= tel HFP; [BIT6] - BT Intel A2DP + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel W= oV, 1: Windows Voice Activation + Default is zero. + **/ + UINT32 DspFeatureMask; +} HDAUDIO_DXE_CONFIG; + +#pragma pack (pop) + +#endif // _HDAUDIO_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBrid= ge/HostBridgeConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlo= ck/HostBridge/HostBridgeConfig.h new file mode 100644 index 0000000000..67335be92e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/Host= BridgeConfig.h @@ -0,0 +1,62 @@ +/** @file + Configurations for HostBridge + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _HOST_BRIDGE_CONFIG_H_ +#define _HOST_BRIDGE_CONFIG_H_ + +#include + +#define HOST_BRIDGE_PREMEM_CONFIG_REVISION 1 +#define HOST_BRIDGE_PEI_CONFIG_REVISION 1 + +extern EFI_GUID gHostBridgePeiPreMemConfigGuid; +extern EFI_GUID gHostBridgePeiConfigGuid; + +#pragma pack (push,1) + +/** + This configuration block describes HostBridge settings in PreMem.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT32 MchBar; ///< Offset 28 Address of Sys= tem Agent MCHBAR: 0xFEDC0000(TGL)/0xFED10000(RKL)/0xFEA80000(JSL) + UINT32 DmiBar; ///< Offset 32 Address of Sys= tem Agent DMIBAR: 0xFEDA0000 + UINT32 EpBar; ///< Offset 36 Address of Sys= tem Agent EPBAR: 0xFEDA1000 + UINT32 GdxcBar; ///< Offset 40 Address of Sys= tem Agent GDXCBAR: 0xFED84000 + UINT32 RegBar; ///< Offset 44 Address of Sys= tem Agent REGBAR: 0xFB000000 + UINT32 EdramBar; ///< Offset 48 Address of Sys= tem Agent EDRAMBAR: 0xFED80000 + /** + Offset 52 : + Size of reserved MMIO space for PCI devices\n + 0=3DAUTO, 512=3D512MB, 768=3D768MB, 1024=3D1024MB, 1280=3D1280M= B, 1536=3D1536MB, 1792=3D1792MB, + 2048=3D2048MB, 2304=3D2304MB, 2560=3D2560MB, 2816=3D2816MB, 3072=3D307= 2MB\n + When AUTO mode selected, the MMIO size will be calculated by required = MMIO size from PCIe devices detected. + **/ + UINT32 MmioSize; + UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (give= n positive value) or Decrease (given negative value) the Reserved MMIO size= when Dynamic Tolud/AUTO mode enabled (in MBs): 0=3Dno adjustment + UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disable= above 4GB MMIO resource support: 0=3DDisable, 1=3DEnable + UINT8 Reserved[3]; ///< Offset 61 Reserved for f= uture use. +} HOST_BRIDGE_PREMEM_CONFIG; + + +/** + This configuration block describes HostBridge settings in Post-Mem.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT8 Device4Enable; ///< Offser 28 :This policy i= s used to control enable or disable System Agent Thermal device (0,4,0). 0=3DFALSE, 1=3DTRUE. + UINT8 ChapDeviceEnable; ///< Offset 29 :(Test)= This policy is used to control enable or disable System Agent Chap device (= 0,7,0). 0=3DFALSE, 1=3DTRUE. + UINT8 SkipPamLock; ///< Offset 30 :To skip PAM r= egister locking. @note It is still recommended to set PCI Config space B0: = D0: F0: Offset 80h[0]=3D1 in platform code even Silicon code skipped this.\= n 0=3DAll PAM registers will be locked in Silicon code, 1=3DSkip loc= k PAM registers in Silicon code. + UINT8 EdramTestMode; ///< Offset 28 :EDRAM Test Mo= de. For EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, 2- ED= RAM HW Mode +} HOST_BRIDGE_PEI_CONFIG; + +#pragma pack (pop) + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGr= aphics/HybridGraphicsConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/C= onfigBlock/HybridGraphics/HybridGraphicsConfig.h new file mode 100644 index 0000000000..3f420aed48 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/= HybridGraphicsConfig.h @@ -0,0 +1,66 @@ +/** @file + Hybrid Graphics policy definitions + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _HYBRID_GRAPHICS_CONFIG_H_ +#define _HYBRID_GRAPHICS_CONFIG_H_ + +#define HYBRID_GRAPHICS_CONFIG_REVISION 2 + +#pragma pack(push, 1) +/// +/// GPIO Support +/// +typedef enum { + NotSupported =3D 0, + PchGpio, + I2CGpio, +} GPIO_SUPPORT; + +/// +/// CPU PCIe GPIO Data Structure +/// +typedef struct { + UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO + BOOLEAN Active; ///< Offset 1 0=3DActive Low; 1=3DActive High + UINT8 Rsvd0[2]; ///< Offset 2 Reserved + UINT32 GpioNo; ///< Offset 4 GPIO pad +} CPU_PCIE_GPIO_INFO; + +/** + CPU PCIE RTD3 GPIO Data Structure +**/ +typedef struct { + CPU_PCIE_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe = HLD RESET GPIO value and level information + CPU_PCIE_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe = PWR Enable GPIO value and level information + UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe= RTD3 Device Wake GPIO Number + UINT8 GpioSupport; ///< Offset 20 Depends on board design= the GPIO configuration may be different: 0=3DNot Supported, 1=3DPCH= Based, 2=3DI2C based + UINT8 Rsvd0[3]; ///< Offset 21 +} CPU_PCIE_RTD3_GPIO; + +/** + This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & R= oot Port. + Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3. + Revision 1: + - Initial version. + Revision 2: + - Add HgSlot Policy: PEG or PCH Slot Slection for Hybrid Graphics +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio; ///< Offset 28 RTD3 GPIOs use= d for PCIe + UINT8 RootPortIndex; ///< Offset 52 Root Port Inde= x number used for HG + UINT8 HgMode; ///< Offset 53 HgMode: 0= =3DDisabled, 1=3DHG Muxed, 2=3DHG Muxless, 3=3DPEG + UINT16 HgSubSystemId; ///< Offset 54 Hybrid Graphic= s Subsystem ID: 2212 + UINT16 HgDelayAfterPwrEn; ///< Offset 56 Dgpu Delay aft= er Power enable using Setup option: 0=3DMinimal, 1000=3DMaximum, 300=3D3= 00 microseconds + UINT16 HgDelayAfterHoldReset; ///< Offset 58 Dgpu Delay aft= er Hold Reset using Setup option: 0=3DMinimal, 1000=3DMaximum, 100=3D100= microseconds + CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio; ///< Offset 60 RTD3 GPIOs use= d for PCIe + CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio; ///< Offset 84 RTD3 GPIOs use= d for PCIe + CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio; ///< Offset 108 RTD3 GPIOs us= ed for PCIe + UINT8 HgSlot; ///< Offset 132 Slot selectio= n between PEG and PCH + UINT8 Rsvd0[3]; ///< Offset 133 Reserved Byte= s +} HYBRID_GRAPHICS_CONFIG; +#pragma pack(pop) +#endif // _HYBRID_GRAPHICS_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridSt= orage/HybridStorageConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Con= figBlock/HybridStorage/HybridStorageConfig.h new file mode 100644 index 0000000000..705fe43751 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/H= ybridStorageConfig.h @@ -0,0 +1,36 @@ +/** @file + Hybrid Storage policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _HYBRID_STORAGE_CONFIG_H_ +#define _HYBRID_STORAGE_CONFIG_H_ + +#include + +#define HYBRID_STORAGE_CONFIG_REVISION 1 + +extern EFI_GUID gHybridStorageConfigGuid; + +#pragma pack (push,1) + +/** + The HYBRID_STORAGE_CONFIG block describes the expected configuration for= Hybrid Storage device + + Revision 1: + - Init version +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Hybrid Storage Mode + 0: Disable, 1: Enable Dynamic Configuration + **/ + UINT8 HybridStorageMode; + UINT8 RsvdBytes[3]; +} HYBRID_STORAGE_CONFIG; + +#pragma pack (pop) + +#endif // _HYBRID_STORAGE_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConf= ig.h new file mode 100644 index 0000000000..a9275152f5 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h @@ -0,0 +1,34 @@ +/** @file + Integrated Error Handler policy. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IEH_CONFIG_H_ +#define _IEH_CONFIG_H_ + +#define IEH_MODE_BYPASS 0 +#define IEH_MODE_ENABLE 1 + +#define IEH_CONFIG_REVISION 1 +extern EFI_GUID gIehConfigGuid; + +#pragma pack (push,1) + +/** + The IEH_CONFIG block describes the expected configuration of the PCH + Integrated Error Handler. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + IEH mode 0: Bypass Mode; 1: Enable + **/ + UINT32 Mode : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} IEH_CONFIG; + +#pragma pack (pop) + +#endif // _IEH_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConf= ig.h new file mode 100644 index 0000000000..75a11e3052 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h @@ -0,0 +1,134 @@ +/** @file + ISH policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _ISH_CONFIG_H_ +#define _ISH_CONFIG_H_ + +#define ISH_PREMEM_CONFIG_REVISION 1 +#define ISH_CONFIG_REVISION 1 +extern EFI_GUID gIshPreMemConfigGuid; +extern EFI_GUID gIshConfigGuid; + +#pragma pack (push,1) + +/** + ISH GPIO settings +**/ +typedef struct { + /** + GPIO signals pin muxing settings. If signal can be enable only on a si= ngle pin + then this parameter should be set to 0. Refer to GPIO_*_MUXING_ISH_*x_= * in GpioPins*.h + for supported settings on a given platform + **/ + UINT32 PinMux; ///< GPIO Pin mux configuration. R= efer to GPIO_*_MUXING_ISH_*x_MOSI_* + /** + GPIO Pads Internal Termination. + For more information please see Platform Design Guide. + Check GPIO_ELECTRICAL_CONFIG for reference + **/ + UINT32 PadTermination; +} ISH_GPIO_CONFIG; + +/** + SPI signals settings. +**/ +typedef struct { + ISH_GPIO_CONFIG Mosi; ///< MOSI Pin configurati= on. + ISH_GPIO_CONFIG Miso; ///< MISO Pin configurati= on. + ISH_GPIO_CONFIG Clk; ///< CLK Pin configurati= on. + ISH_GPIO_CONFIG Cs[PCH_MAX_ISH_SPI_CS_PINS]; ///< CS Pin configurati= on. +} ISH_SPI_PIN_CONFIG; + + +/** + UART signals settings. +**/ +typedef struct { + ISH_GPIO_CONFIG Rx; ///< RXD Pin configuration. + ISH_GPIO_CONFIG Tx; ///< TXD Pin configuration. + ISH_GPIO_CONFIG Rts; ///< RTS Pin configuration. + ISH_GPIO_CONFIG Cts; ///< CTS Pin configuration. +} ISH_UART_PIN_CONFIG; + + +/** + I2C signals settings. +**/ +typedef struct { + ISH_GPIO_CONFIG Sda; ///< SDA Pin configuration. + ISH_GPIO_CONFIG Scl; ///< SCL Pin configuration. +} ISH_I2C_PIN_CONFIG; + + +/** + Struct contains GPIO pins assigned and signal settings of SPI +**/ +typedef struct { + UINT8 Enable; ///< ISH SPI GPIO= pins assigned: 0: False 1: True + UINT8 CsEnable[PCH_MAX_ISH_SPI_CS_PINS]; ///< ISH SPI CS p= ins assigned: 0: False 1: True + UINT16 RsvdField0; ///< Reserved fie= ld + ISH_SPI_PIN_CONFIG PinConfig; +} ISH_SPI; + + +/** + Struct contains GPIO pins assigned and signal settings of UART +**/ +typedef struct { + UINT32 Enable : 1; ///< ISH UART GPIO pins assigned= : 0: False 1: True + UINT32 RsvdBits0 : 31; ///< Reserved Bits + ISH_UART_PIN_CONFIG PinConfig; +} ISH_UART; + +/** + Struct contains GPIO pins assigned and signal settings of I2C +**/ +typedef struct { + UINT32 Enable : 1; ///< ISH I2C GPIO pins assigned:= 0: False 1: True + UINT32 RsvdBits0 : 31; ///< Reserved Bits + ISH_I2C_PIN_CONFIG PinConfig; +} ISH_I2C; + +/** + Struct contains GPIO pins assigned and signal settings of GP +**/ +typedef struct { + UINT32 Enable : 1; ///< ISH GP GPIO pins assigned: = 0: False 1: True + UINT32 RsvdBits0 : 31; ///< Reserved Bits + ISH_GPIO_CONFIG PinConfig; +} ISH_GP; + +/// +/// The ISH_CONFIG block describes Integrated Sensor Hub device. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + ISH_SPI Spi[PCH_MAX_ISH_SPI_CONTROLLERS]; + ISH_UART Uart[PCH_MAX_ISH_UART_CONTROLLERS]; + ISH_I2C I2c[PCH_MAX_ISH_I2C_CONTROLLERS]; + ISH_GP Gp[PCH_MAX_ISH_GP_PINS]; + + UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: = 0: False 1: True + UINT32 RsvdBits0 : 31; ///< Reserved Bits + +} ISH_CONFIG; + +/// +/// Premem Policy for Integrated Sensor Hub device. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + ISH Controler 0: Disable; 1: Enable. + For Desktop sku, the ISH POR should be disabled. 0:Disable . + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved Bits +} ISH_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _ISH_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/Int= erruptConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss= /InterruptConfig.h new file mode 100644 index 0000000000..7f6fa8675b --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptC= onfig.h @@ -0,0 +1,58 @@ +/** @file + Interrupt policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _INTERRUPT_CONFIG_H_ +#define _INTERRUPT_CONFIG_H_ + +#define INTERRUPT_CONFIG_REVISION 1 +extern EFI_GUID gInterruptConfigGuid; + +#pragma pack (push,1) + +// +// --------------------- Interrupts Config ------------------------------ +// +typedef enum { + PchNoInt, ///< No Interrupt Pin + PchIntA, + PchIntB, + PchIntC, + PchIntD +} PCH_INT_PIN; + +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and= interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see= PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} PCH_DEVICE_INTERRUPT_CONFIG; + +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 128 ///< Number of all PCH d= evices +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC regi= sters in ITSS +#define PCH_MAX_ITSS_IPC_REGS 4 ///< Number of IPC regis= ters in ITSS +#define PCH_MAX_ITSS_IRQ_NUM 120 ///< Maximum number of I= RQs + + +/// +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; = ///< Config Block Header + UINT8 NumOfDevIntConfig; = ///< Number of entries in DevIntConfig table + UINT8 Rsvd0[3]; = ///< Reserved bytes, align to multiple 4. + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFI= G]; ///< Array which stores PCH devices interrupts settings + UINT8 GpioIrqRoute; = ///< Interrupt routing for GPIO. Default is 14. + UINT8 SciIrqSelect; = ///< Interrupt select for SCI. Default is 9. + UINT8 TcoIrqSelect; = ///< Interrupt select for TCO. Default is 9. + UINT8 TcoIrqEnable; = ///< Enable IRQ generation for TCO. 0: Disable; 1: Enable. +} PCH_INTERRUPT_CONFIG; + +#pragma pack (pop) + +#endif // _INTERRUPT_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoA= picConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/Io= ApicConfig.h new file mode 100644 index 0000000000..726a27f7a1 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConf= ig.h @@ -0,0 +1,60 @@ +/** @file + IoApic policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _IOAPIC_CONFIG_H_ +#define _IOAPIC_CONFIG_H_ + +#define IOAPIC_CONFIG_REVISION 1 +extern EFI_GUID gIoApicConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_IOAPIC_CONFIG block describes the expected configuration of the = PCH + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit = is + not TRUE. Bus:device:function fields will be programmed to the register + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpos= e: + As the Requester ID when initiating Interrupt Messages to the processor. + As the Completer ID when responding to the reads targeting the IOxAPI's + Memory-Mapped I/O registers. + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS ca= n + program this field to provide a unique Bus:Device:Function number for th= e + internal IOxAPIC. + The address resource range of IOAPIC must be reserved in E820 and ACPI a= s + system resource. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; 1: Enable = IOAPIC Entry 24-119 + /** + Enable 8254 Static Clock Gating during early POST time. 0: Disable, 1: Enable + Setting 8254CGE is required to support SLP_S0. + Enable this if 8254 timer is not used. + However, set 8254CGE=3D1 in POST time might fail to boot legacy OS usi= ng 8254 timer. + Make sure it is disabled to support legacy OS using 8254 timer. + @note: + For some OS environment that it needs to set 8254CGE in late state it = should + set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in = SMM later. + This is also required during S3 resume. + To avoid SMI requirement in S3 reusme path, it can enable the Enable82= 54ClockGatingOnS3 + and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_= SAI. + **/ + UINT32 Enable8254ClockGating : 1; + /** + Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, 1: E= nable + This is only applicable when Enable8254ClockGating is disabled. + If Enable8254ClockGating is enabled, RC will do the 8254 CGE programmi= ng on + S3 resume path as well. + **/ + UINT32 Enable8254ClockGatingOnS3 : 1; + UINT32 RsvdBits1 : 29; ///< Reserved bits + UINT8 IoApicId; ///< This member determines IOAPIC= ID. Default is 0x02. + UINT8 Rsvd0[3]; ///< Reserved bytes +} PCH_IOAPIC_CONFIG; + +#pragma pack (pop) + +#endif // _IOAPIC_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePei= Config.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiCo= nfig.h new file mode 100644 index 0000000000..82786501f0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.= h @@ -0,0 +1,117 @@ +/** @file + ME config block for PEI phase + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _ME_PEI_CONFIG_H_ +#define _ME_PEI_CONFIG_H_ + +#define ME_PEI_PREMEM_CONFIG_REVISION 2 +extern EFI_GUID gMePeiPreMemConfigGuid; + +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif + +#pragma pack (push,1) + +/** + ME Pei Pre-Memory Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Add SkipCpuReplacementCheck Option. + Revision 3: + - Deprecate SendDidMsg. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 HeciTimeouts : 1; ///< 0: Disable; 1: Ena= ble - HECI Send/Receive Timeouts. + /** + (Test) + 0: Disabled + 1: ME DID init stat 0 - Success + 2: ME DID init stat 1 - No Memory in Channels + 3: ME DID init stat 2 - Memory Init Error + **/ + UINT32 DidInitStat : 2; + /** + (Test) + 0: Set to 0 to enable polling for CPU replacement + 1: Set to 1 will disable polling for CPU replacement + **/ + UINT32 DisableCpuReplacedPolling : 1; + UINT32 SendDidMsg : 1; ///< (Deprecated) 0= : Disable; 1: Enable - Enable/Disable to send DID message. + /** + (Test) + 0: ME BIOS will check each messages before sending + 1: ME BIOS always sends messages without checking + **/ + UINT32 DisableMessageCheck : 1; + /** + (Test) + The SkipMbpHob policy determines whether ME BIOS Payload data will be = requested during boot + in a MBP message. If set to 1, BIOS will send the MBP message with Ski= pMbp flag + set causing CSME to respond with MKHI header only and no MBP data + 0: ME BIOS will keep MBP and create HOB for MBP data + 1: ME BIOS will skip MBP data + **/ + UINT32 SkipMbpHob : 1; + UINT32 HeciCommunication2 : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable HECI2. + UINT32 KtDeviceEnable : 1; ///< (Test) 0: Disa= ble; 1: Enable - Enable/Disable Kt Device. + UINT32 SkipCpuReplacementCheck : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable to skip CPU replacement check. + UINT32 RsvdBits : 22; ///< Reserved for future u= se & Config block alignment + UINT32 Heci1BarAddress; ///< HECI1 BAR address. + UINT32 Heci2BarAddress; ///< HECI2 BAR address. + UINT32 Heci3BarAddress; ///< HECI3 BAR address. +} ME_PEI_PREMEM_CONFIG; +#pragma pack (pop) + + +#define ME_PEI_CONFIG_REVISION 3 +extern EFI_GUID gMePeiConfigGuid; + +#pragma pack (push,1) + +/** + ME Pei Post-Memory Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Deprecated Heci3Enabled. + Revision 3 + - Added EnforceEDebugMode. +**/ + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + + UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send = in PEI; 2: Send in DXE - Send EOP at specific phase. + UINT32 Heci3Enabled : 1; ///< @deprecated + UINT32 DisableD0I3SettingForHeci : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable D0i3 for HECI. + /** + Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send Me= UnconfigOnRtcClearDisable Msg with parameter 0. + It will cause ME to unconfig if RTC is cleared. + - 0: Disable + - 1: Enable + - 2: Cmos is clear, status unkonwn + - 3: Reserved + **/ + UINT32 MeUnconfigOnRtcClear : 2; + UINT32 MctpBroadcastCycle : 1; ///< (Test) 0: = Disable; 1: Enable - Program registers for MCTP Cycle. + UINT32 EnforceEDebugMode : 1; ///< 0: Disable; 1= : Enable - Enforces ME to enter Enhanced Debug Mode + UINT32 RsvdBits : 24; ///< Reserved for future = use & Config block alignment +} ME_PEI_CONFIG; + +#pragma pack (pop) + +#endif // _ME_PEI_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/V= er2/MemoryConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/= Memory/Ver2/MemoryConfig.h new file mode 100644 index 0000000000..17c0a10eee --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Mem= oryConfig.h @@ -0,0 +1,478 @@ +/** @file + Policy definition of Memory Config Block + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _MEMORY_CONFIG_H_ +#define _MEMORY_CONFIG_H_ + + +#pragma pack(push, 1) + +// MEMORY_CONFIG_REVISION 3 adds DDR5 PDA Enumeration training within MEMO= RY_CONFIGURATION +// MEMORY_CONFIG_REVISION 4 adds LPDDR4 Command Mirroring within MEMORY_CO= NFIGURATION +// MEMORY_CONFIG_REVISION 5 adds CpuBclkSpread option within MEMORY_CONFIG= URATION +// MEMORY_CONFIG_REVISION 6 adds McParity option within MEMORY_CONFIGURATI= ON +// MEMORY_CONFIG_REVISION 7 adds VddqVoltageOverride option within MEMORY_= CONFIGURATION +// MEMORY_CONFIG_REVISION 8 adds ExtendedBankHashing option within MEMORY_= CONFIGURATION +// MEMORY_CONFIG_REVISION 9 adds IbeccErrorInj option within MEMORY_CONFIG= URATION +#define MEMORY_CONFIG_REVISION 9 +/// +/// MEMORY_CONFIG interface definitions +/// +#define MRC_MAX_RCOMP_TARGETS 5 +/// +/// Memory SubSystem Definitions +/// +#define MEM_CFG_MAX_CONTROLLERS 2 +#define MEM_CFG_MAX_CHANNELS 4 +#define MEM_CFG_MAX_CHANNEL_SHARE_REGS 2 +#define MEM_CFG_MAX_DIMMS 2 +#define MEM_CFG_MAX_RANKS_PER_DIMM 2 +#define MEM_CFG_NUM_BYTES_MAPPED 2 +#define MEM_CFG_MAX_SPD_SIZE 1024 +#define MEM_CFG_MAX_SOCKETS (MEM_CFG_MAX_CONTROLLERS * MEM_CF= G_MAX_CHANNELS * MEM_CFG_MAX_DIMMS) +#define MEM_CFG_MAX_ROWS (MEM_CFG_MAX_RANKS_PER_DIMM * MEM= _CFG_MAX_SOCKETS) +#ifndef MEM_MAX_SAGV_POINTS +#define MEM_MAX_SAGV_POINTS 4 +#endif +#define MEM_MAX_IBECC_REGIONS 8 +/// +/// SMRAM Memory Range +/// +#define PEI_MR_SMRAM_ABSEG_MASK 0x01 +#define PEI_MR_SMRAM_HSEG_MASK 0x02 + +/// +/// SA SPD profile selections. +/// +typedef enum { + Default, ///< 0, Default SPD + UserDefined, ///< 1, User Defined profile + XMPProfile1, ///< 2, XMP Profile 1 + XMPProfile2, ///< 3, XMP Profile 2 + XMPProfileMax =3D 0xFF ///< Ensures SA_SPD is UINT8 +} SA_SPD; + +/// +/// Define the boot modes used by the SPD read function. +/// +typedef enum { + SpdCold, ///< Cold boot + SpdWarm, ///< Warm boot + SpdS3, ///< S3 resume + SpdFast, ///< Fast boot + SpdBootModeMax ///< Delimiter +} SPD_BOOT_MODE; + +/** + SPD Data Buffer +**/ +typedef struct { + UINT8 SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX= _DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData +//Next Field Offset 2048 +} SPD_DATA_BUFFER; + +/** + DqDqs Mapping +**/ +typedef struct { + UINT8 DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_= CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram + UINT8 DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_C= FG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram +//Next Field Offset 16 +} SA_MEMORY_DQDQS_MAPPING; + +/** + Rcomp Policies +**/ +typedef struct { + UINT16 RcompResistor; ///< Offset 0: Reference RCO= MP resistors on motherboard ~ 100 ohms + UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: RCOMP target = values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv +//Next Field Offset 16 +} SA_MEMORY_RCOMP; + +/** + SPD Offset Table +**/ +typedef struct { + UINT16 Start; ///< Offset 0 + UINT16 End; ///< Offset 2 + UINT8 BootMode; ///< Offset 4 + UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use +} SPD_OFFSET_TABLE; + +/// +/// SA memory address decode. +/// +typedef struct +{ + UINT8 Controller; ///< Offset 0 Zero based Controller number + UINT8 Channel; ///< Offset 1 Zero based Channel number + UINT8 Dimm; ///< Offset 2 Zero based DIMM number + UINT8 Rank; ///< Offset 3 Zero based Rank number + UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number + UINT8 Bank; ///< Offset 5 Zero based Bank number + UINT16 Cas; ///< Offset 6 Zero based CAS number + UINT32 Ras; ///< Offset 8 Zero based RAS number +} SA_ADDRESS_DECODE; + +typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress)= ; = = ///< CPU I/O port 8-bit read. +typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress)= ; = = ///< CPU I/O port 16-bit read. +typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress)= ; = = ///< CPU I/O port 32-bit read. +typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress,= UINT8 Value); = = ///< CPU I/O port 8-bit write. +typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress,= UINT16 Value); = = ///< CPU I/O port 16-bit write. +typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress,= UINT32 Value); = = ///< CPU I/O port 32-bit write. +typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); = = = ///< Memory Mapped I/O port 8-bit read. +typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); = = = ///< Memory Mapped I/O port 16-bit read. +typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); = = = ///< Memory Mapped I/O port 32-bit read. +typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); = = = ///< Memory Mapped I/O port 64-bit read. +typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, U= INT8 Value); = = ///< Memory Mapped I/O port 8-bit write. +typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, U= INT16 Value); = = ///< Memory Mapped I/O port 16-bit write. +typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, U= INT32 Value); = = ///< Memory Mapped I/O port 32-bit write. +typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, U= INT64 Value); = = ///< Memory Mapped I/O port 64-bit write. +typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, R= ETURN_STATUS *Status); = = ///< Smbus 8-bit read. +typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, R= ETURN_STATUS *Status); = = ///< Smbus 16-bit read. +typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, U= INT8 Value, RETURN_STATUS *Status); = = ///< Smbus 8-bit write. +typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, U= INT16 Value, RETURN_STATUS *Status); = = ///< Smbus 16-bit write. +typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); = = ///< Get PCI device address. +typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); = = ///< Get PCI express device address. +typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, U= INT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); = = ///< Get the current time value. +typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); = = = ///< The current CPU time in milliseconds. +typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destinatio= n, CONST VOID *Source, UINTN NumBytes); = = ///< Perform byte copy operation. +typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UI= NTN NumBytes, UINT8 Value); = = ///< Perform byte initialization operation. +typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UI= NTN NumWords, UINT16 Value); = = ///< Perform word initialization operation. +typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UI= NTN NumDwords, UINT32 Value); = = ///< Perform dword initialization operation. +typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); = = ///< Left shift the 64-bit data value by specifie= d number of bits. +typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); = = ///< Right shift the 64-bit data value by specifi= ed number of bits. +typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplic= and, UINT32 Multiplier); = = ///< Multiply a 64-bit data value by a 32-bit dat= a value. +typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend,= UINT64 Divisor, UINT64 *Remainder); = = ///< Divide a 64-bit data value by a 64-bit data = value. +typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE Bo= otMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3Table= Size, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 Lpd= drTableSize); ///< Read the SPD data over the SMBus, at the giv= en SmBus SPD address and copy the data to the data structure. +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, = SA_ADDRESS_DECODE *DramAddress); +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECOD= E *DramAddress, UINT64 Address); +typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); = = = ///< Get the next random 32-bit number. +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UIN= T32 Command, UINT32 *Value, UINT32 *Status); = = ///< Perform a CPU mailbox read. +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UIN= T32 Command, UINT32 Value, UINT32 *Status); = = ///< Perform a CPU mailbox write. +typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd); = = ///< Get the current memory voltage (VDD). +typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd, UINT32 Value); = = ///< Set the memory voltage (VDD) to the given va= lue. +typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData= , UINT32 CheckPoint, VOID *Scratch); = = ///< Check point that is called at various points= in the MRC. +typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData= , UINT16 DisplayDebugNumber); = = ///< Typically used to display to the I/O port 80= h. +typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, U= INT8 Channel); = = ///< Returns whether Channel is or is not present= . +typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UIN= T32 Level, char *Format, ...); = = ///< Print to output stream/device. +typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); = = = ///< Output a string to the debug stream/device. +typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData= , UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel= , UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWai= t, UINT32 RegFileParam); ///< Change the margin. +typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UIN= T8 OldMsb, UINT8 NewMsb); = = ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit = 6 to Bit 7). +typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData= , UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 Ne= wValue, UINT8 UpdateHost); = ///< Move CMD/CTL/CLK/CKE PIs during training. +typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData= , UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 O= ffset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); = ///< Update the Vref value and wait until it is s= table. +typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location);= = = ///< Get the current value of the specified RTC C= MOS location. +typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location)= ; = = ///< Get the current value of the specified MSR l= ocation. +typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location,= UINT64 Data); = = ///< Set the current value of the specified MSR l= ocation. +typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData= , UINT32 MrcStatus); = = ///< Hook function after returning from MrcStartM= emoryConfiguration() +typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseA= ddress, UINT32 ResetValue); = = ///< Assert or deassert DRAM_RESET# pin; this is = used in JEDEC Reset. +typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData= , UINT32 DelayNs); = = ///< Delay (stall) for the given amount of nanose= conds. +typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 PrmrrBase= Address, UINT32 PrmrrSize); + + +/// +/// Function calls into the SA. +/// +typedef struct { + SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU= I/O port 8-bit read. + SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU= I/O port 16-bit read. + SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU= I/O port 32-bit read. + SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU= I/O port 8-bit write. + SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU= I/O port 16-bit write. + SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU= I/O port 32-bit write. + SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Mem= ory Mapped I/O port 8-bit read. + SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Mem= ory Mapped I/O port 16-bit read. + SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Mem= ory Mapped I/O port 32-bit read. + SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Mem= ory Mapped I/O port 64-bit read. + SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Mem= ory Mapped I/O port 8-bit write. + SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Mem= ory Mapped I/O port 16-bit write. + SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Mem= ory Mapped I/O port 32-bit write. + SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Mem= ory Mapped I/O port 64-bit write. + SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smb= us 8-bit read. + SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smb= us 16-bit read. + SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smb= us 8-bit write. + SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smb= us 16-bit write. + SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get= PCI device address. + SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get= PCI express device address. + SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get= the current time value. + SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The= current CPU time in milliseconds. + SA_MEMORY_COPY CopyMem; ///< Offset 88: - Per= form byte copy operation. + SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Per= form byte initialization operation. + SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Per= form word initialization operation. + SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Per= form dword initialization operation. + SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Lef= t shift the 64-bit data value by specified number of bits. + SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Rig= ht shift the 64-bit data value by specified number of bits. + SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Mul= tiply a 64-bit data value by a 32-bit data value. + SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Div= ide a 64-bit data value by a 64-bit data value. + SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Rea= d the SPD data over the SMBus, at the given SmBus SPD address and copy the = data to the data structure. + SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get= the next random 32-bit number. + SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Per= form a CPU mailbox read. + SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Per= form a CPU mailbox write. + SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get= the current memory voltage (VDD). + SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set= the memory voltage (VDD) to the given value. + SA_CHECKPOINT CheckPoint; ///< Offset 144: - Che= ck point that is called at various points in the MRC. + SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typ= ically used to display to the I/O port 80h. + SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Out= put a string to the debug stream/device. + SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get= the current value of the specified RTC CMOS location. + SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get= the current value of the specified MSR location. + SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set= the current value of the specified MSR location. + SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hoo= k function after returning from MrcStartMemoryConfiguration() + SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Ass= ert or deassert DRAM_RESET# pin; this is used in JEDEC Reset. + SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Del= ay (stall) for the given amount of nanoseconds. +} SA_FUNCTION_CALLS; + +/// +/// Function calls into the MRC. +/// +typedef struct { + SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Retu= rns whether Channel is or is not present. + SA_PRINTF MrcPrintf; ///< Offset 4: - Prin= t to output stream/device. + SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Chan= ge the margin. + SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign= extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7). + SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move= CMD/CTL/CLK/CKE PIs during training. + SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Upda= te the Vref value and wait until it is stable. +} SA_MEMORY_FUNCTIONS; + +/** + Memory Configuration + The contents of this structure are CRC'd by the MRC for option change det= ection. + This structure is copied en mass to the MrcInput structure. If you add fi= elds here, you must update the MrcInput structure. + Revision 1: - Initial version. + Revision 2: - Adding ChHashOverride option. + Revision 3: - Adding PDA enumeration option. + Revision 4: - Adding LPDDR4 Command Mirroring. + Revision 5: - Adding CpuBclkSpread option. + Revision 6: - Adding McParity option. + Revision 7: - Adding VddqVoltageOverride option. + Revision 8: - Adding ExtendedBankHashing option. + Revision 9: - Adding IbeccErrorInj option + **/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + UINT16 Size; ///< Offset 28 The size of this structur= e, in bytes. Must be the first entry in this structure. + UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MR= C + + UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection= - for XMP supported DIMM: 0=3DDefault DIMM profile, 1=3DCustomized = profile, 2=3DXMP profile 1, 3=3DXMP profile 2. + + // The following parameters are used only when SpdProfileSelected is Use= rDefined (CUSTOM PROFILE) + UINT16 tCL; ///< Offset 32 User defined Memory Timin= g tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 31=3DMaximum. + UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timin= g tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE= : 0=3DAUTO, 63=3DMaximum + UINT16 tRAS; ///< Offset 36 User defined Memory Timin= g tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 64=3DMaximum. + UINT16 tWR; ///< Offset 38 User defined Memory Timin= g tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24. + UINT16 tRFC; ///< Offset 40 User defined Memory Timin= g tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 1023=3DMaximum. + UINT16 tRRD; ///< Offset 42 User defined Memory Timin= g tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum. + UINT16 tWTR; ///< Offset 44 User defined Memory Timin= g tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 28=3DMaximum. + UINT16 tRTP; ///< Offset 46 User defined Memory Timin= g tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12 + UINT16 tFAW; ///< Offset 48 User defined Memory Timin= g tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 63=3DMaximum. + UINT16 tCWL; ///< Offset 50 User defined Memory Timin= g tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 20=3DMaximum. + UINT16 tREFI; ///< Offset 52 User defined Memory Timin= g tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 65535=3DMaximum. + UINT16 PciIndex; ///< Offset 54 Pci index register addres= s: 0xCF8=3DDefault + UINT16 PciData; ///< Offset 56 Pci data register address= : 0xCFC=3DDefault + UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in mil= livolts: 0=3DPlatform Default (no override), 1200=3D1.2V, 1350=3D1.3= 5V etc. + UINT16 Idd3n; ///< Offset 60 EPG Active standby curren= t (Idd3N) in milliamps from DIMM datasheet. + UINT16 Idd3p; ///< Offset 62 EPG Active power-down cur= rent (Idd3P) in milliamps from DIMM datasheet. + + UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Supp= ort option - for Desktop only: 0=3DDisable, 1=3DEnable + UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode= : 0=3DDisable, 1=3DEnable + UINT32 RemapEnable:1; ///< Bit 2 - This option i= s used to control whether to enable/disable memory remap above 4GB: 0=3DDis= able, 1=3DEnable. + UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scramb= ler support: 0=3DDisable, 1=3DEnable + UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Mete= ring Enable: 0=3DDisable, 1=3DEnable + UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means us= e SubChannel0 only (for LPDDR4): 0=3DDisable, 1=3DEnable + UINT32 SimicsFlag:1; ///< Bit 6 - Option to Ena= ble SIMICS: 0=3DDisable, 1=3DEnable + UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK= 0 is shared between Rank0 and Rank1 in DDR4 DDP package. 0=3DNot shared<= /b>, 1=3DShared + UINT32 SharedZqPin:1; ///< Bit 8 - Select if the= ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages 0=3DNo= t Shared, 1=3DShared + UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write D= Q/DQS Retraining: 0=3DDisable, 1=3DEnable + UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin T= ool Per Task. 0 =3D Disabled, 1 =3D Enabled + UINT32 TrainTrace:1; ///< Bit 11 - Trained state= tracing debug. 0 =3D Disabled, 1 =3D Enabled + UINT32 SafeMode:1; ///< Bit 12 - Define if saf= e mode is enabled for MC/IO + UINT32 MsHashEnable:1; ///< Bit 13 - Controller Ha= sh Enable: 0=3DDisable, 1=3DEnable + UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page = Close Idle Timeout: 0=3DEnable, 1=3DDisable + UINT32 Ibecc:1; ///< Bit 15 - Inband ECC - = for LPDDR4, LPDDR5 and DDR4 only: 0=3DDisable, 1=3DEnable + UINT32 IbeccParity:1; ///< Bit 16 - Inband ECC Pa= rity Control - for LPDDR4, LPDDR5 and DDR4 only: 0=3DDisable, 1=3DEn= able + UINT32 IbeccOperationMode:2; ///< Bits 17:18 - Inband EC= C Operation Mode: 0=3DFunctional Mode protects requests based on the addres= s range, 1=3DMakes all requests non protected and ignore range checks, 2=3DMakes all requests protected and ignore range checks + UINT32 ChHashOverride:1; ///< Bit 19 - Select if Cha= nnel Hash setting values will be taken from input parameters or automatical= ly taken from POR values depending on DRAM type detected. + UINT32 McParity:1; ///< Bit 20 - MC Parity Con= trol - Enable Parity for CMI/MC: 0=3DDisable, 1=3DEnable + UINT32 IbeccErrorInj:1; ///< Bit 21 - In-Band ECC E= rror Injection: 1=3DEnable, 0=3DDisable + UINT32 RsvdO64B22t31:10; ///< Bits 22:31 reserved + /** + Disables a DIMM slot in the channel even if a DIMM is present\n + Array index represents the channel number (0 =3D channel 0, 1 =3D chann= el 1)\n + 0x0 =3D DIMM 0 and DIMM 1 enabled\n + 0x1 =3D DIMM 0 disabled, DIMM 1 enabled\n + 0x2 =3D DIMM 0 enabled, DIMM 1 disabled\n + 0x3 =3D DIMM 0 and DIMM 1 disabled (will disable the whole channel)\n + **/ + UINT8 DisableDimmChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS= ]; ///< Offset 68-75 + UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to m= ultiply by 133 or 100 MHz depending on RefClk. 0 =3D Auto + UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: 0=3DD= isabled, 1=3DEnabled + /** + - Channel Hash Enable.\n + NOTE: BIT7 will interleave the channels at a 2 cache-line granularity,= BIT8 at 4 and BIT9 at 8\n + 0=3DBIT6, 1=3DBIT7, 2=3DBIT8, 3=3DBIT9 + **/ + UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interlea= ve Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW= are 0-7 for BITS 6 - 13) + UINT8 SmramMask; ///< Offset 79 Reserved memory ranges fo= r SMRAM + UINT32 BClkFrequency; ///< Offset 80 Base reference clock valu= e, in Hertz: 100000000 =3D 100Hz, 125000000=3D125Hz, 167000000=3D167= Hz, 250000000=3D250Hz + + /// Training Algorithms 1 Offset 84 + UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Comman= d Training. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable. + UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Of= fset Training. Note it is not recommended to change this setting from the d= efault value: 0=3DDisable, 1=3DEnable. + UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMP= R Timing Centering 2D. Note it is not recommended to change this setting fr= om the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Tra= ining. Note it is not recommended to change this setting from the default v= alue: 0=3DDisable, 1=3DEnable. + UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enab= le Training. Note it is not recommended to change this setting from the def= ault value: 0=3DDisable, 1=3DEnable. + UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write = Leveling Training. Note it is not recommended to change this setting from t= he default value: 0=3DDisable, 1=3DEnable. + UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write = Time Centering 2D Training. Note it is not recommended to change this setti= ng from the default value: 0=3DDisable, 1=3DEnable. + UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read T= ime Centering 2D Training. Note it is not recommended to change this settin= g from the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Tim= ing Centering Training. Note it is not recommended to change this setting f= rom the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Vol= tage Centering Training. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Tim= ing Centering Training. Note it is not recommended to change this setting f= rom the default value: 0=3DDisable, 1=3DEnable. + UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT Tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive= Strength / Equalization Training 2D. Note it is not recommended to change = this setting from the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew = Rate traning. Note it is not recommended to change this setting from the de= fault value: 0=3DDisable, 1=3DEnable. + UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equali= zation Training. Note it is not recommended to change this setting from the= default value: 0=3DDisable, 1=3DEnable. + UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplif= ier Power Training. Note it is not recommended to change this setting from = the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Ti= ming Centering Training. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Tim= ing Centering Training. Note it is not recommended to change this setting f= rom the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Vo= ltage Centering Training. Note it is not recommended to change this setting= from the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Vol= tage Centering Training. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable. + UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vre= f Centering Training. Note it is not recommended to change this setting fro= m the default value 0=3DDisable, 1=3DEnable. + UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Comman= d Training. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable. + UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip = Latency function. Note it is not recommended to change this setting from th= e default value: 0=3DDisable, 1=3DEnable. + UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around= Time function. Note it is not recommended to change this setting from the = default value: 0=3DDisable, 1=3DEnable. + UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin= Tool function: 0=3DDisable, 1=3DEnable. + UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test= function: 0=3DDisable, 1=3DEnable. + UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Al= ias Check: 0=3DDisable, 1=3DEnable + UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Ena= ble Centering Training (LPDDR Only). Note it is not recommended to change t= his setting from the default value: 0=3DDisable, 1=3DEnable + UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Mar= gin Check. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable + UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive= Strength Up/Dn independently. Note it is not recommended to change this se= tting from the default value: 0=3DDisable, 1=3DEnable + /// Training Algorithms 2 Offset 88 + UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle = Correction: 0=3DDisable, 1=3DEnable. + UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltag= e Centering 1D: 0=3DDisable, 1=3DEnable. + UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO C= omp Training: 0=3DDisable, 1=3DEnable. + UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO C= omp Training: 0=3DDisable, 1=3DEnable. + UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Ra= te Training: 0=3DDisable, 1=3DEnable. + UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive S= trength and Tx Equalization: 0=3DDisable, 1=3DEnable. + UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA= Training: 0=3DDisable, 1=3DEnable. + UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO D= qs Training: 0=3DDisable, 1=3DEnable. + UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Dri= ve Strength Up/Dn 2D: 0=3DDisable, 1=3DEnable. + UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypa= ss to VccIOG training: 0=3DDisable, 1=3DEnable. + UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnL= p Training: 0=3DDisable, 1=3DEnable. + UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref D= ecap Training: 0=3DDisable, 1=3DEnable. + UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Traini= ng: 0=3DDisable, 1=3DEnable. + UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin= Tool Per Bit: 0=3DDisable, 1=3DEnable. + UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumera= tion Training. Note it is not recommended to change this setting from the d= efault value: 0=3DDisable, 1=3DEnable. + UINT32 WRITE0 : 1; ///< BIT 15 - Write0 feature enablement + UINT32 ReservedBits2 :16; ///< Bits 16:31 - Reserved + + UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial= debug level to display the MRC execution times only: 0=3DDisable, 1= =3DEnable + UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MR= C fast boot path for faster cold boot execution: 0=3DDisable, 1=3DEnable= + UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving m= ode of DQ/DQS pins which depends on board routing: 0=3DDisable, 1=3D= Enable + UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleav= e Mode: 0=3DDisable, 1=3DEnable + UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Inter= leave Mode: 0=3DDisable, 1=3DEnable + UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enab= le: 0=3DDisable, 1=3DEnable + UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash E= nable: 0=3DDisable, 1=3DEnable + UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power D= own control for DDR: 0=3DPCODE control, 1=3DBIOS control + UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power D= own for LPDDR: 0=3DPCODE control, 1=3DBIOS control + UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Re= fresh: 0=3DDisable, 1=3DEnable + UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE = min defeature for LPDDR: 0=3DDisable, 1=3DEnable + UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE = min defeature: 0=3DDisable, 1=3DEnable + UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE =3D No a= uto self refresh support, TRUE =3D auto self refresh support + UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE =3D No e= xtended temperature support, TRUE =3D extended temperature support + UINT32 MobilePlatform:1; ///< Bit 14 - Memory control= ler device id indicates: TRUE if mobile, FALSE if not. Note: This wi= ll be auto-detected and updated. + UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means for= ce one DIMM per channel, FALSE means no limit + UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use= Rank0 only (in each DIMM): 0=3DDisable, 1=3DEnable + UINT32 VttTermination:1; ///< Bit 17 - Vtt Terminatio= n for Data ODT: 0=3DDisable, 1=3DEnable + UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable= Vtt Comparator For Vsshi: 0=3DDisable, 1=3DEnable + UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for= exit on failure or continue on failure: 0=3DDisable, 1=3DEnable + UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable= knob for new feature set 1 0: Disable ; 1: Enable + UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable= knob for new feature set 2 0: Disable ; 1: Enable + UINT32 RhPrevention:1; ///< Bit 22 - RH Prevention = Enable/Disable: 0=3DDisable, 1=3DEnable + UINT32 RhSolution:1; ///< Bit 23 - Type of soluti= on to be used for RHP - 0/1 =3D HardwareRhp/Refresh2x + UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Refresh Pan= ic Watermark, Range 1-8, default 8. + UINT32 RefreshHpWm:4; ///< Bit 28-31 - Refresh Hig= h Profile Watermark, Range 1-7, default 7. + UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in microse= conds to wait for Vdd to settle on top of 200us required by JEDEC spec: = Default=3D0 + UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer:= 512=3DMinimal, 65535=3DMaximum + UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: 0x000= 1=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D BIT[19= :18, 13:12 ,9:7] set + UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency setting= : 3=3D1067, 5=3D1333, 7=3D1600, 9=3D1867, 11=3D2133, 13=3D2400, 15=3D266= 7 + UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to u= se in power training: 0=3DODT Off, 1 =3D 120 ohms + UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer:= 0=3DMinimal, 0xFF=3DMaximum, 0x00=3DDefault + UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer = for LPDDR: 0=3DMinimal, 0xFF=3DMaximum, 0x00=3DDefault + BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the= per bank refresh. This only impacts memory technologies that support PBR:= LPDDR3, LPDDR4. FALSE=3DDisabled, TRUE=3DEnabled + UINT8 SaGv; ///< Offset 110 SA GV: 0=3DDisabled, 1=3DPoint1, 2=3DPoint2, 3=3DPoint3, 4=3DPoint4, 5=3DEnabled + UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support - = Enable user to select Auto, 1N or 2N: 0=3DAUTO, 1=3D1N, 2=3D2N. + UINT8 RefClk; ///< Offset 112 Selects the DDR base ref= erence clock. 0x01 =3D 100MHz, 0x00 =3D 133MHz + UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=3DDis= able, 5=3D2 CMDs, 7=3D3 CMDs, 9=3D4 CMDs, 11=3D5 CMDs, 13=3D6 CMDs, = 15=3D7 CMDs + UINT8 Refresh2X; ///< Offset 114 Refresh 2x: 0=3DDisab= le, 1=3DEnable for WARM or HOT, 2=3DEnable for HOT only + UINT8 EpgEnable; ///< Offset 115 Enable Energy Performanc= e Gain. + UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select = the DIMM CLTM Thermal Threshold, 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select = the Budget Registers for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, 0= =3DDefault + UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode= if SW MemTest fails during Fast flow. 0 =3D Disabled, 1 =3D Enabled + UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: = 0xFF=3DAUTO, 0=3DNo Power Down, 1=3D APD mode, 6=3DPPD-DLL Off mode + UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode Idle= Counter: 0=3DMinimal, 255=3DMaximum, 0x80=3D0x80 DCLK + UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks = that have CA bus terminated. 0x01=3DDefault, Rank0 is terminating and Ra= nk1 is non-terminating + UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: 0x= 0001=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D BIT= [19:18, 13:12 ,9:7] set + UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0]= are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. = 0 selects Ascending mapping and 1 selects Descending mapping. + UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count= to be used for Rank Margin Tool Testing: 1=3DMinimal, 32=3DMaximum, 0=3DAU= TO, 0=3DDefault + UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interle= ave Address bit. Valid values are 0 - 3 for BITS 6 - 9 + UINT8 GearRatio; ///< Offset 130 This input control's the= current gear expressed as an integer when SAGV is disabled: 0=3DDefault= , 1, 2. + UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance fe= ature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; = 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1) + UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI Frequ= ency for each SAGV point in Hz units. 98000000Hz =3D 98MHz 0 - No RFI Tu= ning. Range is 98Mhz-100Mhz. + UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 Frequency per = SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an= integer: 0=3DDefault, 1067, 1333, 1600, 1800, 1867, etc. + /** + Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the = Gear ratio expressed as an integer: 0=3DDefault, 1, 2. + Only valid combinations of Gear Ratio per point is: + | point | set1 | set2 | set3 + | 0 | 1 | 2 | 2 + | 1 | 1 | 2 | 2 + | 2 | 1 | 2 | 2 + | 3 | 1 | 2 | 1 + **/ + UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset = 156 + UINT8 IbeccProtectedRegionEnable[MEM_MAX_IBECC_REGIONS]; ///< Offset = 160 Enable use of address range for ECC Protection: 0=3DDefault, 1 + UINT16 IbeccProtectedRegionBase[MEM_MAX_IBECC_REGIONS]; ///< Offset = 168 Base address for address range of ECC Protection: 0=3DDefault, = 1 + UINT16 IbeccProtectedRegionMask[MEM_MAX_IBECC_REGIONS]; ///< Offset = 184 Mask address for address range of ECC Protection: 0=3DDefault, = 1 + UINT32 CmdMirror; ///< Offset 200 BitMask where bits [3:0]= are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. = 0 =3D No Command Mirror and 1 =3D Command Mirror. + UINT8 CpuBclkSpread; ///< Offset 204 CPU BCLK Spread Specturm= : 0 =3D Disabled; 1 =3D Enabled + UINT8 ExtendedBankHashing; ///< Offset 205 Enable EBH Extended Bank= Hashing: 0=3DDisabled; 1 =3D Enabled. + UINT16 VddqVoltageOverride; ///< Offset 206 VccddqVoltage override i= n # of 1mV + UINT8 MarginLimitCheck; ///< Offset = 208 Margin limit check enable: 0=3DDisable, 1=3DL1 only, 2=3DL2 only= , 3=3DBoth L1 and L2 + UINT8 RsvdO209; ///< Offset = 209 + UINT16 MarginLimitL2; ///< Offset = 210 Margin limit check L2 threshold: 100=3DDefault +} MEMORY_CONFIGURATION; + +/// Memory Configuration +/// The contents of this structure are not CRC'd by the MRC for option cha= nge detection. +/// Revision 1: - Initial version. +/// Revision 2: - Added MemTestOnWarmBoot +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Bl= ock Header + SA_FUNCTION_CALLS SaCall; ///< Offset 24 Function = calls into the SA. + SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 204 Function = calls into the MRC. + SPD_DATA_BUFFER *SpdData; ///< Offset 240 Memory SP= D data, will be used by the MRC when SPD SmBus address is zero. + UINT32 Reserved0; + SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 244 LPDDR DQ = bit and DQS byte swizzling between CPU and DRAM. + SA_MEMORY_RCOMP *RcompData; ///< Offset 248 DDR RCOMP= resistors and target values. + UINT64 PlatformMemorySize; ///< Offset 252 The minim= um platform memory size required to pass control into DXE + UINT32 CleanMemory:1; ///< Offset 256 Ask MRC t= o clear memory content: FALSE=3DDo not Clear Memory; TRUE=3DClear Me= mory + UINT32 ReservedBits5:31; + /** + Sets the serial debug message level\n + 0x00 =3D Disabled\n + 0x01 =3D Errors only\n + 0x02 =3D Errors and Warnings\n + 0x03 =3D Errors, Warnings, and Info\n + 0x04 =3D Errors, Warnings, Info, and Events\n + 0x05 =3D Displays Memory Init Execution Time Summary only\n + **/ + UINT8 SerialDebugLevel; ///< Offset 260 + UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base = Memory Test On WarmBoot: 0=3DDisabled, 1=3DEnabled + UINT8 Reserved11[2]; ///< Offset 262 - 263 Res= erved +} MEMORY_CONFIG_NO_CRC; +#pragma pack(pop) + +#endif // _MEMORY_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overcloc= king/OverclockingConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Confi= gBlock/Overclocking/OverclockingConfig.h new file mode 100644 index 0000000000..462c02cef1 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Ov= erclockingConfig.h @@ -0,0 +1,236 @@ +/** @file + Overclocking Config Block. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _OVERCLOCKING_PREMEM_CONFIG_H_ +#define _OVERCLOCKING_PREMEM_CONFIG_H_ + +#define OVERCLOCKING_CONFIG_REVISION 9 + +extern EFI_GUID gOverclockingPreMemConfigGuid; + +#pragma pack (push,1) + +// +// Max number of VF point offset +// +#ifndef CPU_OC_MAX_VF_POINTS +#define CPU_OC_MAX_VF_POINTS 0xF +#endif + +#ifndef CPU_OC_MAX_CORES +#define CPU_OC_MAX_CORES 8 +#endif +/** + Overclocking Configuration Structure. + + Revision 1: + - Initial version. + Revision 2 + - Add PerCoreHtDisable + Revision 3 + - Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor + Revision 4 + - Add CoreVfPointOffsetMode & CoreVfPointOffset & CoreVfPointRatio & Cor= eVfPointCount + Revision 5 + - Change OcLock default to 'Enabled' + Revision 6: + - Add DisableCoreMask. + Revision 7 + Add UnlimitedIccMax + Revision 8 + - Add PerCoreRatioOverride and PerCoreRatio for Per Core PState overcloc= king. + Revision 9 + - Add VccInVoltageOverride. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Overclocking support. This controls whether OC mailbox transactions are = sent. + If disabled, all policies in this config block besides OcSupport and OcL= ock will be ignored. + 0: Disable; + 1: Enable. + @note If PcdOverclockEnable is disabled, this should also be disabled. + **/ + UINT32 OcSupport : 1; + UINT32 OcLock : 1; ///< If enabled, sets OC= lock bit in MSR 0x194[20], locking the OC mailbox and other OC configurati= on settings.; 0: Disable; 1: Enable (Lock). + /** + Core voltage mode, specifies which voltage mode the processor will be op= erating. + 0: Adaptive Mode allows the processor to interpolate a voltage cu= rve when beyond fused P0 range; + 1: Override, sets one voltage for for the entire frequency range, Pn-P0. + **/ + UINT32 CoreVoltageMode : 1; + UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage of= fset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. = 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize= possible ratio for SSE workload. + UINT32 Avx3RatioOffset : 5; ///< AVX3 Ratio Offset. = 0: No offset. Range is 0-31. Used to lower the AVX3 ratio to maximiz= e possible ratio for SSE workload. + UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Volta= ge enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/= F curves are aware of BCLK frequency when calculated. + /** + Ring Downbin enable/disable. + When enabled, the CPU will force the ring ratio to be lower than the cor= e ratio. + Disabling will allow the ring and core ratios to run at the same frequen= cy. + Uses OC Mailbox command 0x19. + 0: Disables Ring Downbin feature. 1: Enables Ring downbin feature. + **/ + UINT32 RingDownBin : 1; + /** + Ring voltage mode, specifies which voltage mode the processor will be op= erating. + 0: Adaptive Mode allows the processor to interpolate a voltage cu= rve when beyond fused P0 range; + 1: Override, sets one voltage for for the entire frequency range, Pn-P0. + **/ + UINT32 RingVoltageMode : 1; + UINT32 GtVoltageMode : 1; ///< Specifies whether GT voltage i= s operating in Adaptive or Override mode: 0=3DAdaptive, 1=3DOverride + UINT32 RealtimeMemoryTiming : 1; ///< Enable/Disable the message sen= t to the CPU to allow realtime memory timing changes after MRC_DONE. 0= =3DDisable, 1=3DEnable + UINT32 FivrFaults : 1; ///< Fivr Faults. Enable or Disable= FIVR Faults. 0: Disabled, 1: Enabled. + UINT32 FivrEfficiency : 1; ///< Fivr Efficiency Management. 0:= Disabled, 1: Enabled. + /** + Selects Core Voltage & Frequency Point Offset between Legacy and Selecti= on modes. + Need Reset System after enabling OverClocking Feature to Initialize the = default value. + 0: In Legacy Mode, setting a global offset for the entire VF curve. + 1: In Selection modes, setting a selected VF point. + **/ + UINT32 CoreVfPointOffsetMode : 1; + UINT32 UnlimitedIccMax : 1; ///< Support Unlimited ICCMAX more = than maximum value 255.75A. 0: Disabled, 1: Enabled. + UINT32 PerCoreRatioOverride : 1; ///< Enable or disable Pe= r Core PState OC supported by writing OCMB 0x1D to program new favored core= ratio to each Core. 0: Disable, 1: enable + UINT32 DynamicMemoryChange : 1; ///< Dynamic Memory Timings Changes;= 0: Disabled; 1: Enabled. + UINT32 RsvdBits : 2; ///< Reserved for future use + + /** + Maximum core turbo ratio override allows to increase CPU core frequency = beyond the fused max turbo ratio limit (P0). + 0. no override/HW defaults.. Range 0-85. + **/ + UINT8 CoreMaxOcRatio; + UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio overrid= e: 0=3DMinimal, 60=3DMaximum, 0=3DAUTO + /** + Maximum ring ratio override allows to increase CPU ring frequency beyond= the fused max ring ratio limit. + 0. no override/HW defaults.. Range 0-85. + **/ + UINT8 RingMaxOcRatio; + UINT8 RsvdByte1; + /** + The core voltage override which is applied to the entire range of cpu co= re frequencies. + Used when CoreVoltageMode =3D Override. + 0. no override. Range 0-2000 mV. + **/ + UINT16 CoreVoltageOverride; + /** + Adaptive Turbo voltage target used to define the interpolation voltage p= oint when the cpu is operating in turbo mode range. + Used when CoreVoltageMode =3D Adaptive. + 0. no override. Range 0-2000mV. + **/ + UINT16 CoreVoltageAdaptive; + /** + The core voltage offset applied on top of all other voltage modes. This = offset is applied over the entire frequency range. + This is a 2's complement number in mV units. Default: 0 Range: -1= 000 to 1000. + **/ + INT16 CoreVoltageOffset; + /** + The ring voltage override which is applied to the entire range of cpu ri= ng frequencies. + Used when RingVoltageMode =3D Override. + 0. no override. Range 0-2000 mV. + **/ + UINT16 RingVoltageOverride; + /** + Adaptive Turbo voltage target used to define the interpolation voltage p= oint when the ring is operating in turbo mode range. + Used when RingVoltageMode =3D Adaptive. + 0. no override. Range 0-2000mV. + **/ + UINT16 RingVoltageAdaptive; + /** + The ring voltage offset applied on top of all other voltage modes. This = offset is applied over the entire frequency range. + This is a 2's complement number in mV units. Default: 0 Range: -1= 000 to 1000. + **/ + INT16 RingVoltageOffset; + + INT16 GtVoltageOffset; ///< The voltage offset = applied to GT slice. Valid range from -1000mv to 1000mv: 0=3DMinimal= , 1000=3DMaximum + UINT16 GtVoltageOverride; ///< The GT voltage over= ride which is applied to the entire range of GT frequencies 0=3DDefault<= /b> + UINT16 GtExtraTurboVoltage; ///< The adaptive voltag= e applied during turbo frequencies. Valid range from 0 to 2000mV: 0=3DMi= nimal, 2000=3DMaximum + INT16 SaVoltageOffset; ///< The voltage offset = applied to the SA. Valid range from -1000mv to 1000mv: 0=3DDefault + UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offs= et. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage of= fset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL vo= ltage offset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 McPllVoltageOffset : 6; ///< Memory Controller P= LL voltage offset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 RsvdBits1 : 8; + /** + TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offs= et) to support TjMax in the range of 62 to 115 deg Celsius. + Default: 0 Hardware Defaults Range 10 to 63. 0 =3D No offset / = Keep HW default. + **/ + UINT8 TjMaxOffset; + UINT8 RsvdByte2[3]; //< Reserved for dword al= ignment + /** + This service controls Core frequency reduction caused by high package te= mperatures for processors that + implement the Intel Thermal Velocity Boost (TVB) feature. It is required= to be disabled for supporting + overclocking at frequencies higher than the default max turbo frequency. + 0: Disables TVB ratio clipping. 1: Enables TVB ratio clipping. + **/ + UINT32 TvbRatioClipping : 1; + /** + This service controls thermal based voltage optimizations for processors= that implement the Intel + Thermal Velocity Boost (TVB) feature. + 0: Disables TVB voltage optimization. 1: Enables TVB voltage optimiza= tion. + **/ + UINT32 TvbVoltageOptimization : 1; + UINT32 RsvdBits2 : 30; + /** + Defines the per-core HT disable mask where: 1 - Disable selected logical= core HT, 0 - is ignored. + Input is in HEX and each bit maps to a logical core. Ex. A value of '1F'= would disable HT for cores 4,3,2,1 and 0. + Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You = can only disable up to MAX_CORE_COUNT - 1. + **/ + UINT16 PerCoreHtDisable; + /** + Avx2 Voltage Guardband Scale Factor + This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 wo= rkloads. + Valid range is 0-200 in 1/100 units, where a value of 125 would apply a = 1.25 scale factor. + A value of 0 means no scale factor applied (no change to voltage on AVX = commands) + A value of 100 applies the default voltage guardband values (1.0 factor)= . + A value > 100 will increase the voltage guardband on AVX2 workloads. + A value < 100 will decrease the voltage guardband on AVX2 workloads. + + 0. No scale factor applied + **/ + UINT8 Avx2VoltageScaleFactor; + /** + Avx512 Voltage Guardband Scale Factor + This controls the AVX512 Voltage Guardband Scale factor applied to AVX51= 2 workloads. + Valid range is 0-200 in 1/100 units, where a value of 125 would apply a = 1.25 scale factor. + A value of 0 means no scale factor applied (no change to voltage on AVX = commands) + A value of 100 applies the default voltage guardband values (1.0 factor)= . + A value > 100 will increase the voltage guardband on AVX512 workloads. + A value < 100 will decrease the voltage guardband on AVX512 workloads. + + 0. No scale factor applied + **/ + UINT8 Avx512VoltageScaleFactor; + /** + Array used to specifies the Core Voltage Offset applied to the each sele= cted VF Point. + This voltage is specified in millivolts. + **/ + INT16 CoreVfPointOffset[CPU_OC_MAX_VF_POINTS]; + UINT8 RsvdByte3[2]; ///< Just to keep native alignment. + /** + Array for the each selected VF Point to display the Core Ration. + **/ + UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS]; + /** + Number of supported Core Voltage & Frequency Point. + **/ + UINT8 CoreVfPointCount; + /** + Core mask is a bitwise indication of which core should be disabled. Bit = 0 - core 0, bit 7 - core 7. + **/ + UINT32 DisableCoreMask; + UINT8 PerCoreRatio[CPU_OC_MAX_CORES]; + /** + The VcccIn voltage override. + This will override VccIn output voltage level to the voltage value speci= fied. + The voltage level is fixed and will not change except on PKG C-states or= resets. + + 0. no override. Range 0-3000 mV. + **/ + UINT32 VccInVoltageOverride; +} OVERCLOCKING_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_OVERCLOCKING_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2s= bConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sb= Config.h new file mode 100644 index 0000000000..69271205b1 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig= .h @@ -0,0 +1,34 @@ +/** @file + P2sb policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _P2SB_CONFIG_H_ +#define _P2SB_CONFIG_H_ + +#define P2SB_CONFIG_REVISION 1 +extern EFI_GUID gP2sbConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to P2SB device. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + (Test) + The sideband MMIO register access to specific ports will be locked + before 3rd party code execution. Currently it disables PSFx access. + This policy unlocks the sideband MMIO space for those IPs. + 0: Lock sideband access ; 1: Unlock sideband access. + NOTE: Do not set this policy "SbAccessUnlock" unless its necessary. + **/ + UINT32 SbAccessUnlock : 1; + UINT32 Rsvdbits : 31; ///< Reserved bits +} PCH_P2SB_CONFIG; + +#pragma pack (pop) + +#endif // _P2SB_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/P= chDmiConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDm= i/PchDmiConfig.h new file mode 100644 index 0000000000..b73108bcfd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiCo= nfig.h @@ -0,0 +1,44 @@ +/** @file + DMI policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_DMI_CONFIG_H_ +#define _PCH_DMI_CONFIG_H_ + +#define PCH_DMI_CONFIG_REVISION 2 +extern EFI_GUID gPchDmiConfigGuid; + + +#pragma pack (push,1) + + +/** + The PCH_DMI_CONFIG block describes the expected configuration of the PCH = for DMI. + Revision 1: - Initial version. + Revision 2: - Add OpioRecenter +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable = DMI Power Optimizer on PCH side. + UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH= side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig + UINT32 CwbEnable : 1; ///< 0: Disable; 1: Enable = Central Write Buffer feature configurable and enabled by default + UINT32 L1RpCtl : 1; ///< 0: Disable; 1: Enable = Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disable= d by default. + /** + When set to TRUE turns on: + - L1 State Controller Power Gating + - L1 State PHY Data Lane Power Gating + - PHY Common Lane Power Gating + - Hardware Autonomous Enable + - PMC Request Enable and Sleep Enable + **/ + UINT32 DmiPowerReduction : 1; + UINT32 OpioRecenter : 1; ///< 0: Disable; 1: Enable = Opio Recentering Disable for Pcie latency + UINT32 Rsvdbits : 19; ///< Reserved bits +} PCH_DMI_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_DMI_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/P= chPcieRp/PchPcieRpConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Conf= igBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h new file mode 100644 index 0000000000..de086473a9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieR= p/PchPcieRpConfig.h @@ -0,0 +1,368 @@ +/** @file + PCH Pcie root port policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCH_PCIERP_CONFIG_H_ +#define _PCH_PCIERP_CONFIG_H_ + +#include +#include +#include + +#define PCIE_RP_CONFIG_REVISION 1 +#define PCIE_RP_PREMEM_CONFIG_REVISION 1 +#define PCIE_RP_DXE_CONFIG_REVISION 1 + +extern EFI_GUID gPchPcieConfigGuid; +extern EFI_GUID gPcieRpPreMemConfigGuid; + +#pragma pack (push,1) + +#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10 +#define PCIE_LINK_EQ_PRESETS_MAX 11 + +typedef enum { + PchPcieOverrideDisabled =3D 0, + PchPcieL1L2Override =3D 0x01, + PchPcieL1SubstatesOverride =3D 0x02, + PchPcieL1L2AndL1SubstatesOverride =3D 0x03, + PchPcieLtrOverride =3D 0x04 +} PCH_PCIE_OVERRIDE_CONFIG; + +/** + PCIe device table entry entry + + The PCIe device table is being used to override PCIe device ASPM setting= s. + To take effect table consisting of such entries must be instelled as PPI + on gPchPcieDeviceTablePpiGuid. + Last entry VendorId must be 0. +**/ +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card= ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Exp= ress card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Expr= ess card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH= _PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideC= onfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (se= e: PCH_PCIE_OVERRIDE_CONFIG). + /** + The L1Substates Capability Offset Override. (applicable if bit 2 is se= t in OverrideConfig) + This field can be zero if only the L1 Substate value is going to be ov= erride. + **/ + UINT16 L1SubstatesCapOffset; + /** + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideCo= nfig) + Set to zero then the L1 Substate Capability [3:0] is ignored, and only= L1s values are override. + Only bit [3:0] are applicable. Other bits are ignored. + **/ + UINT8 L1SubstatesCapMask; + /** + L1 Substate Port Common Mode Restore Time Override. (applicable if bit= 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sCommonModeRestoreTime; + /** + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnScale; + /** + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnValue; + + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be mul= tiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be= multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 NonSnoopLatency; + + /** + Forces LTR override to be permanent + The default way LTR override works is: + rootport uses LTR override values provided by BIOS until connected d= evice sends an LTR message, then it will use values from the message + This settings allows force override of LTR mechanism. If it's enabled,= then: + rootport will use LTR override values provided by BIOS forever; LTR = messages sent from connected device will be ignored + **/ + UINT8 ForceLtrOverride; + UINT8 Reserved[3]; +} PCH_PCIE_DEVICE_OVERRIDE; + +/// +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCIE_ASPM_CONTROL; + +/** + Refer to PCH EDS for the PCH implementation values corresponding + to below PCI-E spec defined ranges +**/ +typedef enum { + PchPcieL1SubstatesDisabled, + PchPcieL1SubstatesL1_1, + PchPcieL1SubstatesL1_1_2, + PchPcieL1SubstatesMax +} PCH_PCIE_L1SUBSTATES_CONTROL; + +enum PCH_PCIE_MAX_PAYLOAD { + PchPcieMaxPayload128 =3D 0, + PchPcieMaxPayload256, + PchPcieMaxPayloadMax +}; + +typedef enum { + PcieLinkHardwareEq =3D 0, ///< Hardware is responsible for performing c= oefficient/preset search. + PcieLinkFixedEq ///< No coefficient/preset search is performed.= Fixed values are used. +} PCIE_LINK_EQ_METHOD; + +typedef enum { + PcieLinkEqPresetMode =3D 0, ///< Use presets during PCIe link equaliza= tion + PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equal= ization +} PCIE_LINK_EQ_MODE; + +typedef struct { + UINT32 PreCursor; ///< Pre-cursor coefficient + UINT32 PostCursor; ///< Post-cursor coefficient +} PCIE_LINK_EQ_COEFFICIENTS; + +/** + PCIe Link EQ Platform Settings +**/ +typedef struct { + UINT8 PcieLinkEqMethod; ///< Tells BI= OS which link EQ method should be used for this port. Please refer to PCIE_= LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareE= q + UINT8 PcieLinkEqMode; ///< Tells BI= OS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ= _MODE for details of supported modes. Default: depends on SoC + /** + Specifies if BIOS should perform local transmitter override during pha= se 2 of EQ process. + If enabled value in Ph2LocalTransmitterOverridePreset must be valid. + 0: Disabled; 1: Enabled + **/ + UINT8 LocalTransmitterOverrideEnable; + /** + Tells BIOS how many presets/coefficients should be used during link EQ= . + Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chose= n mode) need to be valid up to the number specified in this field. + **/ + UINT8 Ph3NumberOfPresetsOrCoefficients; + + PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS= _MAX]; ///< List of the PCIe coefficients to be used during equalization p= rocess. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode + UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; = ///< List of the PCIe preset values to be used during equalization = process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode + UINT32 Ph1DownstreamPortTransmitterPreset; ///< Spe= cifies the value of the downstream port transmitter preset to be used durin= g phase 1 of the equalization process. Will be applied to all lanes + UINT32 Ph1UpstreamPortTransmitterPreset; ///< Spe= cifies the value of the upstream port transmitter preset to be used during = phase 1 of the equalization process. Will be applied to all lanes + /** + Specifies the preset that should be used during local transmitter over= ride during phase 2 of EQ process. + Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied t= o all PCIe lanes of the root port. + Valid up to the PCIE_LINK_EQ_PRESET_MAX value. Default: 0<\b> + **/ + UINT32 Ph2LocalTransmitterOverridePreset; +} PCIE_LINK_EQ_PLATFORM_SETTINGS; + +#define PCH_PCIE_NO_SUCH_CLOCK 0xFF + +typedef enum { + PchClockUsagePchPcie0 =3D 0, + PchClockUsagePchPcie1 =3D 1, + PchClockUsagePchPcie2 =3D 2, + PchClockUsagePchPcie3 =3D 3, + PchClockUsagePchPcie4 =3D 4, + PchClockUsagePchPcie5 =3D 5, + PchClockUsagePchPcie6 =3D 6, + PchClockUsagePchPcie7 =3D 7, + PchClockUsagePchPcie8 =3D 8, + PchClockUsagePchPcie9 =3D 9, + PchClockUsagePchPcie10 =3D 10, + PchClockUsagePchPcie11 =3D 11, + PchClockUsagePchPcie12 =3D 12, + PchClockUsagePchPcie13 =3D 13, + PchClockUsagePchPcie14 =3D 14, + PchClockUsagePchPcie15 =3D 15, + PchClockUsagePchPcie16 =3D 16, + PchClockUsagePchPcie17 =3D 17, + PchClockUsagePchPcie18 =3D 18, + PchClockUsagePchPcie19 =3D 19, + PchClockUsagePchPcie20 =3D 20, + PchClockUsagePchPcie21 =3D 21, + PchClockUsagePchPcie22 =3D 22, + PchClockUsagePchPcie23 =3D 23, + /** + Quantity of PCH and CPU PCIe ports, as well as their encoding in this = enum, may change between + silicon generations and series. Do not assume that PCH port 0 will be = always encoded by 0. + Instead, it is recommended to use (PchClockUsagePchPcie0 + PchPortInde= x) style to be forward-compatible + **/ + PchClockUsageCpuPcie0 =3D 0x40, + PchClockUsageCpuPcie1 =3D 0x41, + PchClockUsageCpuPcie2 =3D 0x42, + PchClockUsageCpuPcie3 =3D 0x43, + + PchClockUsageLan =3D 0x70, + PchClockUsageUnspecified =3D 0x80, ///< In use for a purpose not liste= d above + PchClockUsageNotUsed =3D 0xFF +} PCH_PCIE_CLOCK_USAGE; + +/** + PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. +**/ +typedef struct { + UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_US= AGE). Default: Unused, 0xFF + UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping= with Clock numbers + UINT8 RsvdBytes[2]; ///< Reserved byte +} PCH_PCIE_CLOCK; + +/** + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability= of each PCH PCIe root port. +**/ +typedef struct { + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie= Common Config + UINT8 ExtSync; ///< Indicate whether the extended synch is= enabled. 0: Disable; 1: Enable. + // + // Error handlings + // + UINT8 SystemErrorEnable; ///< Indicate whether the System Error is e= nabled. 0: Disable; 1: Enable. + /** + The Multiple VC (MVC) supports hardware to avoid HoQ block for latency= sensitive TC. + Currently it is only applicable to Root Ports with 2pX4 port configura= tion with 2 VCs,or + DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, = two RPs (RP0, + RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP= 3) shall be + disabled. + 0: Disable; 1: Enable + **/ + UINT8 MvcEnabled; + /** + Virtual Pin Port is industry standard introduced to PCIe Hot Plug supp= ort in systems + when GPIO pins expansion is needed. It is server specific feature. + 0x00: Default; 0xFF: Disabled + **/ + UINT8 VppPort; + UINT8 VppAddress; ///< PCIe Hot Plug VPP= SMBus Address. Default is zero. + UINT8 RsvdBytes0[3]; ///< Reserved bytes +} PCH_PCIE_ROOT_PORT_CONFIG; + +/** + The PCH_PCIE_CONFIG block describes the expected configuration of the PC= H PCI Express controllers + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCIE_COMMON_CONFIG PcieCommonConfig; + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; + PCIE_LINK_EQ_PLATFORM_SETTINGS PcieLinkEqPlatformSettings; ///< Glob= al PCIe link EQ settings that BIOS will use during PCIe link EQ for every p= ort. + /// + /// 0: Use project default equalization settings; 1: Use equaliza= tion settings from PcieLinkEqPlatformSettings + /// + UINT8 OverrideEqualizationDefaults; + /// + /// (Test) This member describes whether PCIE root port Port 8xh = Decode is enabled. 0: Disable; 1: Enable. + /// + UINT8 EnablePort8xhDecode; + /// + /// (Test) The Index of PCIe Port that is selected for Port8xh De= code (0 Based) + /// + UINT8 PchPciePort8xhDecodePortIndex; + UINT8 RsvdBytes0[1]; +} PCH_PCIE_CONFIG; + +/** + The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the= PCH PCI Express controllers + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config= Block Header + /** + Root Port enabling mask. + Bit0 presents RP1, Bit1 presents RP2, and so on. + 0: Disable; 1: Enable. + **/ + UINT32 RpEnabledMask; + /// Configuration of PCIe source clocks + /// + PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS]; + + /** + Per Controller Bifurcation Configuration + 0: Disabled; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4= _2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG) + **/ + UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS]; + UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4]; +} PCH_PCIE_RP_PREMEM_CONFIG; + +/** + The PCIE_RP_DXE_CONFIG block describes the expected configuration of the= PCH PCI Express controllers in DXE phase + + Revision 1: + - Init version +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block H= eader + + /** + PCIe device override table + The PCIe device table is being used to override PCIe device ASPM setti= ngs. + And it's only used in DXE phase. + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. + Last entry VendorId must be 0. + **/ + PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr; +} PCIE_RP_DXE_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_PCIERP_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/P= cieConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/= PcieConfig.h new file mode 100644 index 0000000000..4c5b075334 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConf= ig.h @@ -0,0 +1,217 @@ +/** @file + PCIe Config Block + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCIE_CONFIG_H_ +#define _PCIE_CONFIG_H_ +#include + +#define PCIE_CONFIG_REVISION 3 +/* +Revision 2< / b>: +FomsCp - Deprecated +Revision 3< / b>: +Added PCIE_EQ_PARAM HwEqGen3CoeffList for all CPU_PCIE_MAX_ROOT_PORTS +Added PCIE_EQ_PARAM HwEqGen4CoeffList for all CPU_PCIE_MAX_ROOT_PORTS +Added PCIE_EQ_PARAM HwEqGen5CoeffList for all CPU_PCIE_MAX_ROOT_PORTS +*/ + +extern EFI_GUID gPcieConfigGuid; + +#pragma pack (push,1) + +enum PCIE_COMPLETION_TIMEOUT { + PcieCompletionTO_Default, + PcieCompletionTO_50_100us, + PcieCompletionTO_1_10ms, + PcieCompletionTO_16_55ms, + PcieCompletionTO_65_210ms, + PcieCompletionTO_260_900ms, + PcieCompletionTO_1_3P5s, + PcieCompletionTO_4_13s, + PcieCompletionTO_17_64s, + PcieCompletionTO_Disabled +}; + +enum PCIE_SPEED { + PcieAuto, + PcieGen1, + PcieGen2, + PcieGen3, + PcieGen4 +}; + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCIE_EQ_PARAM; + +typedef struct { + UINT16 LtrMaxSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Value. + UINT8 LtrConfigLock; ///< 0: Disable; = 1: Enable. + UINT8 ForceLtrOverride; + UINT16 RsvdByte1; +} PCIE_LTR_CONFIG; + + +/** + Specifies the form factor that the slot + implements. For custom form factors that + do not require any special handling please + set PcieFormFactorOther. +**/ +typedef enum { + PcieFormFactorOther =3D 0, + PcieFormFactorCem, + PcieFormFactorMiniPci, + PcieFormFactorM2, + PcieFormFactorOcuLink, + PcieFormFactorExpressModule, // Also known as Server IO module(SIOM) + PcieFormFactorExpressCard, + PcieFormFactorU2 // Also known as SF-8639 +} PCIE_FORM_FACTOR; + +//Note: This structure will be expanded to hold all common PCIe policies b= etween SA and PCH RootPort +typedef struct { + UINT32 HotPlug : 1; ///< Indicate whether th= e root port is hot plug available. 0: Disable; 1: Enable. + UINT32 PmSci : 1; ///< Indicate whether th= e root port power manager SCI is enabled. 0: Disable; 1: Enable. + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether th= e Transmitter Half Swing is enabled. 0: Disable; 1: Enable. + UINT32 AcsEnabled : 1; ///< Indicate whether th= e ACS is enabled. 0: Disable; 1: Enable. + // + // Error handlings + // + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether th= e Advanced Error Reporting is enabled. 0: Disable; 1: Enable. + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether th= e Unsupported Request Report is enabled. 0: Disable; 1: Enable. + UINT32 FatalErrorReport : 1; ///< Indicate whether th= e Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 NoFatalErrorReport : 1; ///< Indicate whether th= e No Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 CorrectableErrorReport : 1; ///< Indicate whether th= e Correctable Error Report is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether th= e System Error on Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether th= e System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether th= e System Error on Correctable Error is enabled. 0: Disable; 1: Enabl= e. + /** + Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX= _PAYLOAD + Changes Max Payload Size Supported field in Device Capabilities of the= root port. + **/ + UINT32 MaxPayload : 2; + UINT32 DpcEnabled : 1; ///< Downstream Port Con= tainment. 0: Disable; 1: Enable + UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for D= ownstream Port Containment. 0: Disable; 1: Enable + /** + Indicates how this root port is connected to endpoint. 0: built-in dev= ice; 1: slot + Built-in is incompatible with hotplug-capable ports. + **/ + UINT32 SlotImplemented : 1; + UINT32 PtmEnabled : 1; ///< Enables PTM capabil= ity + UINT32 SlotPowerLimitScale : 2; ///< (Test) Speci= fies scale used for slot power limit value. Leave as 0 to set to default. D= efault is zero. + UINT32 SlotPowerLimitValue : 12; //< (Test) Specif= ies upper limit on power supplies by slot. Leave as 0 to set to default. De= fault is zero. + /** + Probe CLKREQ# signal before enabling CLKREQ# based power management. + Conforming device shall hold CLKREQ# low until CPM is enabled. This fe= ature attempts + to verify CLKREQ# signal is connected by testing pad state before enab= ling CPM. + In particular this helps to avoid issues with open-ended PCIe slots. + This is only applicable to non hot-plug ports. + 0: Disable; 1: Enable. + **/ + UINT32 ClkReqDetect : 1; + /** + Set if the slot supports manually operated retention latch. + **/ + UINT32 MrlSensorPresent : 1; + UINT32 RelaxedOrder : 1; + UINT32 NoSnoop : 1; + UINT32 RsvdBits0 : 28; ///< Reserved bits. + /** + PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD). + 0: DEPRECATED, hardware equalization; 1: hardware equalization;= 4: Fixed Coefficients + **/ + UINT8 Gen3EqPh3Method; + UINT8 PhysicalSlotNumber; ///< Indicates the slot = number for the root port. Default is the value as root port index. + UINT8 CompletionTimeout; ///< The completion time= out configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Defa= ult is PchPcieCompletionTO_Default. + // + // Power Management + // + UINT8 Aspm; ///< The ASPM configurat= ion of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is PchPcieAsp= mAutoConfig. + UINT8 L1Substates; ///< The L1 Substates co= nfiguration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default i= s PchPcieL1SubstatesL1_1_2. + UINT8 LtrEnable; ///< Latency Tolerance R= eporting Mechanism. 0: Disable; 1: Enable. + UINT8 EnableCpm; ///< Enables Clock Power= Management; even if disabled, CLKREQ# signal can still be controlled by L1= PM substates mechanism + UINT8 PcieSpeed; ///< Contains speed of P= CIe bus (see: PCIE_SPEED) + /** + (Test) + Forces LTR override to be permanent + The default way LTR override works is: + rootport uses LTR override values provided by BIOS until connected devic= e sends an LTR message, then it will use values from the message + This settings allows force override of LTR mechanism. If it's enabled, t= hen: + rootport will use LTR override values provided by BIOS forever; LTR mess= ages sent from connected device will be ignored + **/ + PCIE_LTR_CONFIG PcieRpLtrConfig; ///< (Test)= Latency Tolerance Reporting Policies including LTR limit and Override + /** + The number of milliseconds reference code will wait for link to exit D= etect state for enabled ports + before assuming there is no device and potentially disabling the port. + It's assumed that the link will exit detect state before root port ini= tialization (sufficient time + elapsed since PLTRST de-assertion) therefore default timeout is zero. = However this might be useful + if device power-up seqence is controlled by BIOS or a specific device = requires more time to detect. + In case of non-common clock enabled the default timout is 15ms. + Default: 0 + **/ + UINT16 DetectTimeoutMs; + UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported value= s + UINT8 Reserved; +} PCIE_ROOT_PORT_COMMON_CONFIG; + +/** + PCIe Common Config + @note This structure will be expanded to hold all common PCIe policies b= etween SA and PCH +**/ +typedef struct { + /// + /// This member describes whether Peer Memory Writes are enabled on the = platform. 0: Disable; 1: Enable. + /// + UINT32 EnablePeerMemoryWrite : 1; + /** + RpFunctionSwap allows BIOS to use root port function number swapping w= hen root port of function 0 is disabled. + A PCIE device can have higher functions only when Function0 exists. To= satisfy this requirement, + BIOS will always enable Function0 of a device that contains more than = 0 enabled root ports. + - Enabled: One of enabled root ports get assigned to Function0. + This offers no guarantee that any particular root port will be avail= able at a specific DevNr:FuncNr location + - Disabled: Root port that corresponds to Function0 will be kept visib= le even though it might be not used. + That way rootport - to - DevNr:FuncNr assignment is constant. This o= ption will impact ports 1, 9, 17. + NOTE: This option will not work if ports 1, 9, 17 are fused or confi= gured for RST PCIe storage or disabled through policy + In other words, it only affects ports that would become hidden= because they have no device connected. + NOTE: Disabling function swap may have adverse impact on power manag= ement. This option should ONLY + be used when each one of root ports 1, 9, 17: + - is configured as PCIe and has correctly configured ClkReq signal= , or + - does not own any mPhy lanes (they are configured as SATA or USB) + **/ + UINT32 RpFunctionSwap : 1; + /** + Compliance Test Mode shall be enabled when using Compliance Load Board= . + 0: Disable, 1: Enable + **/ + UINT32 ComplianceTestMode : 1; + UINT32 RsvdBits0 : 29; ///< Reserved bits + /// + /// List of coefficients used during equalization (applicable to both so= ftware and hardware EQ) + /// Deprecated Policy + /// + PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX]= ; +} PCIE_COMMON_CONFIG; + +typedef struct { + PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_= ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX]; + PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_= ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX]; +} PCIE_COMMON_CONFIG2; + +#pragma pack (pop) +#endif // _PCIE_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConf= ig.h new file mode 100644 index 0000000000..5c7811823d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h @@ -0,0 +1,86 @@ +/** @file + ADR policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ADR_CONFIG_H_ +#define _ADR_CONFIG_H_ + +#include + +#define ADR_CONFIG_REVISION 1 +extern EFI_GUID gAdrConfigGuid; + +#pragma pack (push,1) + +typedef enum { + AdrScale1us, + AdrScale10us, + AdrScale100us, + AdrScale1ms, + AdrScale10ms, + AdrScale100ms, + AdrScale1s, + AdrScale10s +} ADR_TIMER_SCALE; + +/** + ADR Source Enable +**/ +typedef union { + struct { + UINT32 Reserved1 : 1; + UINT32 AdrSrcPbo : 1; + UINT32 AdrSrcPmcUncErr : 1; + UINT32 AdrSrcPchThrm : 1; + UINT32 AdrSrcMePbo : 1; + UINT32 AdrSrcCpuThrm : 1; + UINT32 AdrSrcMegbl : 1; + UINT32 AdrSrcLtReset : 1; + UINT32 AdrSrcPmcWdt : 1; + UINT32 AdrSrcMeWdt : 1; + UINT32 AdrSrcPmcFw : 1; + UINT32 AdrSrcPchpwrFlr : 1; + UINT32 AdrSrcSyspwrFlr : 1; + UINT32 Reserved2 : 1; + UINT32 AdrSrcMiaUxsErr : 1; + UINT32 AdrSrcMiaUxErr : 1; + UINT32 AdrSrcCpuThrmWdt : 1; + UINT32 AdrSrcMeUncErr : 1; + UINT32 AdrSrcAdrGpio : 1; + UINT32 AdrSrcOcwdtNoicc : 1; + UINT32 AdrSrcOcwdtIcc : 1; + UINT32 AdrSrcCseHecUncErr : 1; + UINT32 AdrSrcPmcSramUncErr : 1; + UINT32 AdrSrcPmcIromParity : 1; + UINT32 AdrSrcPmcRfFusaErr : 1; + UINT32 Reserved3 : 4; + UINT32 AdrSrcPpbrParityErr : 1; + UINT32 Reserved4 : 2; + } Field; + UINT32 Value; +} ADR_SOURCE_ENABLE; + +/** + ADR Configuration + Revision 1: - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 AdrEn : 2; ///< Determine if Adr is enabl= ed - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE + UINT32 AdrTimerEn : 2; ///< Determine if Adr timer op= tions are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE + UINT32 AdrTimer1Val : 2; ///< Determines the Timeout va= lue used for the ADR timer 1. A value of zero bypasses the timer + UINT32 AdrMultiplier1Val : 8; ///< Specifies the tick freque= ncy upon which the timer 1 will increment. ADR_TIMER_SCALE should be used t= o encode values + UINT32 AdrTimer2Val : 8; ///< Determines the Timeout va= lue used for the ADR timer 2. A value of zero bypasses the timer + UINT32 AdrMultiplier2Val : 8; ///< Specifies the tick freque= ncy upon which the timer 2 will increment. ADR_TIMER_SCALE should be used t= o encode values + UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partiti= on Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE + UINT32 AdrSrcOverride : 1; ///< Check if default ADR sour= ces will be overriten with custom 0: Not overwritten, 1: Overwritten + UINT32 ReservedBits : 31; + ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR sourc= es are enabled - 0: Enabled, 1: Disabled +} ADR_CONFIG; + +#pragma pack (pop) + +#endif // _ADR_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmCo= nfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig= .h new file mode 100644 index 0000000000..2f8e19b50b --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h @@ -0,0 +1,391 @@ +/** @file + Power Management policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PM_CONFIG_H_ +#define _PM_CONFIG_H_ + +#include + +#define PM_CONFIG_REVISION 2 +extern EFI_GUID gPmConfigGuid; + +#pragma pack (push,1) + +/** + This structure allows to customize PCH wake up capability from S5 or Dee= pSx by WOL, LAN, PCIE wake events. +**/ +typedef struct { + /** + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B= (GEN_PMCON_B) register. + When set to 1, this bit blocks wake events from PME_B0_STS in S5, rega= rdless of the state of PME_B0_EN. + When cleared (default), wake events from PME_B0_STS are allowed in S5 = if PME_B0_EN =3D 1. 0: Disable; 1: Enable. + **/ + UINT32 PmeB0S5Dis : 1; + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enabl= e Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0= : Disable; 1: Enable. + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to w= ake from deep Sx. 0: Disable; 1: Enable. + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from S= x, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0= : Disable; 1: Enable. + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from D= eepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <= b>0: Disable; 1: Enable. + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wa= ke from deep Sx. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 26; +} PCH_WAKE_CONFIG; + +typedef enum { + PchDeepSxPolDisable, + PchDpS5BatteryEn, + PchDpS5AlwaysEn, + PchDpS4S5BatteryEn, + PchDpS4S5AlwaysEn, + PchDpS3S4S5BatteryEn, + PchDpS3S4S5AlwaysEn +} PCH_DEEP_SX_CONFIG; + +typedef enum { + PchSlpS360us =3D 1, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing a= nd Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef enum { + PchSlpSus0ms =3D 1, + PchSlpSus500ms, + PchSlpSus1s, + PchSlpSus4s, +} PCH_SLP_SUS_MIN_ASSERT; + +typedef enum { + PchSlpA0ms =3D 1, + PchSlpA4s, + PchSlpA98ms, + PchSlpA2s, +} PCH_SLP_A_MIN_ASSERT; + +typedef enum { + S0ixDisQNoChange, + S0ixDisQDciOob, + S0ixDisQUsb2Dbc, + S0ixDisQMax, +} S0IX_DISQ_PROBE_TYPE; + +/** + Low Power Mode Enable config. + Used to configure if respective S0i2/3 sub-states are to be supported + by the platform. Each bit corresponds to one LPM state - LPMx->BITx. + Some sub-states will require external FETs controlled by EXT_PWR_GATE#/E= XT_PWR_GATE2# pins + to gate v1p05-PHY or v1p05-IS supplies +**/ +typedef union { + struct { + UINT32 S0i2p0En : 1; ///< LPM0 - S0i2.0 Enable + UINT32 S0i2p1En : 1; ///< LPM1 - S0i2.1 Enable + /** + LPM2 - S0i2.2 Enable. + Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. + Refer to V1p05PhyExtFetControlEn. + **/ + UINT32 S0i2p2En : 1; + UINT32 S0i3p0En : 1; ///< LPM3 - S0i3.0 Enable + UINT32 S0i3p1En : 1; ///< LPM4 - S0i3.1 Enable + UINT32 S0i3p2En : 1; ///< LPM5 - S0i3.2 Enable + /** + LPM5 - S0i3.3 Enable. + Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY. + Refer to V1p05PhyExtFetControlEn. + **/ + UINT32 S0i3p3En : 1; + /** + LPM7 - S0i3.4 Enable. + Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK. + Refer to V1p05IsExtFetControlEn. + **/ + UINT32 S0i3p4En : 1; + UINT32 Reserved : 24; ///< Reserved + } Field; + UINT32 Val; +} PMC_LPM_S0IX_SUB_STATE_EN; + +/** + Description of Global Reset Trigger/Event Mask register +**/ +typedef union { + struct { + UINT32 Reserved1 : 1; + UINT32 Pbo : 1; + UINT32 PmcUncErr : 1; + UINT32 PchThrm : 1; + UINT32 MePbo : 1; + UINT32 CpuThrm : 1; + UINT32 Megbl : 1; + UINT32 LtReset : 1; + UINT32 PmcWdt : 1; + UINT32 MeWdt : 1; + UINT32 PmcFw : 1; + UINT32 PchpwrFlr : 1; + UINT32 SyspwrFlr : 1; + UINT32 Reserved2 : 1; + UINT32 MiaUxsErr : 1; + UINT32 MiaUxErr : 1; + UINT32 CpuThrmWdt : 1; + UINT32 MeUncErr : 1; + UINT32 AdrGpio : 1; + UINT32 OcwdtNoicc : 1; + UINT32 OcwdtIcc : 1; + UINT32 CseHecUncErr : 1; + UINT32 PmcSramUncErr : 1; + UINT32 PmcIromParity : 1; + UINT32 PmcRfFusaErr : 1; + UINT32 Reserved3 : 4; + UINT32 PpbrParityErr : 1; + UINT32 Reserved4 : 2; + } Field; + UINT32 Value; +} PMC_GLOBAL_RESET_MASK; + +/** + The PCH_PM_CONFIG block describes expected miscellaneous power managemen= t settings. + The PowerResetStatusClear field would clear the Power/Reset status bits,= please + set the bits if you want PCH Init driver to clear it, if you want to che= ck the + status later then clear the bits. + + Revision 1: + - Initial version. + Revision 2 + - Added C10DynamicThresholdAdjustment +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Bl= ock Header + + PCH_WAKE_CONFIG WakeConfig; ///< Specify W= ake Policy + UINT32 PchDeepSxPol : 4; ///< Deep Sx P= olicy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxP= olDisable. + UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Mi= nimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value= . Default is PchSlpS350ms. + UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Mi= nimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value= . Default is PchSlpS44s. + UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS M= inimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each val= ue. Default is PchSlpSus4s. + UINT32 PchSlpAMinAssert : 4; ///< SLP_A Min= imum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. = Default is PchSlpA2s. + UINT32 RsvdBits0 : 12; + /** + This member describes whether or not the LPC ClockRun feature of PCH s= hould + be enabled. 0: Disable; 1: Enable + **/ + UINT32 SlpStrchSusUp : 1; ///< 0: Dis= able; 1: Enable SLP_X Stretching After SUS Well Power Up + /** + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; 1: Enable. + Configure On DC PHY Power Diable according to policy SlpLanLowDc. + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is lo= w. + This indicates that LAN PHY should be powered off on battery mode. + This will override the DC_PP_DIS setting by WolEnableOverride. + **/ + UINT32 SlpLanLowDc : 1; + /** + PCH power button override period. + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s + Default is 0: 4s + **/ + UINT32 PwrBtnOverridePeriod : 3; + /** + (Test) + Disable/Enable PCH to CPU enery report feature. 0: Disable; 1: = Enable. + Enery Report is must have feature. Wihtout Energy Report, the performa= nce report + by workloads/benchmarks will be unrealistic because PCH's energy is no= t being accounted + in power/performance management algorithm. + If for some reason PCH energy report is too high, which forces CPU to = try to reduce + its power by throttling, then it could try to disable Energy Report to= do first debug. + This might be due to energy scaling factors are not correct or the LPM= settings are not + kicking in. + **/ + UINT32 DisableEnergyReport : 1; + /** + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX= and during G3 exit. + When set to Enable, PCH will not pull down AC_PRESENT. + This setting is ignored when DeepSx is not supported. + Default is 0:Disable + **/ + UINT32 DisableDsxAcPresentPulldown : 1; + /** + Power button native mode disable. + While FALSE, the PMC's power button logic will act upon the input valu= e from the GPIO unit, as normal. + While TRUE, this will result in the PMC logic constantly seeing the po= wer button as de-asserted. + Default is FALSE. + **/ + UINT32 DisableNativePowerButton : 1; + UINT32 MeWakeSts : 1; ///< Clea= r the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Di= sable; 1: Enable. + UINT32 WolOvrWkSts : 1; ///< Clea= r the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0:= Disable; 1: Enable. + /* + Set true to enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. + @note: This will have significant power impact when it's enabled. + If TCO timer is disabled, uCode ACPI timer emulation must be enabled, + and WDAT table must not be exposed to the OS. + 0: Disable, 1: Enable + */ + UINT32 EnableTcoTimer : 1; + /* + When VRAlert# feature pin is enabled and its state is '0', + the PMC requests throttling to a T3 Tstate to the PCH throttling unit. + 0: Disable; 1: Enable. + */ + UINT32 VrAlert : 1; + /** + Decide if PS_ON is to be enabled. This is available on desktop only. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a + lower power target that will be required by the California Energy + Commission (CEC). When FALSE, PS_ON is to be disabled.} + 0: Disable; 1: Enable. + **/ + UINT32 PsOnEnable : 1; + /** + Enable/Disable platform support for CPU_C10_GATE# pin to control gatin= g + of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy need= s + to be set if board design includes support for CPU_C10_GATE# pin. + 0: Disable; 1: Enable + **/ + UINT32 CpuC10GatePinEnable : 1; + /** + Control whether to enable PMC debug messages to Trace Hub. + When Enabled, PMC HW will send debug messages to trace hub; + When Disabled, PMC HW will never send debug meesages to trace hub. + @note: When enabled, system may not enter S0ix + 0: Disable; 1: Enable. + **/ + UINT32 PmcDbgMsgEn : 1; + /** + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. + EXT_PWR_GATE# signal (if supported on platform) can be used to + control external FET for power gating ModPHY + @note: This setting is not supported and ignored on PCH-H + 0: Disable; 1: Enable. + **/ + UINT32 ModPhySusPgEnable : 1; + /** + (Test) + This policy option enables USB2 PHY SUS Well Power Gating functionalit= y. + @note: This setting is not supported and ignored on PCH-H + 0: disable USB2 PHY SUS Well Power Gating + 1: enable USB2 PHY SUS Well Power Gating + **/ + UINT32 Usb2PhySusPgEnable : 1; + /** + Enable Os Idle Mode. + 0: Disable; 1: Enable. + **/ + UINT32 OsIdleEnable : 1; + /** + Enable control using EXT_PWR_GATE# pin of external FET + to power gate v1p05-PHY + 0: Disable; 1: Enable. + **/ + UINT32 V1p05PhyExtFetControlEn : 1; + /** + Enable control using EXT_PWR_GATE2# pin of external FET + to power gate v1p05-IS supply + 0: Disable; 1: Enable. + **/ + UINT32 V1p05IsExtFetControlEn : 1; + /** + Enable/Disable the Low Power Mode Host S0ix Auto-Demotion + feature. This feature enables the PMC to autonomously manage + the deepest allowed S0ix substate to combat thrashing between + power management states. + 0: Disable; 1: Enable. + **/ + UINT32 S0ixAutoDemotion : 1; + /** + Enable/Disable Latch Events C10 Exit. When this bit is set to 1, + SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured + on C10 exit (instead of C10 entry which is default) + 0: Disable; 1: Enable. + **/ + UINT32 LatchEventsC10Exit : 1; + UINT32 RsvdBits1 : 10; + /* + Power button debounce configuration + Debounce time can be specified in microseconds. Only certain values ac= cording + to below formula are supported: + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock perio= d). + RTC clock with f =3D 32 KHz is used for glitch filter. + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us). + Supported DebounceTime values are following: + DebounceTime =3D 0 -> Debounce feature disabled + DebounceTime > 0 && < 250us -> Not supported + DebounceTime =3D 250us - 1024000us -> Supported range (DebounceTime = =3D 250us * 2^n) + For values not supported by HW, they will be rounded down to closest s= upported one + Default is 0 + */ + UINT32 PowerButtonDebounce; + /** + Reset Power Cycle Duration could be customized in the unit of second. = Please refer to EDS + for all support settings. PCH HW default is 4 seconds, and range is 1~= 4 seconds, where + 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds= . + And make sure the setting correct, which never less than the following= register. + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH + - PWRM_CFG.SLP_A_MIN_ASST_WDTH + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH + **/ + UINT8 PchPwrCycDur; + /** + Specifies the Pcie Pll Spread Spectrum Percentage + The value of this policy is in 1/10th percent units. + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% + The default is 0xFF: AUTO - No BIOS override. + **/ + UINT8 PciePllSsc; + /** + Tells BIOS to enable C10 dynamic threshold adjustment mode. + BIOS will only attemt to enable it on PCH SKUs which support it. + **/ + UINT8 C10DynamicThresholdAdjustment; + UINT8 Rsvd0[1]; ///< Reser= ved bytes + /** + (Test) + Low Power Mode Enable/Disable config. + Configure if respective S0i2/3 sub-states are to be supported + by the platform. By default all sub-states are enabled but + for test purpose respective states can be disabled. + Default is 0xFF + **/ + PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable; + /* + Set true to enable Timed GPIO 0 timer. + 0: Disable, 1: Enable + */ + UINT32 EnableTimedGpio0 : 1; + /* + Set true to enable Timed GPIO 1 timer. + 0: Disable, 1: Enable + */ + UINT32 EnableTimedGpio1 : 1; + UINT32 Rsvdbits : 30; + + /** + Set true to enable override of Global Reset Event/Trigger masks. + Values from GlobalResetTriggerMask and GlobalResetEventMask will + be used as override value. + 0: Disable, 1: Enable + **/ + UINT8 GlobalResetMasksOverride; + UINT8 Rsvd1[3]; ///< Reserved bytes + /* + Mask for enabling Global Reset Trigger prevention + */ + PMC_GLOBAL_RESET_MASK GlobalResetTriggerMask; + /* + Mask for enabling Global Reset Event prevention + */ + PMC_GLOBAL_RESET_MASK GlobalResetEventMask; +} PCH_PM_CONFIG; + +#pragma pack (pop) + +#endif // _PM_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConf= ig.h new file mode 100644 index 0000000000..033e416b83 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h @@ -0,0 +1,32 @@ +/** @file + Primary Sideband Fabric policy. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PSF_CONFIG_H_ +#define _PSF_CONFIG_H_ + +#define PSF_CONFIG_REVISION 1 +extern EFI_GUID gPsfConfigGuid; + +#pragma pack (push,1) + +/** + The PSF_CONFIG block describes the expected configuration of the Primary + Sideband Fabric. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Psf Tcc (Time Coordinated Computing) Enable will decrease psf transact= ion latency by disable + some psf power management features. 0: Disable; 1: Enable. + **/ + UINT32 TccEnable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PSF_CONFIG; + +#pragma pack (pop) + +#endif // _PSF_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConf= ig.h new file mode 100644 index 0000000000..469d46a205 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h @@ -0,0 +1,82 @@ +/** @file + Rst policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _RST_CONFIG_H_ +#define _RST_CONFIG_H_ +#include +#include + +#define RST_CONFIG_REVISION 1 +extern EFI_GUID gRstConfigGuid; + +#pragma pack (push,1) + +typedef enum { + SataOromDelay2sec, + SataOromDelay4sec, + SataOromDelay6sec, + SataOromDelay8sec +} SATA_OROM_DELAY; + +/** + This structure describes the details of Intel RST for PCIe Storage remap= ping + Note: In order to use this feature, Intel RST Driver is required +**/ +typedef struct { + /** + This member describes whether or not the Intel RST for PCIe Storage re= mapping should be enabled. 0: Disable; 1: Enable. + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should = be disabled as well + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI = controllers Class Code is configured as RAID + **/ + UINT32 Enable : 1; + /** + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <= b>0 =3D autodetect) + The supported ports for PCIe Storage remapping is different depend on = the platform and cycle router + **/ + UINT32 RstPcieStoragePort : 5; + /** + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarant= ees such delay gap is fulfilled + before PCIe Storage Device configuration space is accessed after an re= set caused by the link disable and enable step. + Default value is 100ms. + **/ + UINT32 DeviceResetDelay : 8; + UINT32 RsvdBits0 : 18; ///< Reserved bits + +} RST_HARDWARE_REMAPPED_STORAGE_CONFIG; + +/** + Rapid Storage Technology settings. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Bl= ock Header + + UINT32 Raid0 : 1; ///< 0 : Disable; 1 : Enab= le RAID0 + UINT32 Raid1 : 1; ///< 0 : Disable; 1 : Enab= le RAID1 + UINT32 Raid10 : 1; ///< 0 : Disable; 1 : Enab= le RAID10 + UINT32 Raid5 : 1; ///< 0 : Disable; 1 : Enab= le RAID5 + UINT32 Irrt : 1; ///< 0 : Disable; 1 : Enab= le Intel Rapid Recovery Technology + UINT32 OromUiBanner : 1; ///< 0 : Disable; 1 : Enab= le OROM UI and BANNER + UINT32 OromUiDelay : 2; ///< 00b : 2 secs; 01b = : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY) + UINT32 HddUnlock : 1; ///< 0 : Disable; 1 : Enab= le. Indicates that the HDD password unlock in the OS is enabled + UINT32 LedLocate : 1; ///< 0 : Disable; 1 : Enab= le. Indicates that the LED/SGPIO hardware is attached and ping to locat= e feature is enabled on the OS + UINT32 IrrtOnly : 1; ///< 0 : Disable; 1 : Enab= le. Allow only IRRT drives to span internal and external ports + UINT32 SmartStorage : 1; ///< 0 : Disable; 1 : Enab= le RST Smart Storage caching Bit + UINT32 LegacyOrom : 1; ///< 0 : Disable; 1 : = Enable RST Legacy OROM + UINT32 OptaneMemory : 1; ///< 0: Disable; 1: Enable RST Optane(TM) Memory + UINT32 CpuAttachedStorage : 1; ///< 0: Disable; 1: Enable CPU Attached Storage + UINT32 RsvdBits0 : 17; ///< Reserved Bits + /** + This member describes the details of implementation of Intel RST for P= CIe Storage remapping (Intel RST Driver is required) + Note: RST for PCIe Sorage remapping is supported only for first SATA c= ontroller if more controllers are available + **/ + RST_HARDWARE_REMAPPED_STORAGE_CONFIG HardwareRemappedStorageConfig[PCH= _MAX_RST_PCIE_STORAGE_CR]; +} RST_CONFIG; + +#pragma pack (pop) +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConf= ig.h new file mode 100644 index 0000000000..1f354c10ae --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h @@ -0,0 +1,38 @@ +/** @file + RTC policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _RTC_CONFIG_H_ +#define _RTC_CONFIG_H_ + +#define RTC_CONFIG_REVISION 1 +extern EFI_GUID gRtcConfigGuid; + +#pragma pack (push,1) + +/** + The RTC_CONFIG block describes the expected configuration of RTC configu= ration. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + When set, prevents RTC TS (BUC.TS) from being changed. + This BILD bit has different function compared to LPC/eSPI, SPI. + 0: Disabled; 1: Enabled + **/ + UINT32 BiosInterfaceLock : 1; + /** + When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are lock= ed + and cannot be accessed. + Writes will be droipped and reads will not return any guaranteed data. + 0: Disabled; 1: Enabled + **/ + UINT32 MemoryLock : 1; + UINT32 RsvdBits0 : 30; +} RTC_CONFIG; + +#pragma pack (pop) + +#endif // _RTC_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/Sat= aConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/Sata= Config.h new file mode 100644 index 0000000000..c560fdd3ab --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig= .h @@ -0,0 +1,168 @@ +/** @file + Sata policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SATA_CONFIG_H_ +#define _SATA_CONFIG_H_ + +#include + +#define SATA_CONFIG_REVISION 1 +extern EFI_GUID gSataConfigGuid; + +#pragma pack (push,1) + +typedef enum { + SataModeAhci, + SataModeRaid, + SataModeMax +} SATA_MODE; + +typedef enum { + SataSpeedDefault, + SataSpeedGen1, + SataSpeedGen2, + SataSpeedGen3 +} SATA_SPEED; + +typedef enum { + SataRstMsix, + SataRstMsi, + SataRstLegacy +} SATA_RST_INTERRUPT; + +typedef enum { + SataRaidClient, + SataRaidAlternate, + SataRaidServer +} SATA_RAID_DEV_ID; + +/** + This structure configures the features, property, and capability for eac= h SATA port. +**/ +typedef struct { + /** + Enable SATA port. + It is highly recommended to disable unused ports for power savings + **/ + UINT32 Enable : 1; ///< 0: Disable; 1: E= nable + UINT32 HotPlug : 1; ///< 0: Disable; = 1: Enable + UINT32 InterlockSw : 1; ///< 0: Disable; = 1: Enable + UINT32 External : 1; ///< 0: Disable; = 1: Enable + UINT32 SpinUp : 1; ///< 0: Disable; = 1: Enable the COMRESET initialization Sequence to the device + UINT32 SolidStateDrive : 1; ///< 0: HDD; 1: S= SD + UINT32 DevSlp : 1; ///< 0: Disable; = 1: Enable DEVSLP on the port + UINT32 EnableDitoConfig : 1; ///< 0: Disable; = 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal) + UINT32 DmVal : 4; ///< DITO multiplier. De= fault is 15. + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout= (DITO), Default is 625. + /** + Support zero power ODD 0: Disable, 1: Enable. + This is also used to disable ModPHY dynamic power gate. + **/ + UINT32 ZpOdd : 1; + UINT32 DevSlpResetConfig : 4; ///< 0: Hardware default= ; 0x01: GpioResumeReset; 0x03: GpioHostDeepReset; 0x05: GpioPlatform= Reset; 0x07: GpioDswReset + UINT32 SataPmPtm : 1; ///< Deprecated + UINT32 RxPolarity : 1; ///< 0: Disable; = 1: Enable; Rx Polarity + UINT32 RsvdBits0 : 3; ///< Reserved fields for= future expansion w/o protocol change +} PCH_SATA_PORT_CONFIG; + +/** + This structure lists PCH supported SATA thermal throttling register sett= ing for customization. + The settings is programmed through SATA Index/Data registers. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch + + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch + + UINT32 P0Tinact : 2; ///< Port 0 Tinactive + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Td= ispatch + UINT32 P1Tinact : 2; ///< Port 1 Tinactive + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Td= ispatch + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values + UINT32 RsvdBits0 : 9; ///< Reserved bits +} SATA_THERMAL_THROTTLING; + +/** + The SATA_CONFIG block describes the expected configuration of the SATA = controllers. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Bl= ock Header + /// + /// This member describes whether or not the SATA controllers should be = enabled. 0: Disable; 1: Enable. + /// + UINT8 Enable; + UINT8 TestMode; ///< (Test) 0: D= isable; 1: Allow entrance to the PCH SATA test modes + UINT8 SalpSupport; ///< 0: Disable; 1: Ena= ble Aggressive Link Power Management + UINT8 PwrOptEnable; ///< 0: Disable; 1: Ena= ble SATA Power Optimizer on PCH side. + /** + EsataSpeedLimit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSA= TA port speed. + Please be noted, this setting could be cleared by HBA reset, which mig= ht be issued + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver = after POST. + To support the Speed Limitation when POST, the EFI AHCI driver should = preserve the + setting before and after initialization. For support it after POST, it= 's dependent on + driver's behavior. + 0: Disable; 1: Enable + **/ + UINT8 EsataSpeedLimit; + UINT8 LedEnable; ///< SATA LED indicates S= ATA controller activity. 0: Disable; 1: Enable SATA LED. + /** + This option allows to configure SATA controller device ID while in RAI= D mode. + Refer to SATA_RAID_DEV_ID enumeration for supported options. + Choosing Client will allow RST driver loading, RSTe driver will not be= able to load + Choosing Alternate will not allow RST inbox driver loading in Windows + Choosing Server will allow RSTe driver loading, RST driver will not lo= ad + 0: Client; 1: Alternate; 2: Server + **/ + UINT8 RaidDeviceId; + /** + Controlls which interrupts will be linked to SATA controller CAP list + This option will take effect only if SATA controller is in RAID mode + Default: PchSataMsix + **/ + UINT8 SataRstInterrupt; + + /** + Determines the system will be configured to which SATA mode. + Refer to SATA_MODE enumeration for supported options. Default is Sa= taModeAhci. + **/ + UINT8 SataMode; + /** + Indicates the maximum speed the SATA controller can support. + Refer to SATA_SPEED enumeration for supported options. + 0h: SataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); = 3h: 6 Gb/s (Gen 1) + **/ + UINT8 SpeedLimit; + UINT8 EnclosureSupport; ///< Enclosure Managem= ent Support. 0: Disable; 1: Enable + /** + Controlls whenever Serial GPIO support is enabled for controller + 0: Disable; 1: Enable + **/ + UINT8 SgpioSupport; + /** + This member configures the features, property, and capability for each= SATA port. + **/ + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; + /** + This field decides the settings of Sata thermal throttling. When the S= uggested Setting + is enabled, PCH RC will use the suggested representative values. + **/ + SATA_THERMAL_THROTTLING ThermalThrottling; +} SATA_CONFIG; + +#pragma pack (pop) + +#endif // _SATA_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConf= ig.h new file mode 100644 index 0000000000..2ebc901896 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h @@ -0,0 +1,139 @@ +/** @file + Scs policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SCS_CONFIG_H_ +#define _SCS_CONFIG_H_ + +#include +#include + +#define SCS_SDCARD_CONFIG_REVISION 1 +#define SCS_EMMC_CONFIG_REVISION 1 +#define SCS_EMMC_DXE_CONFIG_REVISION 1 +#define SCS_SDCARD_MAX_DATA_GPIOS 4 +#define SCS_EMMC_MAX_DATA_GPIOS 8 +extern EFI_GUID gSdCardConfigGuid; +extern EFI_GUID gEmmcConfigGuid; +extern EFI_GUID gUfsConfigGuid; +extern EFI_GUID gEmmcDxeConfigGuid; + +#pragma pack (push,1) + +/** + This structre holds the DLL configuration + register values that will be programmed by RC + if EnableCustomDlls field is set to TRUE. Those + policies should be used by platform if default values + provided by RC are not sufficient to provide stable operation + at all supported spped modes. RC will blindly set the DLL values + as provided in this structre. + + For help with obtaining valid DLL values for your platform please + contact enabling support. +**/ +typedef struct { + UINT32 TxCmdDelayControl; // Offset 820h: Tx CMD Delay Control + UINT32 TxDataDelayControl1; // Offset 824h: Tx Data Delay Control 1 + UINT32 TxDataDelayControl2; // Offset 828h: Tx Data Delay Control 2 + UINT32 RxCmdDataDelayControl1; // Offset 82Ch: Rx CMD + Data Delay Cont= rol 1 + UINT32 RxCmdDataDelayControl2; // Offset 834h: Rx CMD + Data Delay Cont= rol 2 + UINT32 RxStrobeDelayControl; // Offset 830h: Rx Strobe Delay Control,= valid only for eMMC +} SCS_SD_DLL; + +/** + SD GPIO settings +**/ +typedef struct { + /** + GPIO signals pin muxing settings. If signal can be enable only on a si= ngle pin + then this parameter should be set to 0. Refer to GPIO_*_MUXING_SDCARD_= *x_* in GpioPins*.h + for supported settings on a given platform + **/ + UINT32 PinMux; + /** + GPIO Pads Internal Termination. + For more information please see Platform Design Guide. + Check GPIO_ELECTRICAL_CONFIG for reference + **/ + UINT32 PadTermination; +} MUX_GPIO_PARAM; + +typedef struct { + MUX_GPIO_PARAM PowerEnable; + MUX_GPIO_PARAM Cmd; + MUX_GPIO_PARAM Data[SCS_SDCARD_MAX_DATA_GPIOS]; + MUX_GPIO_PARAM Cdb; + MUX_GPIO_PARAM Clk; + MUX_GPIO_PARAM Wp; +} SCS_SDCARD_GPIO_CONFIG; + +typedef struct { + MUX_GPIO_PARAM Cmd; + MUX_GPIO_PARAM Data[SCS_EMMC_MAX_DATA_GPIOS]; + MUX_GPIO_PARAM Rclk; + MUX_GPIO_PARAM Clk; + MUX_GPIO_PARAM Resetb; +} SCS_EMMC_GPIO_CONFIG; + +typedef struct { + CONFIG_BLOCK_HEADER Header; + + UINT32 Enable : 1; ///< Enable/Disable SdCard 0: D= isabled, 1: Enabled + UINT32 PowerEnableActiveHigh : 1; ///< Determine SD_PWREN# polari= ty 0: Active low, 1: Active high + UINT32 UseCustomDlls : 1; ///< Use tuned DLL values from = policy 0: Use default DLL, 1: Use values from TunedDllValues field + UINT32 Reserved : 29; + SCS_SD_DLL CustomDllValues; ///< Structure containing custo= m DLL values for SD card + SCS_SDCARD_GPIO_CONFIG GpioConfig; +} SCS_SDCARD_CONFIG; + +typedef struct { + UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value + UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value + UINT32 Reserved : 18; +} SCS_EMMC_TUNED_DLL; + +typedef struct { + CONFIG_BLOCK_HEADER Header; + + UINT32 Enable : 1; ///< Enable/Disable eMMC 0: Disabled, = 1: Enabled + UINT32 Hs400Supported : 1; ///< Enable/Disable eMMC HS400 support= 0: Disabled, 1: Enabled + UINT32 UseCustomDlls : 1; ///< Use custom DLL values from policy= 0: Use default DLL, 1: Use values from TunedDllValues field + UINT32 Reserved : 29; + SCS_SD_DLL CustomDllValues; ///< Structure containing custom DLL v= alues for eMMC ///< Structure containing tuned DLL setti= ngs for eMMC + SCS_EMMC_GPIO_CONFIG GpioConfig; +} SCS_EMMC_CONFIG; + +typedef enum { + DriverStrength33Ohm =3D 0, + DriverStrength40Ohm, + DriverStrength50Ohm +} SCS_EMMC_DRIVER_STRENGTH; + +typedef struct { + UINT32 TuningSuccessful : 1; ///< Informs software tuning module abou= t previous software tuning status. + UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value r= eturned from software tuning module + UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value r= eturned from software tuning module + UINT32 Reserved : 17; +} SCS_EMMC_SOFTWARE_TUNING_RESULTS; + +typedef struct { + CONFIG_BLOCK_HEADER Header; + + UINT32 EnableSoftwareHs400Tuning : 1; ///< Enable/Di= sable software eMMC HS400 tuning: 0 - Disable, 1 - Enable + UINT32 DriverStrength : 2; ///< I/O drive= r strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm + UINT32 Reserved : 29; + EFI_LBA TuningLba; ///< Specifies= LBA which will be used during software tuning process. + SCS_EMMC_SOFTWARE_TUNING_RESULTS PreviousTuningResults; ///< Informes = software tuning module about previous software tuning results.} SCS_EMMC_DX= E_CONFIG; +} SCS_EMMC_DXE_CONFIG; + +typedef struct { + UINT32 Enable : 1; ///< Enable/Disable UFS controller 0: Disabled, <= b>1: Enabled + UINT32 Reserved : 31; +} SCS_UFS_CONTROLLER_CONFIG; + +#pragma pack (pop) + +#endif // _SCS_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo= /SerialIoConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/S= erialIo/SerialIoConfig.h new file mode 100644 index 0000000000..d76937cf59 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/Serial= IoConfig.h @@ -0,0 +1,32 @@ +/** @file + Serial IO policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SERIAL_IO_CONFIG_H_ +#define _SERIAL_IO_CONFIG_H_ + +#define SERIAL_IO_CONFIG_REVISION 1 +extern EFI_GUID gSerialIoConfigGuid; + +#include + +#pragma pack (push,1) + +/** + The SERIAL_IO_CONFIG block provides the configurations to set the Serial= IO controllers + + Revision 1: + - Inital version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; = ///< Config Block Header + SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS];= ///< SPI Configuration + SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS];= ///< I2C Configuration + SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS= ]; ///< UART Configuration +} SERIAL_IO_CONFIG; + +#pragma pack (pop) + +#endif // _SERIAL_IO_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig= .h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h new file mode 100644 index 0000000000..7ee4554b1d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h @@ -0,0 +1,152 @@ +/** @file + Si Config Block + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SI_CONFIG_H_ +#define _SI_CONFIG_H_ + +#define SI_CONFIG_REVISION 2 + +extern EFI_GUID gSiConfigGuid; + + +#pragma pack (push,1) + +/** + The Silicon Policy allows the platform code to publish a set of configur= ation + information that the RC drivers will use to configure the silicon hardwa= re. + + Revision 1: + - Initial version. + Revision 2: + - Added TraceHubMemBase +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header + // + // Platform specific common policies that used by several silicon compon= ents. + // + UINT8 CsmFlag; ///< CSM status flag. + /** + This is used to skip the SSID programming in silicon code. + When set to TRUE, silicon code will not do any SSID programming and pl= atform code + needs to handle that by itself properly. + 0: FALSE, 1: TRUE + **/ + UINT8 SkipSsidProgramming; + UINT8 RsvdBytes0[2]; + /** + When SkipSsidProgramming is FALSE, silicon code will use this as defau= lt value + to program the SVID for all internal devices. + 0: use silicon default SVID 0x8086 , Non-zero: use customized S= VID. + **/ + UINT16 CustomizedSvid; + /** + When SkipSsidProgramming is FALSE, silicon code will use this as defau= lt value + to program the Sid for all internal devices. + 0: use silicon default SSID 0x7270 , Non-zero: use customized S= SID. + **/ + UINT16 CustomizedSsid; + /** + SsidTablePtr contains the SVID_SID_INIT_ENTRY table. + This is valid when SkipSsidProgramming is FALSE; + It doesn't need to contain entries for all Intel internal devices. + It can only contains the SVID_SID_INIT_ENTRY entries for those Dev# Fu= nc# which needs + to be overridden. + In the enties, only Dev, Function, SubSystemVendorId, and SubSystemId = are required. + Default is NULL. + + E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF 0= :31:3 to CCCC:DDDD, + it can be done in platform like this: + STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] =3D {0}; + + VOID SiPolicyUpdate () { + UINT32 EntryCount =3D 0; + SiPolicy->SkipSsidProgramming =3D FALSE; + SiPolicy->SsidTablePtr =3D mSsidTablePtr; + + mSsidTablePtr[EntryCount].Address.Bits.Device =3D SpiDeviceNumber = (); + mSsidTablePtr[EntryCount].Address.Bits.Function =3D SpiFunctionNumbe= r (); + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId =3D 0xAAAA; + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId =3D 0xBBBB; + EntryCount ++; + mSsidTablePtr[EntryCount].Address.Bits.Device =3D HdaDevNumber (); + mSsidTablePtr[EntryCount].Address.Bits.Function =3D HdaFuncNumber ()= ; + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId =3D 0xCCCC; + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId =3D 0xDDDD; + EntryCount ++; + ASSERT (EntryCount < SI_MAX_DEVICE_COUNT); + SiPolicy->NumberOfSsidTableEntry =3D EntryCount; + } + **/ + UINT32 *SsidTablePtr; + /** + Number of valid enties in SsidTablePtr. + This is valid when SkipSsidProgramming is FALSE; + Default is 0. + **/ + UINT16 NumberOfSsidTableEntry; + UINT8 RsvdBytes1[2]; + /** + If Trace Hub is enabled and trace to memory is desired, Platform code = or BootLoader needs to allocate trace hub memory + as reserved, and save allocated memory base to TraceHubMemBase to ensu= re Trace Hub memory is configured properly. + To get total trace hub memory size please refer to TraceHubCalculateTo= talBufferSize () + + Noted: If EDKII memory service is used to allocate memory, it will req= uire double memory size to support size-aligned memory allocation, + so Platform code or FSP Wrapper code should ensure enough memory avail= able for size-aligned TraceHub memory allocation. + **/ + UINT32 TraceHubMemBase; // Offset 58 + /** + This is used to skip setting BIOS_DONE MSR during firmware update boot= mode. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, + skip setting BIOS_DONE MSR at EndofPei. + 0: FALSE, 1: TRUE + **/ + UINT8 SkipBiosDoneWhenFwUpdate; + UINT8 RsvdBytes2[3]; +} SI_CONFIG; + +#pragma pack (pop) + +#define DEFAULT_SSVID 0x8086 +#define DEFAULT_SSDID 0x7270 +#define SI_MAX_DEVICE_COUNT 70 + +/// +/// Subsystem Vendor ID / Subsystem ID +/// +typedef struct { + UINT16 SubSystemVendorId; + UINT16 SubSystemId; +} SVID_SID_VALUE; + +// +// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to= PciSegmentRead/Write functions. +// +typedef struct { + union { + struct { + UINT32 Register:12; + UINT32 Function:3; + UINT32 Device:5; + UINT32 Bus:8; + UINT32 Reserved1:4; + UINT32 Segment:16; + UINT32 Reserved2:16; + } Bits; + UINT64 SegBusDevFuncRegister; + } Address; + SVID_SID_VALUE SvidSidValue; + UINT32 Reserved; +} SVID_SID_INIT_ENTRY; + + +typedef struct { + UINT32 SkipBus; + UINT32 SkipDevice; + UINT32 SkipFunction; +} SVID_SID_SKIP_TABLE; + +#endif // _SI_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMem= Config.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemCo= nfig.h new file mode 100644 index 0000000000..4bf014e9ba --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.= h @@ -0,0 +1,67 @@ +/** @file + Si Config Block PreMem + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SI_PREMEM_CONFIG_H_ +#define _SI_PREMEM_CONFIG_H_ + +#define SI_PREMEM_CONFIG_REVISION 1 + +extern EFI_GUID gSiPreMemConfigGuid; + +typedef enum { + ProbeTypeDisabled =3D 0x00, + ProbeTypeDciOob =3D 0x02, + ProbeTypeUsb3Dbc =3D 0x03, + ProbeTypeXdp3 =3D 0x04, + ProbeTypeUsb2Dbc =3D 0x05, + ProbeType2WireDciOob =3D 0x06, + ProbeTypeManual =3D 0x07, + ProbeTypeMax +} PLATFORM_DEBUG_CONSENT_PROBE_TYPE; + +#pragma pack (push,1) +/** + The Silicon PreMem Policy allows the platform code to publish a set of c= onfiguration + information that the RC drivers will use to configure the silicon hardwa= re. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header + /** + Platform Debug Consent + As a master switch to enable platform debug capability and relevant se= ttings with specified probe type. + Manual: Do not use Platform Debug Consent to override other debug-rele= vant policies, but the user must set each debug option manually, aimed at a= dvanced users. + + PDC-dependent policies are listed: + DciPreMemConfig->DciEn + DciPreMemConfig->DciDbcMode + CpuTraceHubConfig->EnableMode + CpuTraceHubConfig->CpuTraceHubMemReg0Size + CpuTraceHubConfig->CpuTraceHubMemReg1Size + PchTraceHubPreMemConfig->EnableMode + PchTraceHubPreMemConfig->MemReg0Size + PchTraceHubPreMemConfig->MemReg1Size + + Note: DCI OOB (aka BSSB) uses CCA probe. + Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE + 0:Disabled; 2:DCI OOB; 3:USB3 DbC; 4:XDP3/MIPI60 5:USB2 DbC; 6:= 2-wire DCI OOB; 7:Manual + **/ + UINT32 PlatformDebugConsent : 4; + UINT32 RsvdBits : 28; + /** + This is used to skip override boot mode during firmware update boot mo= de. + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE, + skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory i= nit. + 0: FALSE, 1: TRUE + **/ + UINT8 SkipOverrideBootModeWhenFwUpdate; + UINT8 RsvdBytes[3]; +} SI_PREMEM_CONFIG; + +#pragma pack (pop) +#endif // _SI_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/Sm= busConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/S= mbusConfig.h new file mode 100644 index 0000000000..36f96a4f32 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConf= ig.h @@ -0,0 +1,50 @@ +/** @file + Smbus policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SMBUS_CONFIG_H_ +#define _SMBUS_CONFIG_H_ + +#define SMBUS_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gSmbusPreMemConfigGuid; + +#pragma pack (push,1) + +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128 + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capabl= e devices in the platform. +/// +typedef struct { + /** + Revision 1: Init version + **/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This member describes whether or not the SMBus controller of PCH shoul= d be enabled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, = 0: Disable; 1: Enable. + UINT32 DynamicPowerGating : 1; ///< (Test) Disable = or Enable Smbus dynamic power gating. + /// + /// (Test) SPD Write Disable, 0: leave SPD Write Disable bit; = 1: set SPD Write Disable bit. + /// For security recommendations, SPD write disable bit must be set. + /// + UINT32 SpdWriteDisable : 1; + UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBAL= ERT#). 0: Disabled, 1: Enabled. + UINT32 RsvdBits0 : 27; ///< Reserved bits + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space)= . Default is 0xEFA0. + UINT8 Rsvd0; ///< Reserved bytes + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the= RsvdSmbusAddressTable. + /** + Array of addresses reserved for non-ARP-capable SMBus devices. + **/ + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; +} PCH_SMBUS_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _SMBUS_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConf= ig.h new file mode 100644 index 0000000000..f3e52ff453 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h @@ -0,0 +1,43 @@ +/** @file + PCH SPI Flash Controller config block + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SPI_CONFIG_H_ +#define _SPI_CONFIG_H_ + +#define SPI_CONFIG_REVISION 1 +extern EFI_GUID gSpiConfigGuid; + +#pragma pack (push,1) + +/** + Basic configuration for option features of PCH SPI Flash controller +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Enable extended BIOS Direct Read Region feature + Enabling this will make all memory accesses in a decode range to be tr= anslated + to BIOS region reads from SPI flash + 0: Disabled, 1: Enabled + **/ + UINT32 ExtendedBiosDecodeRangeEnable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits + /** + Base address that will be used for Extended Decode Range. + This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0. + **/ + UINT32 ExtendedBiosDecodeRangeBase; + /** + Limit address that will be used for Extended Decode Range. + This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0. + **/ + UINT32 ExtendedBiosDecodeRangeLimit; +} SPI_CONFIG; + +#pragma pack (pop) + +#endif // _SPI_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/Tcs= sPeiConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/T= cssPeiConfig.h new file mode 100644 index 0000000000..53af4ccd45 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiCon= fig.h @@ -0,0 +1,145 @@ +/** @file + TCSS PEI policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _TCSS_PEI_CONFIG_H_ +#define _TCSS_PEI_CONFIG_H_ + +#include +#include +#include + +#define TCSS_PEI_CONFIG_REVISION 2 +extern EFI_GUID gTcssPeiConfigGuid; + +#pragma pack (push,1) + + +#define MAX_IOM_AUX_BIAS_COUNT 4 + +/// +/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin. +/// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC = port didn't have re-timer. +/// IOM needs know Pull-Up and Pull-Down pin for Bias control +/// +typedef struct { + UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM inde= cate the pull up pin from TypeC port. + UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM in= decate the pull down pin from TypeC port. +} IOM_AUX_ORI_PAD_CONFIG; + +/// +/// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS a= nd IOM-EC. +/// + +typedef struct { + UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual V= CCST value) + UINT32 UsbOverride; ///< IOM to override USB connection. + UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS + UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS +} IOM_INTERFACE_CONFIG; + +/// +/// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and = PMC +/// +typedef struct { + UINT8 PmcPdEnable; ///< PMC PD Solution Enable + UINT8 Rsvd[3]; +} PMC_INTERFACE_CONFIG; + +/// +/// The SA XDCI INT Pin and IRQ number +/// +typedef struct { + UINT8 IntPing; ///< Int Pin Number + UINT8 Irq; ///< Irq Number + UINT16 Rsvd; +} SA_XDCI_IRQ_INT_CONFIG; + +/// +/// The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS. +/// +typedef struct { + UINT8 AcsEnabled; ///< Indicate whether the AC= S is enabled. 0: Disable; 1: Enable. + UINT8 DpcEnabled; ///< Downstream Port Contain= ment. 0: Disable; 1: Enable + UINT8 RpDpcExtensionsEnabled; ///< RP Extensions for Downs= tream Port Containment. 0: Disable; 1: Enable + UINT8 LtrEnable; ///< Latency Tolerance Repor= ting Mechanism. 0: Disable; 1: Enable. + UINT8 PtmEnabled; ///< Enables PTM capability + + UINT8 Aspm; ///< The ASPM configuration = of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is + UINT8 SlotNumber; ///< Indicates the slot numb= er for the root port. Default is the value as root port index. + UINT8 SlotPowerLimitScale; ///< (Test) Specifies= scale used for slot power limit value. Leave as 0 to set to default. Defau= lt is zero. + UINT16 SlotPowerLimitValue; ///< (Test) Specifies= upper limit on power supplies by slot. Leave as 0 to set to default. Defau= lt is zero. + + UINT8 AdvancedErrorReporting; ///< Indicate whether the Ad= vanced Error Reporting is enabled. 0: Disable; 1: Enable. + UINT8 UnsupportedRequestReport; ///< Indicate whether the Un= supported Request Report is enabled. 0: Disable; 1: Enable. + UINT8 FatalErrorReport; ///< Indicate whether the Fa= tal Error Report is enabled. 0: Disable; 1: Enable. + UINT8 NoFatalErrorReport; ///< Indicate whether the No= Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT8 CorrectableErrorReport; ///< Indicate whether the Co= rrectable Error Report is enabled. 0: Disable; 1: Enable. + UINT8 SystemErrorOnFatalError; ///< Indicate whether the Sy= stem Error on Fatal Error is enabled. 0: Disable; 1: Enable. + UINT8 SystemErrorOnNonFatalError; ///< Indicate whether the Sy= stem Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. + UINT8 SystemErrorOnCorrectableError; ///< Indicate whether the Sy= stem Error on Correctable Error is enabled. 0: Disable; 1: Enable. + + UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Repor= ting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Repor= ting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance Repor= ting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance Repor= ting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance Repor= ting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance Repor= ting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance Repor= ting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance Repor= ting, Non-Snoop Latency Override Value. + UINT8 ForceLtrOverride; ///< 0: Disable; 1: E= nable. + UINT8 LtrConfigLock; ///< 0: Disable; 1: E= nable. +} TCSS_PCIE_PORT_POLICY; + +/// +/// TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS. +/// +typedef struct { + TCSS_PCIE_PORT_POLICY PciePortPolicy[MAX_ITBT_PCIE_PORT]; +} TCSS_PCIE_PEI_POLICY; + +/// +/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings = for TCSS. +/// +typedef struct { + UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation R= egister + UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation R= egister +} TCSS_IOM_ORI_OVERRIDE; + +/// +/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS. +/// +typedef struct { + IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< Th= e IOM_AUX_ORI_BIAS_CTRL port config setting. + TCSS_IOM_ORI_OVERRIDE IomOverrides; + IOM_INTERFACE_CONFIG IomInterface; ///< Co= nfig settings are BIOS <-> IOM interface. + PMC_INTERFACE_CONFIG PmcInterface; ///< Co= nfig settings for BIOS <-> PMC interface + UINT8 TcStateLimit; ///< Tc= ss C-State deep stage + UINT8 Usb3ComplModeEnable; + UINT8 Reserved[2]; ///< Re= served bytes for future use +} TCSS_IOM_PEI_CONFIG; + +/// +/// The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS. +/// +typedef struct { + SA_XDCI_IRQ_INT_CONFIG SaXdci; ///< System Agent Xdci Int Pin and I= rq setting + UINT32 Rsvd; ///< Reserved bytes for future use, = align to multiple 4 +} TCSS_MISC_PEI_CONFIG; + +/// +/// The TCSS_PEI_CONFIG block describes TCSS settings for SA. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + TCSS_PCIE_PEI_POLICY PciePolicy; ///< The PCIe Config + USB_CONFIG UsbConfig; ///< USB config is shared between PC= H and SA. + TCSS_IOM_PEI_CONFIG IomConfig; ///< The Iom Config + TCSS_MISC_PEI_CONFIG MiscConfig; ///< The MISC Config +} TCSS_PEI_CONFIG; + +#pragma pack (pop) + +#endif /* _TCSS_PEI_CONFIG_H_ */ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConf= ig.h new file mode 100644 index 0000000000..23c3750216 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h @@ -0,0 +1,73 @@ +/** @file + Touch Host Controller policy. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _THC_CONFIG_H_ +#define _THC_CONFIG_H_ + +#define THC_CONFIG_REVISION 1 +extern EFI_GUID gThcConfigGuid; + +#pragma pack (push,1) + +/** + Available Port Assignments + +**/ +typedef enum { + ThcAssignmentNone, ///< None of the avaialbe controllers assigned + ThcAssignmentThc0, ///< Port assigned to THC0 + ThcAssignmentThc1 ///< Port assigned to THC1 +} THC_PORT_ASSIGNMENT; + + +/** + Port Configuration structure required for each Port that THC might use. + +**/ +typedef struct { + UINT32 Assignment; ///< Sets THCx assignment see THC_PORT_ASSIGN= MENT + UINT32 InterruptPinMuxing; ///< Each GPIO PORTx/SPIx INTB Pin has differ= ent muxing options refer to GPIO_*_MUXING_THC_SPIx_* +} THC_PORT; + +/** + THC_CONFIG block provides the configurations forTouch Host Controllers + + Assignment field in each THC port controlls the THC behavior. + + Available scenarios: + 1: Single Port 0 used by THC0 + - THC0 Enabled + - Port0 assigned to THC0 + - Port1 unassigned + - THC1 will be automatically Disabled. + 2: Both ports used by THC0 + - THC0 Enabled + - Port0 assigned to THC0 + - Port1 assigned to THC0 + - THC1 will be automatically Disabled. + 3: Port 0 used by THC0 and Port 1 used by THC1 + - THC0 Enabled + - Port0 assigned to THC0 + - THC1 Enabled + - Port1 assigned to THC1. +4: Both Ports unassigned. + Both THC Controllers will be disabled in that case. + + @note + Invalid scenario that will cause ASSERT. + 1. Same port Number assigned to THC0 or THC1. + 2. Two Ports assigned to THC1. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + THC_PORT ThcPort[2]; ///< Port Configuration +} THC_CONFIG; + +#pragma pack (pop) + +#endif // _THC_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/= ThermalConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/The= rmal/ThermalConfig.h new file mode 100644 index 0000000000..a952f74238 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/Thermal= Config.h @@ -0,0 +1,153 @@ +/** @file + Thermal policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _THERMAL_CONFIG_H_ +#define _THERMAL_CONFIG_H_ + +#define THERMAL_CONFIG_REVISION 1 +extern EFI_GUID gThermalConfigGuid; + +#pragma pack (push,1) + +/** + This structure lists PCH supported throttling register setting for custi= mization. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 T0Level : 9; ///< Custimized T0Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 T1Level : 9; ///< Custimized T1Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 T2Level : 9; ///< Custimized T2Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 TTEnable : 1; ///< Enable the thermal throttle f= unction. If SuggestedSetting is used, this settings is ignored. + /** + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13= will force at least T2 state. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTState13Enable : 1; + /** + When set to 1, this entire register (TL) is locked and remains locked = until the next platform reset. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTLock : 1; + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values. + /** + ULT processors support thermal management and cross thermal throttling= between the processor package + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit f= ields to update the PCH + thermal status to the processor which is factored into the processor t= hrottling. + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled. + **/ + UINT32 PchCrossThrottling : 1; + UINT32 Rsvd0; ///< Reserved bytes +} THERMAL_THROTTLE_LEVELS; + +// +// Supported Thermal Sensor Target Width +// +typedef enum { + DmiThermSensWidthX1 =3D 0, + DmiThermSensWidthX2 =3D 1, + DmiThermSensWidthX4 =3D 2, + DmiThermSensWidthX8 =3D 3, + DmiThermSensWidthX16 =3D 4 +} DMI_THERMAL_SENSOR_TARGET_WIDTH; + +/** + This structure allows to customize DMI HW Autonomous Width Control for T= hermal and Mechanical spec design. + When the SuggestedSetting is enabled, the customized values are ignored. + Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values +**/ +typedef struct { + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous= Width Enable + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Width= (DmiThermSensWidthx8) + UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Width= (DmiThermSensWidthx4) + UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Width= (DmiThermSensWidthx2) + UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Width= (DmiThermSensWidthx1) + UINT32 RsvdBits1 : 12; ///< Reserved bits +} DMI_HW_WIDTH_CONTROL; + +/** + This structure configures PCH memory throttling thermal sensor GPIO PIN = settings +**/ +typedef struct { + /** + GPIO PM_SYNC enable, 0:Diabled, 1:Enabled + When enabled, RC will overrides the selected GPIO native mode. + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 + For CNL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, C= PU_GP_3 is GPP_B4. + **/ + UINT32 PmsyncEnable : 1; + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 st= ate, 0:Disabled, 1:Enabled + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection= , 0: default, 1: secondary + UINT32 RsvdBits0 : 29; +} TS_GPIO_PIN_SETTING; + +enum PCH_PMSYNC_GPIO_X_SELECTION { + TsGpioC, + TsGpioD, + MaxTsGpioPin +}; + +/** + This structure supports an external memory thermal sensor (TS-on-DIMM or= TS-on-Board). +**/ +typedef struct { + /** + This will enable PCH memory throttling. + While this policy is enabled, must also enable EnableExtts in SA policy= . + 0: Disable; 1: Enable + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; + /** + GPIO_C and GPIO_D selection for memory throttling. + It's strongly recommended to choose GPIO_C and GPIO_D for memory throt= tling feature, + and route EXTTS# accordingly. + **/ + TS_GPIO_PIN_SETTING TsGpioPinSetting[2]; +} PCH_MEMORY_THROTTLING; + +/** + The THERMAL_CONFIG block describes the expected configuration of the The= rmal IP block. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertion = when temperature is higher than PchHotLevel. 0: Disabled, 1: Enabled. + UINT32 RsvdBits0 : 31; + /** + This field decides the settings of Thermal throttling. When the Sugges= ted Setting + is enabled, PCH RC will use the suggested representative values. + **/ + THERMAL_THROTTLE_LEVELS TTLevels; + /** + This field decides the settings of DMI throttling. When the Suggested = Setting + is enabled, PCH RC will use the suggested representative values. + **/ + DMI_HW_WIDTH_CONTROL DmiHaAWC; + /** + Memory Thermal Management settings + **/ + PCH_MEMORY_THROTTLING MemoryThrottling; + /** + The recommendation is the same as Cat Trip point. + This field decides the temperature, default is 120. + Temperature value used for PCHHOT# pin assertion based on 2s complemen= t format + - 0x001 positive 1'C + - 0x000 0'C + - 0x1FF negative 1'C + - 0x1D8 negative 40'C + - and so on + **/ + UINT16 PchHotLevel; + UINT8 Rsvd0[6]; + + +} THERMAL_CONFIG; + +#pragma pack (pop) + +#endif // _THERMAL_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub= /TraceHubConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/T= raceHub/TraceHubConfig.h new file mode 100644 index 0000000000..9c315fb4a4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceH= ubConfig.h @@ -0,0 +1,101 @@ +/** @file + Configurations for CPU and PCH trace hub + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _TRACE_HUB_CONFIG_H_ +#define _TRACE_HUB_CONFIG_H_ + +#include + +#define CPU_TRACEHUB_PREMEM_CONFIG_REVISION 1 +#define PCH_TRACEHUB_PREMEM_CONFIG_REVISION 1 + +extern EFI_GUID gPchTraceHubPreMemConfigGuid; +extern EFI_GUID gCpuTraceHubPreMemConfigGuid; + +typedef enum { + CpuTraceHub, + PchTraceHub +} TRACE_HUB_DEVICE; +/// +/// The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation +/// +typedef enum { + TraceHubModeDisabled =3D 0, + TraceHubModeTargetDebugger =3D 1, + TraceHubModeHostDebugger =3D 2, + TraceHubModeMax +} TRACE_HUB_ENABLE_MODE; + +/// +/// The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size +/// +typedef enum { + TraceBufferNone, + TraceBuffer1M, + TraceBuffer8M, + TraceBuffer64M, + TraceBuffer128M, + TraceBuffer256M, + TraceBuffer512M, + TraceBufferMax +} TRACE_BUFFER_SIZE; + +#pragma pack (push,1) +/// +/// TRACE_HUB_CONFIG block describes TraceHub settings +/// +typedef struct { + /** + Trace hub mode. Default is disabled. + Target Debugger mode refers to debug tool running on target device itsel= f and it works as a conventional PCI device; + Host Debugger mode refers to SUT debugged via probe on host, configured = as ACPI device with PCI configuration sapce hidden. + 0 =3D Disable; 1 =3D Target Debugger mode; 2 =3D Host Debugger mo= de + Refer to TRACE_HUB_ENABLE_MODE + **/ + UINT8 EnableMode; + /** + Trace hub memory buffer region size policy. + The avaliable memory size options are: 0:0MB (none), 1:1MB, 2:8MB= , 3:64MB, 4:128MB, 5:256MB, 6:512MB. + Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt is = enabled, the total size limits to 256 MB. + Refer to TRACE_BUFFER_SIZE + **/ + UINT8 MemReg0Size; + UINT8 MemReg1Size; + /** + AET Trace. AET base address can be set to FW Base either from CPU trace = hub or PCH one. + AetEnabled must be exclusive, if AetEnabled =3D 1 for CPU trace hub, mus= t AetEnabled =3D 0 for PCH one. + The default is set to PCH. + CPU Trace Hub + 0 =3D Disabled; 1 =3D Enabled + PCH Trace Hub + 0 =3D Disabled; 1 =3D Enabled + **/ + UINT8 AetEnabled; +} TRACE_HUB_CONFIG; + +/** + CPU Trace Hub PreMem Configuration + Contains Trace Hub settings for CPU side tracing + Revision 1: - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config +} CPU_TRACE_HUB_PREMEM_CONFIG; + +/** + PCH Trace Hub PreMem Configuration + Contains Trace Hub settings for PCH side tracing + Revision 1: - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config +} PCH_TRACE_HUB_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2= PhyConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb= 2PhyConfig.h new file mode 100644 index 0000000000..99063103c3 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConf= ig.h @@ -0,0 +1,81 @@ +/** @file + USB2 PHY configuration policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _USB2_PHY_CONFIG_H_ +#define _USB2_PHY_CONFIG_H_ + +#include + +#define USB2_PHY_CONFIG_REVISION 1 +extern EFI_GUID gUsb2PhyConfigGuid; + +#pragma pack (push,1) + +/** + This structure configures per USB2 AFE settings. + It allows to setup the port electrical parameters. +**/ +typedef struct { +/** Per Port HS Preemphasis Bias (PERPORTPETXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Petxiset; +/** Per Port HS Transmitter Bias (PERPORTTXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Txiset; +/** + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) + 00b - Emphasis OFF + 01b - De-emphasis ON + 10b - Pre-emphasis ON + 11b - Pre-emphasis & De-emphasis ON +**/ + UINT8 Predeemp; +/** + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) + 1b - half-bit pre-emphasis + 0b - full-bit pre-emphasis +**/ + UINT8 Pehalfbit; +} USB2_PHY_PARAMETERS; + +/** + This structure holds info on how to tune electrical parameters of USB2 p= orts based on board layout + + Revision 1: + - Initial version. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er + /** + This structure configures per USB2 port physical settings. + It allows to setup the port location and port length, and configures t= he port strength accordingly. + Changing this policy values from default ones may require disabling US= B2 PHY Sus Well Power Gating + through Usb2PhySusPgEnable on PCH-LP + **/ + USB2_PHY_PARAMETERS Port[MAX_USB2_PORTS]; +} USB2_PHY_CONFIG; + +#pragma pack (pop) + +#endif // _USB2_PHY_CONFIG_H_ + diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3= HsioConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Us= b3HsioConfig.h new file mode 100644 index 0000000000..da816b1378 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioCon= fig.h @@ -0,0 +1,138 @@ +/** @file + USB3 Mod PHY configuration policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USB3_HSIO_CONFIG_H_ +#define _USB3_HSIO_CONFIG_H_ + +#include + +#define USB3_HSIO_CONFIG_REVISION 2 +extern EFI_GUID gUsb3HsioConfigGuid; + +#pragma pack (push,1) + +/** + This structure describes USB3 Port N configuration parameters +**/ +typedef struct { + /** + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) + HSIO_TX_DWORD8[21:16] + Default =3D 00h + **/ + UINT8 HsioTxDownscaleAmp; + /** + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2dee= mph3p5) + HSIO_TX_DWORD5[21:16] + Default =3D 29h (approximately -3.5dB De-Emphasis) + **/ + UINT8 HsioTxDeEmph; + /** + Signed Magnatude number added to the CTLE code.(ctle_adapt_offset_cfg_= 4_0) + HSIO_RX_DWORD25 [20:16] + Ex: -1 -- 1_0001. +1: 0_0001 + Default =3D 0h + **/ + UINT8 HsioCtrlAdaptOffsetCfg; + /** + LFPS filter select for n (filter_sel_n_2_0) + HSIO_RX_DWORD51 [29:27] + 0h:1.6ns + 1h:2.4ns + 2h:3.2ns + 3h:4.0ns + 4h:4.8ns + 5h:5.6ns + 6h:6.4ns + Default =3D 0h + **/ + UINT8 HsioFilterSelN; + /** + LFPS filter select for p (filter_sel_p_2_0) + HSIO_RX_DWORD51 [26:24] + 0h:1.6ns + 1h:2.4ns + 2h:3.2ns + 3h:4.0ns + 4h:4.8ns + 5h:5.6ns + 6h:6.4ns + Default =3D 0h + **/ + UINT8 HsioFilterSelP; + /** + Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0) + HSIO_RX_DWORD51 [2:0] + 000 Prohibited + 001 45K + 010 Prohibited + 011 31K + 100 36K + 101 36K + 110 36K + 111 36K + Default =3D 3h + **/ + UINT8 HsioOlfpsCfgPullUpDwnRes; + + UINT8 HsioTxDeEmphEnable; ///< Enable the write to USB 3.0 = TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable. + UINT8 HsioTxDownscaleAmpEnable; ///< Enable the write to USB 3.0 = TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable. + UINT8 HsioCtrlAdaptOffsetCfgEnable; ///< Enable the write to Signed M= agnatude number added to the CTLE code, 0: Disable; 1: Enable. + UINT8 HsioFilterSelNEnable; ///< Enable the write to LFPS fil= ter select for n, 0: Disable; 1: Enable. + UINT8 HsioFilterSelPEnable; ///< Enable the write to LFPS fil= ter select for p, 0: Disable; 1: Enable. + UINT8 HsioOlfpsCfgPullUpDwnResEnable; ///< Enable the write to olfpscfg= pullupdwnres, 0: Disable; 1: Enable. + /** + USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqT= ranScale) + HSIO_TX_DWORD9[6:0] + Default =3D 4Ch + **/ + UINT8 HsioTxRate3UniqTran; + /** + USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTr= anScale) + HSIO_TX_DWORD9[14:8] + Default =3D 4Ch + **/ + UINT8 HsioTxRate2UniqTran; + /** + USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqT= ranScale) + HSIO_TX_DWORD9[22:16] + Default =3D 4Ch + **/ + UINT8 HsioTxRate1UniqTran; + /** + USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqT= ranScale) + HSIO_TX_DWORD9[30:24] + Default =3D 4Ch + **/ + UINT8 HsioTxRate0UniqTran; + + UINT8 HsioTxRate3UniqTranEnable; ///< Enable the write to USB 3.0 TX Un= ique Transition Bit Mode for rate 3, 0: Disable; 1: Enable. + UINT8 HsioTxRate2UniqTranEnable; ///< Enable the write to USB 3.0 TX Un= ique Transition Bit Mode for rate 2, 0: Disable; 1: Enable. + UINT8 HsioTxRate1UniqTranEnable; ///< Enable the write to USB 3.0 TX Un= ique Transition Bit Mode for rate 1, 0: Disable; 1: Enable. + UINT8 HsioTxRate0UniqTranEnable; ///< Enable the write to USB 3.0 TX Un= ique Transition Bit Mode for rate 0, 0: Disable; 1: Enable. +} HSIO_PARAMETERS; + +/** + Structure for holding USB3 tuning parameters + + Revision 1: + - Initial version. + Revision 2: + - USB 3.0 TX Output Unique Transition Bit Scale policies added +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er + /** + These members describe whether the USB3 Port N of PCH is enabled by pl= atform modules. + **/ + HSIO_PARAMETERS Port[MAX_USB3_PORTS]; +} USB3_HSIO_CONFIG; + +#pragma pack (pop) + +#endif // _USB3_HSIO_CONFIG_H_ + diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConf= ig.h new file mode 100644 index 0000000000..a1c7f0bb04 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h @@ -0,0 +1,149 @@ +/** @file + Common USB policy shared between PCH and CPU + Contains general features settings for xHCI and xDCI + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _USB_CONFIG_H_ +#define _USB_CONFIG_H_ + +#define USB_CONFIG_REVISION 2 +extern EFI_GUID gUsbConfigGuid; + +#define MAX_USB2_PORTS 16 +#define MAX_USB3_PORTS 10 + +#pragma pack (push,1) + +typedef UINT8 USB_OVERCURRENT_PIN; +#define USB_OC_SKIP 0xFF +#define USB_OC_MAX_PINS 16 ///< Total OC pins number (both p= hysical and virtual) + +/** + This structure configures per USB2.0 port settings like enabling and ove= rcurrent protection +**/ +typedef struct { + /** + These members describe the specific over current pin number of USB 2.0= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same OC pin. + **/ + UINT32 OverCurrentPin : 8; + UINT32 Enable : 1; ///< 0: Disable; 1: Enab= le. + UINT32 PortResetMessageEnable : 1; ///< 0: Disable USB2 Port R= eset Message; 1: Enable USB2 Port Reset Message + UINT32 RsvdBits0 : 22; ///< Reserved bits +} USB2_PORT_CONFIG; + +/** + This structure configures per USB3.x port settings like enabling and ove= rcurrent protection +**/ +typedef struct { + /** + These members describe the specific over current pin number of USB 3.x= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same OC pin. + **/ + UINT32 OverCurrentPin : 8; + UINT32 Enable : 1; ///< 0: Disable; 1: Enable= . + UINT32 RsvdBits0 : 23; ///< Reserved bits +} USB3_PORT_CONFIG; + +/** + The XDCI_CONFIG block describes the configurations + of the xDCI Usb Device controller. +**/ +typedef struct { + /** + This member describes whether or not the xDCI controller should be ena= bled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} XDCI_CONFIG; + + +/** + This member describes the expected configuration of the USB controller, + Platform modules may need to refer Setup options, schematic, BIOS specif= ication to update this field. + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated = by referring the schematic. + + Revision 1: - Initial version. + Revision 2: - Add USB3LinkSpeed +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er + /** + This policy option when set will make BIOS program Port Disable Overri= de register during PEI phase. + When disabled BIOS will not program the PDO during PEI phase and leave= PDO register unlocked for later programming. + If this is disabled, platform code MUST set it before booting into OS. + 1: Enable + 0: Disable + **/ + UINT32 PdoProgramming : 1; + /** + This option allows for control whether USB should program the Overcurr= ent Pins mapping into xHCI. + Disabling this feature will disable overcurrent detection functionalit= y. + Overcurrent Pin mapping data is contained in respective port structure= s (i.e. USB30_PORT_CONFIG) in OverCurrentPin field. + By default this Overcurrent functionality should be enabled and disabl= ed only for OBS debug usage. + 1: Will program USB OC pin mapping in respective xHCI controller re= gisters + 0: Will clear OC pin mapping allow for OBS usage of OC pins + **/ + UINT32 OverCurrentEnable : 1; + /** + (Test) + If this policy option is enabled then BIOS will program OCCFDONE bit i= n xHCI meaning that OC mapping data will be + consumed by xHCI and OC mapping registers will be locked. OverCurrent = mapping data is taken from respective port data + structure from OverCurrentPin field. + If EnableOverCurrent policy is enabled this also should be enabled, ot= herwise xHCI won't consume OC mapping data. + 1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping d= ata + 0: Do not program OCCFDONE bit making it possible to use OBS debug on = OC pins. + **/ + UINT32 XhciOcLock : 1; + /** + Enabling this feature will allow for overriding LTR values for xHCI co= ntroller. + Values used for programming will be taken from this config block and B= IOS will disregard recommended ones. + 0: disable - do not override recommended LTR values + 1: enable - override recommended LTR values + **/ + UINT32 LtrOverrideEnable : 1; + /** + This setting enable LBPM GEN1 speed + 0: GEN2; + 1: GEN1; + **/ + UINT32 USB3LinkSpeed : 1; + UINT32 RsvdBits0 : 27; ///< Rese= rved bits + /** + High Idle Time Control override value + This setting is used only if LtrOverrideEnable is enabled + **/ + UINT32 LtrHighIdleTimeOverride; + /** + Medium Idle Time Control override value + This setting is used only if LtrOverrideEnable is enabled + **/ + UINT32 LtrMediumIdleTimeOverride; + /** + Low Idle Time Control override value + This setting is used only if LtrOverrideEnable is enabled + **/ + UINT32 LtrLowIdleTimeOverride; + /** + These members describe whether the USB2 Port N of PCH is enabled by pl= atform modules. + **/ + USB2_PORT_CONFIG PortUsb20[MAX_USB2_PORTS]; + /** + These members describe whether the USB3 Port N of PCH is enabled by pl= atform modules. + **/ + USB3_PORT_CONFIG PortUsb30[MAX_USB3_PORTS]; + /** + This member describes whether or not the xDCI controller should be ena= bled. + **/ + XDCI_CONFIG XdciConfig; + +} USB_CONFIG; + +#pragma pack (pop) + +#endif // _USB_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageR= egulator/CpuPowerMgmtVrConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include= /ConfigBlock/VoltageRegulator/CpuPowerMgmtVrConfig.h new file mode 100644 index 0000000000..8b01ecd262 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulato= r/CpuPowerMgmtVrConfig.h @@ -0,0 +1,114 @@ +/** @file + CPU Power Management VR Config Block. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _CPU_POWER_MGMT_VR_CONFIG_H_ +#define _CPU_POWER_MGMT_VR_CONFIG_H_ + +#define CPU_POWER_MGMT_VR_CONFIG_REVISION 7 + +extern EFI_GUID gCpuPowerMgmtVrConfigGuid; + +#pragma pack (push,1) + +/// +/// Defines the maximum number of VR domains supported. +/// @warning: Changing this define would cause DWORD alignment issues in p= olicy structures. +/// +#define MAX_NUM_VRS 5 + +/** + CPU Power Management VR Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Updated Acoustic Noise Mitigation. + Revision 3: + - Deprecate PsysOffset and added PsysOffset1 for Psys Offset Correction + Revision 4: + - Deprecate TdcTimeWindow and added TdcTimeWindow1 for TDC Time + Added Irms support. + Revision 5: + - Add RfiMitigation. + Revision 6: + - Added an option to Enable/Disable FIVR Spread Spectrum + Revision 7: + - Add Dynamic Periodicity Alteration (DPA) tuning feature +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 AcousticNoiseMitigation : 1; ///< Enable or Disable A= coustic Noise Mitigation feature. 0: Disabled; 1: Enabled + /** + VR specific mailbox commands. + 00b - no VR specific command sent. + 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be se= nt. + 10b - VR specific command sent for PS4 exit issue. + 11b - Reserved. + **/ + UINT32 SendVrMbxCmd : 2; + UINT32 EnableMinVoltageOverride : 1; ///< Enable or disable M= inimum Voltage override for minimum voltage runtime and minimum voltage C8.= 0: Disabled 1: Enabled. + UINT32 RfiMitigation : 1; ///< Enable or Disable R= FI Mitigation. 0: Disable - DCM is the IO_N default; 1: Enable - Ena= ble IO_N DCM/CCM switching as RFI mitigation. + UINT32 RsvdBits : 27; ///< Reserved for future= use. + UINT8 PsysSlope; ///< PCODE MMIO Mailbox:= Platform Psys slope correction. 0: Auto Specified in 1/100 incremen= t values. Range is 0-200. 125 =3D 1.25. + UINT8 PsysOffset; ///< PCODE MMIO Mailbox:= Platform Psys offset correction. 0: Auto Units 1/4, Range 0-255. Va= lue of 100 =3D 100/4 =3D 25 offset. Deprecated + UINT8 FivrSpreadSpectrum; ///< Set the Spread Spec= trum Range. 1.5%, Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each Ra= nge is translated to internally encoded values. 0.5% =3D 0, 1% =3D 3, 1.5% = =3D 8, 2% =3D 18, 3% =3D 28, 4% =3D 34, 5% =3D 39, 6% =3D 44. + UINT8 RsvdBytes0; + /** + PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100= KHz. + 0: Auto + Range varies based on XTAL clock: + - 0-1918 (Up to 191.8HMz) for 24MHz clock. + - 0-1535 (Up to 153.5MHz) for 19MHz clock. + **/ + UINT16 FivrRfiFrequency; + UINT8 RsvdBytes1[2]; + /** @name VR Settings + The VR related settings are sorted in an array where each index maps to = the VR domain as defined below: + - 0 =3D System Agent VR + - 1 =3D IA Core VR + - 2 =3D Ring Vr + - 3 =3D GT VR + - 4 =3D FIVR VR + + The VR settings for a given domain must be populated in the appropriate = index. + **/ + ///@{ + UINT16 TdcCurrentLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Thermal Design Current current limit. Specified in 1/8A units. Range is 0-= 4095. 1000 =3D 125A. 0: 0 Amps + UINT16 AcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= AcLoadline in 1/100 mOhms (ie. 1250 =3D 12.50 mOhm); Range is 0-6249. I= ntel Recommended Defaults vary by domain and SKU. + UINT16 DcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= DcLoadline in 1/100 mOhms (ie. 1250 =3D 12.50 mOhm); Range is 0-6249.In= tel Recommended Defaults vary by domain and SKU. + UINT16 Psi1Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. + UINT16 Psi2Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. + UINT16 Psi3Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. + INT16 ImonOffset[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Imon offset correction. Value is a 2's complement signed integer. Units 1/= 1000, Range 0-63999. For an offset =3D 12.580, use 12580. 0: Auto + UINT16 IccMax[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= VR Icc Max limit. 0-255A in 1/4 A units. 400 =3D 100A. Default: 0 - Aut= o, no override + UINT16 VrVoltageLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= VR Voltage Limit. Range is 0-7999mV. + UINT16 ImonSlope[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Imon slope correction. Specified in 1/100 increment values. Range is 0-200= . 125 =3D 1.25. 0: Auto + UINT8 Psi3Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 3 enable/disable; 0: Disable; 1: Enable. + UINT8 Psi4Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 4 enable/disable; 0: Disable; 1: Enable. + UINT8 VrConfigEnable[MAX_NUM_VRS]; ///< Enable/Disable BIOS= configuration of VR; 0: Disable; 1: Enable. + UINT8 TdcEnable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Thermal Design Current enable/disable; 0: Disable; 1: Enable + UINT8 TdcTimeWindow[MAX_NUM_VRS]; ///< @deprecated. PCODE = MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.= 1ms default + UINT8 TdcLock[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Thermal Design Current Lock; 0: Disable; 1: Enable. + UINT8 FastPkgCRampDisable[MAX_NUM_VRS]; ///< Disable Fast Slew R= ate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on Aco= ustic Noise Mitigation feature enabled. 0: False; 1: True + UINT8 SlowSlewRate[MAX_NUM_VRS]; ///< Slew Rate configura= tion for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR domain based on= Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2:= Fast/8; 3: Fast/16 + ///@} + UINT16 MinVoltageRuntime; ///< PCODE MMIO Mailbox:= Minimum voltage for runtime. Valid if EnableMinVoltageOverride =3D 1 .Rang= e 0 to 1999mV. 0: 0mV + UINT16 MinVoltageC8; ///< PCODE MMIO Mailbox:= Minimum voltage for C8. Valid if EnableMinVoltageOverride =3D 1. Range 0 t= o 1999mV. 0: 0mV + UINT16 PsysOffset1; ///< PCODE MMIO Mailbox:= Platform Psys offset correction. 0: Auto Units 1/1000, Range 0-6399= 9. For an offset of 25.348, enter 25348. + UINT8 RsvdBytes2[2]; + UINT32 TdcTimeWindow1[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Thermal Design Current time window. Defined in milli seconds. 1ms defau= lt + UINT8 Irms[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Current root mean square. 0: Disable; 1: Enable. + UINT8 FivrSpectrumEnable; ///< Enable or Disable F= IVR Spread Spectrum 0: Disable; 1: Enable. + UINT8 Rsvd1[2]; + UINT8 PreWake; ///< PCODE MMIO Mailbox:= Acoustic Noise Mitigation Range. This can be programmed only if AcousticNo= iseMitigation is enabled.Default Value =3D 0 micro ticks Defines the= max pre-wake randomization time in micro ticks. Range is 0-255. + UINT8 RampUp; ///< PCODE MMIO Mailbox:= Acoustic Noise Mitigation Range. This can be programmed only if AcousticNo= iseMitigation is enabled.Default Value =3D 0 micro ticks Defines the= max ramp up randomization time in micro ticks. Range is 0-255. + UINT8 RampDown; ///< PCODE MMIO Mailbox:= Acoustic Noise Mitigation Range. This can be programmed only if AcousticNo= iseMitigation is enabled.Default Value =3D 0 micro ticks Defines the= max ramp down randomization time in micro ticks. Range is 0-255. + UINT8 Rsvd2[1]; +} CPU_POWER_MGMT_VR_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_POWER_MGMT_VR_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConf= ig.h new file mode 100644 index 0000000000..74ca983a5d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h @@ -0,0 +1,64 @@ +/** @file + VT-d policy definitions. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _VTD_CONFIG_H_ +#define _VTD_CONFIG_H_ + +#include +#pragma pack(push, 1) + +#define VTD_CONFIG_REVISION 1 +#define VTD_DXE_CONFIG_REVISION 2 + +/** + The data elements should be initialized by a Platform Module. + The data structure is for VT-d driver initialization\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Confi= g Block Header + /** + Offset 28: + VT-D Support can be verified by reading CAP ID register as expalined i= n BIOS Spec. + This policy is for debug purpose only. + If VT-D is not supported, all other policies in this config block will= be ignored. + 0 =3D To use Vt-d; + 1 =3D Avoids programming Vtd bars, Vtd overrides and DMAR table. + **/ + UINT8 VtdDisable; + UINT8 X2ApicOptOut; ///< Offset 29 :This field is used to = enable the X2APIC_OPT_OUT bit in the DMAR table. 1=3DEnable/Set and 0=3D= Disable/Clear + UINT8 DmaControlGuarantee; ///< Offset 30 :This field is used to = enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. 1=3DEnable/Set and = 0=3DDisable/Clear + UINT8 VtdIgdEnable; ///< Offset 31 :This field is used to = enable the VtdIgdEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear + UINT8 VtdIpuEnable; ///< Offset 32 :This field is used to = enable the VtdIpuEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear + UINT8 VtdIopEnable; ///< Offset 33 :This field is used to = enable the VtdIopEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear + UINT8 VtdItbtEnable; ///< Offset 34 :This field is used to = enable the VtdItbtEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear + UINT8 PreBootDmaMask; ///< Offset 35 :Convey PcdVTdPolicyPro= pertyMask value from EDK2 IntelSiliconPkg + /** + Offset 36: + This field is used to describe the base addresses for VT-d function:\n + VTD BAR for Gfx if IGfx is supported : BaseAddress[0]=3D0xFED90000,= \n + VTD BAR for IPU if IPU is supporrted : BaseAddress[1]=3D0xFED92000,\n + VTD BAR for other DMA Agents (except Igfx and IPU) : BaseAddress[2]=3D= 0xFED91000,\n + VTD BAR for iTBT if iTBT is supported : BaseAddress[3]=3D0xFED84000, B= aseAddress[4]=3D0xFED85000, BaseAddress[5]=3D0xFED86000,BaseAddress[6]=3D0x= FED87000 + **/ + UINT32 BaseAddress[VTD_ENGINE_NUMBER]; + UINT32 DmaBufferSize; ///< Offset 64 :Protect Memory Region (= PMR) DMA buffer size + + +} VTD_CONFIG; + +/** + The data structure is for VT-d driver initialization in DXE\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config= Block Header +} VTD_DXE_CONFIG; +#pragma pack(pop) + +#endif // _VTD_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/Watc= hDogConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/Wa= tchDogConfig.h new file mode 100644 index 0000000000..8766762580 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogCon= fig.h @@ -0,0 +1,31 @@ +/** @file + WatchDog policy + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _WATCH_DOG_CONFIG_H_ +#define _WATCH_DOG_CONFIG_H_ + +#define WATCH_DOG_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gWatchDogPreMemConfigGuid; + +#pragma pack (push,1) + +/** + This policy clears status bits and disable watchdog, then lock the + WDT registers. + while WDT is designed to be disabled and locked by Policy, + bios should not enable WDT by WDT PPI. In such case, bios shows the + warning message but not disable and lock WDT register to make sure + WDT event trigger correctly. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 DisableAndLock : 1; ///< (Test) Set 1 to clear = WDT status, then disable and lock WDT registers. 0: Disable; 1: Enab= le. + UINT32 RsvdBits : 31; +} PCH_WDT_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _WATCH_DOG_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/Ti= gerlakeSiliconPkg/SiPkg.dec new file mode 100644 index 0000000000..0c0f2db104 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec @@ -0,0 +1,1207 @@ +## @file +# Component description file for the Silicon Reference Code. +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] +DEC_SPECIFICATION =3D 0x00010017 +PACKAGE_NAME =3D SiPkg +PACKAGE_VERSION =3D 0.1 +PACKAGE_GUID =3D F245E276-44A0-46b3-AEB5-9898BBCF008D + +[Includes.Common.Private] + +# +# TigerLake Fru +# +Fru/TglCpu/IncludePrivate +Fru/TglPch/IncludePrivate + +## +# IpBlock IncludePrivate +# +IpBlock/Psf/IncludePrivate +IpBlock/Pmc/IncludePrivate +IpBlock/Smbus/IncludePrivate +IpBlock/Graphics/IncludePrivate +IpBlock/CpuPcieRp/IncludePrivate +IpBlock/Hda/IncludePrivate +IpBlock/PchDmi/IncludePrivate +IpBlock/P2sb/IncludePrivate +IpBlock/Spi/IncludePrivate +IpBlock/Gpio/IncludePrivate +IpBlock/Cnvi/IncludePrivate +IpBlock/Gbe/IncludePrivate +IpBlock/PcieRp/IncludePrivate +IpBlock/Vtd/IncludePrivate +IpBlock/HostBridge/IncludePrivate +IpBlock/SerialIo/IncludePrivate + +SystemAgent/IncludePrivate + +Pch/IncludePrivate + +[Includes] +# +# TigerLake +# +Fru/TglCpu/Include +Fru/TglPch/Include + +# CPU PCIe +IpBlock/CpuPcieRp/Include + +IpBlock/Gpio/Include + + +## +# +# This section is for IP ConfigBlock versions control +# +# - Memory +Include/ConfigBlock/Memory/Ver2 +# +# - Graphics +Include/ConfigBlock/Graphics/Gen12 +# +# - CPU PCIe +Include/ConfigBlock/CpuPcieRp/Gen4 +Include/ConfigBlock/CpuDmi + +# - Hybrid Graphics +Include/ConfigBlock/HybridGraphics + +Include +# +# SystemAgent +# +SystemAgent/Include +SystemAgent/AcpiTables +SystemAgent/AcpiTables/SaSsdt +Include/ConfigBlock/Vtd +Include/ConfigBlock/PcieRp +Include/ConfigBlock/Gna +Include/ConfigBlock/CpuPcieRp/Gen4 +Include/ConfigBlock/CpuDmi +Include/ConfigBlock/HybridGraphics +Include/ConfigBlock/HostBridge +# +# Cpu +# +Cpu/Include +Include/ConfigBlock/Overclocking +Include/ConfigBlock/VoltageRegulator + +# +# Pch +# +Pch/Include +Include/ConfigBlock/Thermal +Include/ConfigBlock/P2sb +Include/ConfigBlock/Ish +Include/ConfigBlock/Usb +Include/ConfigBlock/Espi +Include/ConfigBlock/Fivr +Include/ConfigBlock/Rtc +Include/ConfigBlock/Smbus +Include/ConfigBlock/Pmc +Include/ConfigBlock/Itss +Include/ConfigBlock/Scs +Include/ConfigBlock/Hda +Include/ConfigBlock/Sata +Include/ConfigBlock/Rst +Include/ConfigBlock/Ieh +Include/ConfigBlock/Me +Include/ConfigBlock/PchDmi +Include/ConfigBlock/Gpio +Include/ConfigBlock/Dci +Include/ConfigBlock/Cnvi +Include/ConfigBlock/Gbe +Include/ConfigBlock/TraceHub +Include/ConfigBlock/Thc +Include/ConfigBlock/Wdt +Include/ConfigBlock/PcieRp/PchPcieRp +Include/ConfigBlock/PcieRp +Include/ConfigBlock/Psf +Include/ConfigBlock/SerialIo +Include/ConfigBlock/HybridStorage +Include/ConfigBlock/Spi + + +# +# - Tcss +Include/ConfigBlock/Tcss +[Guids.common.Private] +# +# PCH +# +gPchDeviceTableHobGuid =3D { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x6= 6, 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }} +gWdtHobGuid =3D { 0x65675786, 0xacca, 0x4b11, { 0x8a, 0xb= 7, 0xf8, 0x43, 0xaa, 0x2a, 0x8b, 0xea }} +gPchConfigHobGuid =3D { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd= 9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }} +gGpioLibUnlockHobGuid =3D { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD= 6, 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }} +gSiScheduleResetHobGuid =3D { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC= 1, 0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }} +gCnviConfigHobGuid =3D { 0xa8d6e4d9, 0x94b7, 0x4fc9, { 0x94, 0x3= f, 0x7a, 0x9c, 0xb2, 0x31, 0x57, 0xce }} + +# +# CPU +# +gPeiAcpiCpuDataGuid =3D { 0x7682bbef, 0xb0b6, 0x4939, { 0xae, 0x6= 6, 0x1b, 0x3d, 0xf2, 0xf6, 0xaa, 0xf3 }} +gCpuStatusCodeDataTypeExceptionHandlerGuid =3D { 0x3BC2BD12, 0xAD2E, 0x11D= 5, { 0x87, 0xDD, 0x00, 0x06, 0x29, 0x45, 0xC3, 0xB9 }} + +# +# SA +# +gSchemaListGuid =3D { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0xC= B, 0xEA, 0xAD, 0x0A, 0x88, 0x86, 0x1B }} +gEqPhase3SchemaGuid =3D { 0x145AC084, 0x340E, 0x4777, { 0xBC, 0x7= 5, 0xF8, 0x50, 0x5F, 0xFD, 0x50, 0x9D }} +gScoreSchemaGuid =3D { 0x8233A1BB, 0x58D5, 0x4F66, { 0xA1, 0x3= F, 0x8A, 0xA3, 0xED, 0x6A, 0xF5, 0xA0 }} +gPortMarginGuid =3D { 0xD7154D12, 0x03B2, 0x4054, { 0x8C, 0xD= 2, 0x9F, 0x4B, 0x20, 0x90, 0xBE, 0xF7 }} +gJitterTolerenceGuid =3D { 0xB52A2E04, 0x45FF, 0x484E, { 0xB5, 0xF= E, 0xEE, 0x47, 0x8F, 0x5F, 0x6C, 0x9B }} +gLaneMarginGuid =3D { 0x7AC0996D, 0xA601, 0x4210, { 0x94, 0x4= E, 0x93, 0x4E, 0x51, 0x7B, 0x6C, 0x57 }} +gVocMarginGuid =3D { 0x3578349A, 0x9E98, 0x4F70, { 0x91, 0xC= B, 0xE2, 0x5B, 0x98, 0x99, 0xBC, 0x16 }} + +[Guids] +gSmbiosProcessorInfoHobGuid =3D {0xe6d73d92, 0xff56, 0x4146, {0xaf= , 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71}} +gSmbiosCacheInfoHobGuid =3D {0xd805b74e, 0x1460, 0x4755, {0xbb= , 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7}} + +## +## IntelFrameworkPkg +## +# MsegSmramPei.inf +gEfiSmmPeiSmramMemoryReserveGuid =3D {0x6dadf1d1, 0xd4cc, 0x4910, {0xbb= , 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}} +## +## MdeModulePkg +## +gEfiMemoryTypeInformationGuid =3D {0x4c19049f, 0x4137, 0x4dd3, {0x9c, 0x= 10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}} +gEfiCapsuleVendorGuid =3D {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36= , 0xec, 0xbd, 0x3c, 0x8b, 0xe2}} +gEfiConsoleOutDeviceGuid =3D { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, 0= x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}} +## +## Common +## +## Include/ConfigBlock/SiConfig.h +gSiConfigGuid =3D {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x9= 7, 0x38, 0x59, 0xd8}} +## +gSiPreMemConfigGuid =3D {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b, 0x= 25, 0x88, 0xbe, 0xfd, 0xc6}} +## +## +gPciePreMemConfigGuid =3D {0xd0f9c2a9, 0x7332, 0x4733, {0x8d, 0xb1, 0x98, = 0x79, 0x27, 0x60, 0xda, 0xe6}} +## +gSiPkgTokenSpaceGuid =3D {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x43,= 0x66, 0x99, 0xcb, 0xe4, 0x5b}} +## Include/SiConfigHob.h +gSiConfigHobGuid =3D {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0x5f,= 0x8f, 0xd7, 0x65, 0x4e}} +gBootMediaHobGuid =3D {0x8c7340ea, 0xde8b, 0x4e06, {0xa4, 0x78, 0xec, 0x8b= , 0x62, 0xd7, 0xa, 0x8b}} +gEfiPramConfGuid =3D { 0xecb54cd9, 0xe5ae, 0x4fdc, { 0xa9, 0x71, 0xe8, 0x7= 7, 0x75, 0x60, 0x68, 0xf7}} +## +## +## IPU's GUIDs +## +gIpuDataHobGuid =3D {0x61dd66, 0x212b, 0x4dae, {0x9b, 0xc0, 0x30, 0xe0, 0= x2e, 0x3f, 0x40, 0xfd}} +gIpuConfigHobGuid =3D {0x446268e5, 0x8c30, 0x4e0a, {0x9b, 0x28, 0xa3, 0xe= 7, 0xf0, 0x4, 0x31, 0xd0}} + +## Include/FspErrorInfo.h +gFspErrorInfoHobGuid =3D {0x611e6a88, 0xadb7, 0x4301, {0x93, 0xff, 0xe4, 0= x73, 0x04, 0xb4, 0x3d, 0xa6}} +gStatusCodeDataTypeFspErrorGuid =3D {0x611e6a88, 0xadb7, 0x4301, {0x93, 0x= ff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6}} + +## +## +## SystemAgent +## +gSaOverclockingPreMemConfigGuid =3D { 0x09ecc29d, 0xdbbe, 0x49fb, { 0xa6= , 0x49, 0x4b, 0xf6, 0x40, 0xe2, 0xeb, 0xd6}} +gSaAcpiTableStorageGuid =3D {0x3c0ed5e2, 0x91ea, 0x4b94, { 0x82, 0xd, 0x= 9d, 0xaf, 0x9a, 0x3b, 0xb4, 0xa2}} +gSaDataHobGuid =3D {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2, 0xc4= , 0x4a, 0x0e, 0xd6, 0xd0}} +gPsmiDataHobGuid =3D {0xa9652bd, 0x6acd, 0x47e5, { 0x80, 0x3a, 0x9, 0x53= , 0x7b, 0xd2, 0xa8, 0x48 }} +gSaConfigHobGuid =3D {0x762fa2e6, 0xea3b, 0x41c8, { 0x8c, 0x52, 0x63, 0x7= 6, 0x6d, 0x70, 0x39, 0xe0}} +gCpuPcieHobGuid =3D {0x440ab2e5, 0xa3ea, 0x466f, { 0x84, 0x96, 0xdf, 0xb1= , 0x3b, 0x75, 0x29, 0x95}} +gSaPegHobGuid =3D {0x5807c388, 0xfa06, 0x4683, { 0xab, 0xd3, 0x1b, 0x31= , 0xbb, 0x81, 0x2d, 0x23}} +gHgAcpiTableStorageGuid =3D {0x8de8964f, 0x2939, 0x4b49, { 0xa3, 0x48, 0= xf6, 0xb2, 0xb2, 0xde, 0x4a, 0x42}} +gSaSsdtAcpiTableStorageGuid =3D {0xca89914d, 0x2317, 0x452e, { 0xb2, 0x4= 5, 0x36, 0xc6, 0xfb, 0x77, 0xa9, 0xc6}} +gSegSsdtAcpiTableStorageGuid =3D {0x10c3800d, 0xe225, 0x480e, { 0x85, 0x= da, 0xbe, 0xed, 0xdb, 0x88, 0xe1, 0xc6}} +gHgAcpiTablePchStorageGuid =3D {0xe3164526, 0x690a, 0x4e0d, { 0xb0, 0x28= , 0xae, 0xa1, 0x6f, 0xe2, 0xbc, 0xf3}} +gSaMiscPeiPreMemConfigGuid =3D {0x4a525577, 0x3469, 0x4f11, { 0x99, 0xcf= , 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}} +gSaMiscPeiConfigGuid =3D {0x1def8e6, 0xe998, 0x4e27, { 0x89, 0x98, 0x9c,= 0xfa, 0xb2, 0x92, 0xbc, 0x50}} +gCpuPciePeiPreMemConfigGuid =3D { 0x81baf3c9, 0xf295, 0x4572, { 0x8b, 0x= 21, 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}} +gCpuDmiPreMemConfigGuid =3D { 0x30d12ad5, 0xa3c6, 0x49c7, { 0xa2, 0xfd, = 0x35, 0x5c, 0xcb, 0x61, 0xcb, 0xcf}} +gVmdPeiConfigGuid =3D { 0x79b52c74, 0xb9ba, 0x4f36, {0xa2, 0x40, 0xf2, 0x4= 1, 0x0d, 0x20, 0x84, 0x8a}} +gVmdInfoHobGuid =3D { 0xccd0306e, 0x7fa1, 0x4df5, {0x99, 0x99, = 0xc1, 0xf8, 0x9a, 0x1d, 0x1b, 0xa9}} +gEfiVmdFeatureVariableGuid =3D { 0x61a14fe8, 0x4dab, 0x4a19, {0xb1, 0xe3, = 0x97, 0xfb, 0x23, 0xd0, 0x92, 0x12}} +gPramPreMemConfigGuid =3D { 0xcf0b9b31, 0xa1a6, 0x46d9, { 0x8d, 0x14, 0x= e3, 0xac, 0x69, 0x0f, 0x52, 0x3a}} +gHybridGraphicsConfigGuid =3D { 0xc7956998, 0xc065, 0x46c4, { 0x8e, 0x2f= , 0x58, 0x2b, 0x67, 0xeb, 0xbe, 0x2f}} +gHybridGraphicsInfoHobGuid =3D { 0x46cbed07, 0x717a, 0x4a75, { 0x85, 0xb3= , 0xf4, 0xb6, 0xc4, 0xe2, 0x3a, 0x75}} +gMemoryConfigGuid =3D { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1, = 0x97, 0xb8, 0xa1, 0xe4, 0xbf}} +gMemoryConfigNoCrcGuid =3D { 0xc56c73d0, 0x1cdb, 0x4c0c, { 0xa9, 0x57, 0= xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}} +gGnaConfigGuid =3D { 0x53e0ef18, 0xb8a8, 0x4795, { 0xa6, 0x6d, 0xe4, 0x7= 7, 0x2c, 0xc3, 0xae, 0x82}} +gVtdDxeConfigGuid =3D {0xcbbf1996, 0x4a4c, 0x4dd9, {0xab, 0xbe, 0x83, 0x= 89, 0x73, 0xd, 0x48, 0xb0}} +gPcieDxeConfigGuid =3D {0x1ed2d6f1, 0xa9d2, 0x476e, {0x8e, 0x74, 0xad, 0= xd9, 0x5b, 0x5, 0x10, 0x82}} +gMemoryDxeConfigGuid =3D {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40, 0xf8,= 0x2, 0xd, 0x84, 0x4c, 0x94}} +gFspReservedMemoryResourceHobTsegGuid =3D { 0xd038747c, 0xd00c, 0x4980, = { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}} +gCpuPcieRpPrememConfigGuid =3D { 0x41aef892, 0xc800, 0x4ac0, {0xa9, 0x30, = 0x84, 0xac, 0x47, 0xca, 0xca, 0x7e}} +gCpuPcieRpConfigGuid =3D { 0x9749a5fb, 0x9130, 0x44f0, {0x8f, 0x61, 0xdb, = 0xff, 0x8e, 0xf2, 0xca, 0xc7}} +## Include/Guid/AcpiS3Context.h +gEfiAcpiVariableGuid =3D {0xaf9ffd67, 0xec10, 0x488a, {0x9d, 0xfc, 0x6c,= 0xbf, 0x5e, 0xe2, 0x2c, 0x2e}} +## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as gFspNo= nVolatileStorageHobGuid +gSiMemoryS3DataGuid =3D { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, = 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } } +gSiMemoryInfoDataGuid =3D { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, = 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } } +gSiMemoryPlatformDataGuid =3D { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, = 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } } +## Include/MrcRmtData.h +gEfiMemorySchemaGuid =3D { 0xCE3F6794, 0x4883, 0x492C, { 0x8D, 0xBA, 0x2F= , 0xC0, 0x98, 0x44, 0x77, 0x10}} +gMrcSchemaListHobGuid =3D { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0xCB, 0xEA= , 0xAD, 0x0A, 0x88, 0x86, 0x1B}} +gRmtResultMetadataGuid =3D { 0x02CB1552, 0xD659, 0x4232, { 0xB5, 0x1F, 0xC= A, 0xB1, 0xE1, 0x1F, 0xCA, 0x87}} +gRmtResultColumnsGuid =3D { 0x0E60A1EB, 0x331F, 0x42A1, { 0x9D, 0xE7, 0x4= 5, 0x3E, 0x84, 0x76, 0x11, 0x54}} +gMargin2DResultMetadataGuid =3D { 0x48265582, 0x8E49, 0x4AC7, { 0xAA, 0x06= , 0xE1, 0xB9, 0xA7, 0x4C, 0x97, 0x16}} +gMargin2DResultColumnsGuid =3D { 0x91A449EC, 0x8A4A, 0x4736, { 0xAD, 0x71= , 0xA3, 0xF6, 0xF6, 0xD7, 0x52, 0xD9}} +gSaFspErrorTypePeiGopInit =3D { 0x8106a5cc, 0x30ba, 0x41cf, { 0xa1, 0x78, = 0x63, 0x38, 0x91, 0x11, 0xae, 0xb2}} +gSaFspErrorTypePeiGopGetMode =3D { 0x348cc7fe, 0x1e9a, 0x4c7a, { 0x86, 0x2= 8, 0xae, 0x48, 0x5b, 0x42, 0x10, 0xf0}} +gSaFspErrorTypeCallerId =3D { 0x98230916, 0xe632, 0x49ff, { 0x81, 0x81, 0x= 55, 0xce, 0xe5, 0x10, 0x36, 0x89}} +gMrcFspErrorTypeCallerId =3D { 0x5a47c211, 0x642f, 0x4f92, { 0x9c, 0xb3, 0= x7f, 0xeb, 0x93, 0xda, 0xdd, 0xba}} +gMrcFspErrorTypeMemoryInit =3D { 0x5de1c071, 0x2c9c, 0x4a53, { 0x80, 0x21,= 0x4e, 0x80, 0xd2, 0x5d, 0x44, 0xa8}} +gSaPciePeiConfigGuid =3D { 0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x82,= 0x3a, 0x55, 0xc7, 0xb5, 0xb3}} +gSaPciePeiPreMemConfigGuid =3D { 0xfc5e01a3, 0x69f6, 0x4e35, { 0x9f, 0xcf,= 0x6, 0x68, 0x7b, 0xab, 0x31, 0xd7}} + + +# +# Host Bridge +# +gHostBridgePeiPreMemConfigGuid =3D {0xbdef6805, 0x2080, 0x44ad, { 0x93, = 0x2e, 0x00, 0x04, 0xf5, 0x2c, 0xb7, 0xa1}} +gHostBridgePeiConfigGuid =3D {0x3b6d998e, 0x8b6e, 0x4f53, { 0xbe, 0x41, = 0x7, 0x41, 0x95, 0x53, 0x8a, 0xaf}} +gHostBridgeDataHobGuid =3D {0x3b682d57, 0xd402, 0x40a6, { 0xb1, 0x34, 0x= a0, 0xc4, 0xf6, 0x31, 0x1d, 0x9}} + +# +# Graphics +# +gGraphicsPeiPreMemConfigGuid =3D {0x0319c56b, 0xc43a, 0x42f1, { 0x80, 0x= be, 0xca, 0x5b, 0xd1, 0xd5, 0xc9, 0x28}} +gGraphicsPeiConfigGuid =3D {0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e, 0x= a7, 0x04, 0x2a, 0x06, 0x2f, 0x5d}} +gGraphicsDxeConfigGuid =3D {0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0xd= b, 0x67, 0x16, 0x42, 0x39, 0x24}} +gGraphicsAcpiTableStorageGuid =3D {0xce9caa0e, 0x8248, 0x442c, { 0x9e, 0= x57, 0x50, 0xf2, 0x12, 0xe2, 0xba, 0xed}} +## IpBlock/Graphics/IncludePrivate/GraphicsDataHob.h +gGraphicsDataHobGuid =3D { 0x48e6e20a, 0x9110, 0x4332, { 0x8c, 0x9f, 0x5f,= 0x7c, 0xae, 0x76, 0xfc, 0xf3}} + +# +# IPU +# +gIpuPreMemConfigGuid =3D { 0x830a222b, 0x3ff5, 0x432e, { 0x9d, 0xd5, 0x4= e, 0xe3, 0xfc, 0xa2, 0xaa, 0xa2}} +gIpuAcpiTableStorageGuid =3D {0x9b25dba6, 0x45b3, 0x4190, { 0x99, 0x8d, = 0xaf, 0x31, 0xdc, 0x21, 0x78, 0x21}} + +## Include/SsaCommonConfig.h +gSsaPostcodeHookGuid =3D {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46, 0= x87, 0xE7, 0x9E, 0x6F, 0xBB}} +gSsaBiosVariablesGuid =3D {0x43eeffe8, 0xa978, 0x41dc, {0x9d, 0xb6, 0x54, = 0xc4, 0x27, 0xf2, 0x7e, 0x2a}} +gSsaBiosResultsGuid =3D {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47, 0x9f= , 0xda, 0x27, 0x9d, 0xb6}} +gHobUsageDataGuid =3D {0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, 0x2= 0, 0xfc, 0x7c, 0xe1, 0xf6 }} +## +## TBT +## +gPeiITbtConfigGuid =3D {0xd7e7e1e6, 0xcbec, 0x4f5f, {0xae, 0xd= 3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}} +gDxeITbtConfigGuid =3D {0x196bf9e3, 0x20d7, 0x4b7b, {0x89, 0xf= 9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}} +gITbtInfoHobGuid =3D {0x74a81eaa, 0x033c, 0x4783, {0xbe, 0x2= b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}} + +## +## TCSS +## +gTcssHobGuid =3D { 0x455702ce, 0x4adb, 0x45d9, { 0x8b, 0x27, 0xf7, 0xb0, = 0xd9, 0x79, 0x8a, 0xe0}} +gTcssSsdtAcpiTableStorageGuid =3D { 0xbd53572c, 0x6486, 0x45e2, { 0x90, = 0xe, 0xb9, 0x8a, 0xc1, 0xa8, 0x25, 0x45}} +gTcssPeiConfigGuid =3D { 0xfb631590, 0x79c9, 0x4f0d, { 0xa9, 0x96, 0xee, = 0xe2, 0x98, 0x66, 0xfa, 0xfd}} +gTcssPeiPreMemConfigGuid =3D { 0x514ed829, 0xb2bb, 0x46be, { 0xa9, 0x78, 0= x6d, 0xc, 0x91, 0xc1, 0xeb, 0xe4}} +gTcssSsidHobGuid =3D { 0x8903d47a, 0x8f82, 0x4063, { 0xa8, 0x40, 0x31, 0x= 68, 0x9c, 0x9e, 0x78, 0x20}} +## +## Telemetry +## +gTelemetryPeiConfigGuid =3D { 0x8ebf9fee, 0x7496, 0x42b4, { 0xa6, 0= xf6, 0xcf, 0x2b, 0x33, 0x99, 0x30, 0xd6}} +gTelemetryPeiPreMemConfigGuid =3D { 0x422de269, 0xb2ef, 0x4829, { 0x93, 0= x36, 0x0b, 0xe4, 0x98, 0xb5, 0x53, 0xb2}} + +## +## VTD +## +gVtdDataHobGuid =3D {0x1d60dce8, 0x503a, 0x44a8, { 0xb3, 0x2d, 0x56, 0xb3= , 0x88, 0xf3, 0x4c, 0x55}} +gVtdConfigGuid =3D {0x03e5cf63, 0xbebb, 0x4041, { 0xb7, 0xe7, 0xbf, 0x54= , 0x61, 0x20, 0xf1, 0xc5}} + +# +# TRACEHUB +# +gCpuTraceHubPreMemConfigGuid =3D { 0xf2e17477, 0x93f3, 0x430d, { 0x9e, 0x= 08, 0x3c, 0xcc, 0x6e, 0x2f, 0x6c, 0x4b}} +gTraceHubDataHobGuid =3D { 0xf1187e54, 0x995f, 0x49d9, { 0xac, 0x= ee, 0xc5, 0x34, 0xf4, 0x5a, 0x18, 0xc7}} + +## +## Cpu +## +gSmramCpuDataHeaderGuid =3D {0x5848fd2d, 0xd6af, 0x474b, {0x82, 0x75, 0x= 95, 0xdd, 0xe7, 0x0a, 0xe8, 0x23}} +gCpuAcpiTableStorageGuid =3D {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44, 0= x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}} +gTxtInfoHobGuid =3D {0x2986883f, 0x88e0, 0x48d0, {0x4b, 0x82, 0x20, 0xc2= , 0x69, 0x48, 0xdd, 0xac}} +gHtBistHobGuid =3D {0xbe644001, 0xe7d4, 0x48b1, {0xb0, 0x96, 0x8b, 0xa0,= 0x47, 0xbc, 0x7a, 0xe7}} +gProcessorProducerGuid =3D {0x1bf06aea, 0x5bec, 0x4a8d, {0x95, 0x76, 0x7= 4, 0x9b, 0x09, 0x56, 0x2d, 0x30}} +gCpuInitDataHobGuid =3D {0x266e31cc, 0x13c5, 0x4807, {0xb9, 0xdc, 0x39, = 0xa6, 0xba, 0x88, 0xff, 0x1a}} +gBiosGuardHobGuid =3D {0x66f0c42d, 0x0d0e, 0x4c23, {0x93, 0xc0, 0x2d, 0x= 52, 0x95, 0xdc, 0x5e, 0x21}} +gCpuSecurityPreMemConfigGuid =3D {0xfd5c346, 0x8260, 0x4067, {0x94, 0x69, = 0xcf, 0x91, 0x68, 0xa3, 0x42, 0x90}} +gCpuConfigLibPreMemConfigGuid =3D {0xfc1c0ec2, 0xc6b4, 0x4f05, {0xbb, 0x85= , 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}} +gCpuTxtPreMemConfigGuid =3D {0x20b4db03, 0xd160, 0x4f83, {0xa4, 0x1, 0x9a,= 0x8a, 0xa8, 0x88, 0x68, 0x14}} +gCpuTestConfigGuid =3D {0xd4dba957, 0xd9c, 0x4af2, {0x9d, 0x40, 0x35, 0xa8= , 0x44, 0xe4, 0x93, 0xad}} +gBiosGuardConfigGuid =3D {0x762f9ddb, 0x1c89, 0x4612, {0x84, 0x6b, 0xee, 0= xdc, 0x8f, 0x62, 0x25, 0x45}} +gCpuConfigGuid =3D {0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, 0x= 5f, 0x46, 0x53, 0x41}} +gCpuPidTestConfigGuid =3D {0x2511095f, 0xd49e, 0x4537, {0xa6, 0x60, 0x88, = 0x71, 0x31, 0xd1, 0x53, 0xda}} +gCpuPowerMgmtBasicConfigGuid =3D {0xa021e31d, 0x7c14, 0x47da, {0xb5, 0xec,= 0xca, 0xbb, 0x4d, 0x76, 0xed, 0xc8}} +gCpuPowerMgmtCustomConfigGuid =3D {0x562fa1c8, 0x55ee, 0x4e2f, {0x91, 0xca= , 0x8d, 0x84, 0x50, 0x3, 0x2f, 0xe}} +gCpuPowerMgmtPsysConfigGuid =3D {0x4e7f850, 0x19b5, 0x47ba, {0x9d, 0x28, 0= xb1, 0xe7, 0x5e, 0x1f, 0x48, 0x53}} +gCpuPowerMgmtTestConfigGuid =3D {0x5161ed3d, 0x90bf, 0x436f, {0xb8, 0x33, = 0xd7, 0x17, 0x89, 0xb3, 0x48, 0xc1}} +gCpuPowerMgmtVrConfigGuid =3D {0x254766c9, 0x929d, 0x4eac, {0x9e, 0xec, 0x= df, 0xa2, 0x2, 0x44, 0xb5, 0xea}} +gTxtPrivateBaseHobGuid =3D {0x651EBDB4, 0x4E1D, 0x422A, {0x82, 0xFB, 0x1E,= 0xDA, 0x66, 0x71, 0x6C, 0x0B}} +gTxtAcmInfoTableGuid =3D {0x7FC03AAA, 0x46A7, 0x18DB, {0x2E, 0xAC, 0x69, 0= x8F, 0x8D, 0x41, 0x7F, 0x5A}} +gOverclockingPreMemConfigGuid =3D {0xad151bbc, 0xd5a0, 0x481e, {0x9d, 0x19= , 0xf6, 0x7b, 0x79, 0xe9, 0x8f, 0x68}} +gCpuDataHobGuid =3D {0x1eec629f, 0xf3cf, 0x4b02, { 0xa9, 0xa5, 0x27, 0xa2,= 0x33, 0x20, 0xbe, 0x5d}} + +## +## Me +## +gMePlatformReadyToBootGuid =3D {0x03fdf171, 0x1d67, 0x4ace, {0xa9, 0x04,= 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74}} +gMeSsdtAcpiTableStorageGuid =3D {0x9a8f82d5, 0x39b1, 0x48da, {0x92, 0xdc= , 0xa2, 0x2d, 0xa8, 0x83, 0x4d, 0xf6}} +gMeDataHobGuid =3D {0x1e94f097, 0x5acd, 0x4089, {0xb2, 0xe3, 0xb9, 0xa5,= 0xc8, 0x79, 0xa7, 0x0c}} +gMeEDebugHobGuid =3D {0x5f672ec1, 0xa8f6, 0x47d3, {0x9c, 0xd0, 0x92, 0xe9,= 0xe9, 0xe0, 0xb3, 0x84}} +gPciImrHobGuid =3D {0x49b1eac3, 0x0cd6, 0x451e, {0x96, 0x30, 0x92, 0x4b,= 0xc2, 0x69, 0x35, 0x86}} +gTpm2AcpiTableStorageGuid =3D {0x7d279373, 0xeecc, 0x4d4f, {0xae, 0x2f, = 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a}} +gMeBiosPayloadHobGuid =3D {0x992c52c8, 0xbc01, 0x4ecd, {0x20, 0xbf, 0xf9= , 0x57, 0x16, 0x0e, 0x9e, 0xf7}} +gEfiTouchPanelGuid =3D {0x91b1d27b, 0xe126, 0x48d1, {0x82, 0x34, 0xd2, 0= x8b, 0x81, 0xc8, 0x83, 0x62}} +gMeFwHobGuid =3D {0x52885e62, 0x4c4d, 0x9546, {0x2d, 0xba, 0x2a, 0x84, 0x= 89, 0xee, 0xa8, 0xa3 }} +gMePeiPreMemConfigGuid =3D {0x67ed113b, 0xd4ab, 0x43f5, {0x9c, 0x3c, 0x3= 5, 0x44, 0x15, 0xaa, 0x47, 0x5c}} +gMePeiConfigGuid =3D {0x9bad5628, 0x657b, 0x48e3, {0xb1, 0x11, 0xc3, 0xb= 9, 0xeb, 0xea, 0xee, 0x17}} +gMeDxeConfigGuid =3D {0xad08bacc, 0x4906, 0x4d9b, {0xbe, 0xd1, 0x81, 0xa= 5, 0x2c, 0x13, 0xdb, 0xf8}} +gIvmProtocolGuid =3D {0x3C4852D6, 0xD47B, 0x4F46, {0xB0, 0x5E, 0xB5, 0xED= , 0xC1, 0xAA, 0x44, 0x0E}} +gSdmProtocolGuid =3D {0xDBA4D603, 0xD7ED, 0x4931, {0x88, 0x23, 0x17, 0xAD= , 0x58, 0x57, 0x05, 0xD5}} +gRtmProtocolGuid =3D {0x5565A099, 0x7FE2, 0x45C1, {0xA2, 0x2B, 0xD7, 0xE9= , 0xDF, 0xEA, 0x9A, 0x2E}} +gSvmProtocolGuid =3D {0xF47ACC04, 0xD94B, 0x49CA, {0x87, 0xA6, 0x7F, 0x7D= , 0xC0, 0x3F, 0xBA, 0xF3}} +gMeEopDoneHobGuid =3D {0x247323af, 0xc8f1, 0x4b8c, {0x90, 0x87, 0xaa, 0x4b= , 0xa7, 0xb7, 0x6d, 0x6a}} +gMePreMemPolicyHobGuid =3D {0xe6de74a5, 0x21b, 0x4f78, {0xa3, 0xcd, 0x34, = 0xd6, 0x7e, 0xe4, 0x82, 0xbf}} +gMePolicyHobGuid =3D {0x0341cf17, 0xbc8f, 0x4a20, {0xac, 0x28, 0x6c, 0x3c= , 0x32, 0x4c, 0xd4, 0x17}} +gMeFspErrorTypeEop =3D {0x948585c4, 0x76a4, 0x45bb, {0xbe, 0x6c, 0x39, 0x6= 1, 0xc3, 0xab, 0xde, 0x15}} +gMeFspErrorTypeCallerId =3D {0x1f4dc7e9, 0x26ca, 0x4336, { 0x8c, 0xe3, 0x3= 9, 0x31, 0x3, 0xb5, 0xf3, 0xd7}} +gMeConfigSpaceGuid =3D {0xcb405fd3, 0x4404, 0x4ccd, {0x85, 0x18, 0x0d, 0x0= 3, 0x07, 0x48, 0xd0, 0xa6}} +gMeDidSentHobGuid =3D {0x4c3d3af1, 0x1720, 0x4c3f, {0xab, 0x7c, 0x36, 0x50= , 0xbb, 0x5b, 0x85, 0x7e}} +gMeDisabledEventHobGuid =3D {0x1500b6a7, 0xb82f, 0x456b, {0xba, 0x2b, 0x4,= 0x72, 0x41, 0x6, 0xf, 0x7}} +gMeSavedPmconHobGuid =3D {0xb8baee93, 0xea15, 0x4ddc, {0x90, 0xb8, 0x44, 0= x12, 0xd2, 0xea, 0xcf, 0x4f}} + +## +## Amt +## +gAmtForcePushPetPolicyGuid =3D {0xacc8e1e4, 0x9f9f, 0x4e40, {0xa5, 0x7e,= 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5}} +gAmtForcePushPetVariableGuid =3D {0xd7ac94af, 0xa498, 0x45ec, {0xbf, 0xa= 2, 0xa5, 0x6e, 0x95, 0x34, 0x61, 0x8b}} +gMeBiosExtensionSetupGuid =3D {0xaf013532, 0xc828, 0x4fbd, {0x20, 0xae, = 0xfe, 0xe6, 0xaf, 0xbe, 0xdd, 0x4e}} +gAmtPetQueueHobGuid =3D {0xca0801d3, 0xafb1, 0x4dec, {0x9b, 0x65, 0x93, = 0x65, 0xec, 0xc7, 0x93, 0x6b}} +gAmtForcePushPetHobGuid =3D {0x4efa0db6, 0x26dc, 0x4bb1, {0xa7, 0x6f, 0x= 14, 0xbc, 0x63, 0x0c, 0x7b, 0x3c}} +gAmtPeiConfigGuid =3D {0x7254546a, 0xace3, 0x4a32, {0x9a, 0xc2, 0xf0, 0x= cc, 0x28, 0x4e, 0x1e, 0x4d}} +gAmtDxeConfigGuid =3D {0x3f12ab6b, 0xb04d, 0x4824, {0xbf, 0xb6, 0x3e, 0x= e7, 0x5d, 0x02, 0x0b, 0x84}} +gAmtPolicyHobGuid =3D {0x703eb2cd, 0x5ca8, 0x4233, {0x9d, 0xa3, 0x0d, 0x2d= , 0x57, 0xe6, 0x73, 0x34}} +gAmtMebxDataGuid =3D { 0x912e1538, 0x371d, 0x4ea6, { 0xa8, 0x41, 0xd7, 0x= 6a, 0x8, 0x93, 0x3a, 0x70}} + +## +## PCH +## +gEfiSmbusArpMapGuid =3D {0x707be83e, 0x0bf6, 0x40a5, {0xbe, 0x64, 0x34, = 0xc0, 0x3a, 0xa0, 0xb8, 0xe2}} +gIrmtAcpiTableStorageGuid =3D {0x6684d675, 0xee06, 0x49b2, {0x87, 0x6f, = 0x79, 0xc5, 0x8f, 0xdd, 0xa5, 0xb7}} +gPchGlobalResetGuid =3D { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18= , 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }} +gI2c0MasterGuid =3D {0xa121a5db, 0xb0cb, 0x46ec, {0xa0, 0xcb, 0x27, 0xf8= , 0xda, 0x72, 0xd4, 0x0e}} +gI2c1MasterGuid =3D {0x55e3d0f9, 0xc954, 0x422d, {0x9c, 0x4c, 0xcc, 0x46= , 0x12, 0x7c, 0x5b, 0xa8}} +gI2c2MasterGuid =3D {0x9289aa40, 0xdf32, 0x474e, {0xb0, 0x3a, 0xc7, 0x7f= , 0x76, 0xd3, 0x45, 0x21}} +gI2c3MasterGuid =3D {0xd8b2c17f, 0x4117, 0x4166, {0x90, 0x17, 0x01, 0x68= , 0xb4, 0x81, 0xac, 0x18}} +gI2c4MasterGuid =3D {0x513d943d, 0x15d9, 0x4bd0, {0xb1, 0x41, 0x14, 0x50= , 0x2b, 0xbf, 0xa9, 0xf2}} +gI2c5MasterGuid =3D {0x50df382a, 0xb6bf, 0x4435, {0xae, 0xe6, 0x21, 0xf4= , 0x85, 0x7c, 0xa8, 0xb4}} +gChipsetInitHobGuid =3D {0xc1392859, 0x1f75, 0x446e, {0xb3, 0xf5, 0x83, = 0x35, 0xfc, 0xc8, 0xd1, 0xc4}} + +gPchGeneralPreMemConfigGuid =3D {0xC65F62FA, 0x52B9, 0x4837, {0x86, 0xEB,= 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}} +gDciPreMemConfigGuid =3D {0xAB4AF366, 0x2250, 0x40C3, {0x92, 0xDB, 0x36= , 0x61, 0xC6, 0x71, 0x3C, 0x5A}} +gWatchDogPreMemConfigGuid =3D {0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, 0x88, = 0x09, 0xBB, 0x81, 0x65, 0x52, 0x2B}} +gPchTraceHubPreMemConfigGuid =3D {0x8456c11, 0xdb85, 0x4914, {0x8d, 0x1a,= 0xe5, 0xac, 0x64, 0x37, 0xe8, 0x96}} +gPcieRpPreMemConfigGuid =3D {0x8377AB38, 0xF8B0, 0x476A, { 0x9C, 0xA1, 0= x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}} +gSmbusPreMemConfigGuid =3D {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0x2= 3, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}} +gLpcPreMemConfigGuid =3D {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC6,= 0x30, 0xC6, 0xC4, 0x11, 0x8E}} +gHsioPciePreMemConfigGuid =3D {0xE8FB0C12, 0x0DA1, 0x4A20, {0xB3, 0x36, = 0xFB, 0x75, 0x93, 0x8C, 0xE0, 0x14}} +gHsioSataPreMemConfigGuid =3D {0x732260D0, 0xA5C1, 0x4119, {0xAA, 0x0C, = 0x93, 0xDC, 0xAC, 0x67, 0x0A, 0x31}} + +gPchGeneralConfigGuid =3D {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0xCA= , 0x4D, 0xE2, 0x95, 0x4B, 0x5D}} +gPchPcieConfigGuid =3D {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, 0= xDE, 0x10, 0x6D, 0x94, 0x84}} +gPchPcieRpDxeConfigGuid =3D {0x475530EA, 0xBD72, 0x416F, {0x98, 0x9F,0x4= 8, 0x70, 0x5F, 0x14, 0x4E, 0xD9}} +gSataConfigGuid =3D {0xF5F87B4F, 0xCC3C, 0x408D, {0x89, 0xE3, 0x61, 0xC5= , 0x9C, 0x54, 0x07, 0xC4}} +gRstConfigGuid =3D {0x43B6F112, 0x3851, 0x4DDC, {0x81, 0xB9, 0xE4, 0x5A, 0= x2B, 0xE, 0xB3, 0x25}} +gIoApicConfigGuid =3D {0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, 0x= 68, 0xBA, 0x87, 0x3E, 0x6C}} +gPchDmiConfigGuid =3D {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6, 0xD3, 0x= 42, 0x9C, 0x4F, 0x17, 0xBD}} +gFlashProtectionConfigGuid =3D {0xD0F71512, 0x9E32, 0x4CC9, {0xA5, 0xA3,= 0xAD, 0x67, 0x9A, 0x06, 0x67, 0xB8}} +gHdAudioPreMemConfigGuid =3D {0xD38F1E2B, 0x21B3, 0x43D1, {0x9F, 0xA8, 0= xA5, 0xE1, 0x78, 0x73, 0x1E, 0x88}} +gHdAudioConfigGuid =3D {0x7EB3CE7E, 0x82E0, 0x4CD7, {0xBD, 0xE5, 0xB2, 0= xBF, 0x4E, 0x91, 0xC3, 0x4C}} +gHdAudioDxeConfigGuid =3D {0x22EFC2DE, 0x66EB, 0x412D, {0x97, 0x17, 0xE7= , 0x7A, 0xA1, 0x4E, 0x87, 0x76}} +gInterruptConfigGuid =3D {0x09A2B815, 0xBE29, 0x45EF, {0xBF, 0xBF, 0x58,= 0xEA, 0xAC, 0x5E, 0x29, 0x78}} +gIshPreMemConfigGuid =3D {0x7C24E649, 0xC1F0, 0x4CF9, {0x87, 0x96, 0xE7,= 0xA0, 0xEE, 0x34, 0x43, 0xF8}} +gIshConfigGuid =3D {0x433AE2AA, 0xC5A6, 0x46ED, {0x94, 0x19, 0x1E, 0x5D,= 0xB8, 0x1C, 0x57, 0x40}} +gGbeConfigGuid =3D {0x4B2DE99E, 0x7517, 0x4D04, {0x8C, 0x02, 0xF1, 0x1A,= 0x59, 0x2B, 0x14, 0x2F}} +gTsnConfigGuid =3D {0x9E9A93CB, 0x0F4E, 0x4E56, {0x90, 0x2D, 0x6C, 0x76,= 0xDE, 0x90, 0xF7, 0x71}} +gLockDownConfigGuid =3D {0x8A838E0A, 0xA639, 0x46F0, {0xA9, 0xCE, 0x70, = 0xC4, 0x85, 0xFB, 0xA8, 0x0D}} +gP2sbConfigGuid =3D {0x2474DCB8, 0x4BB4, 0x49DA, {0x87, 0x83, 0x7C, 0xD3= , 0xD3, 0x85, 0xFF, 0x07}} +gPmConfigGuid =3D {0x93826157, 0xDC85, 0x4E34, {0xAE, 0xD9, 0x6E, 0xA1, = 0x0D, 0xF9, 0xE3, 0xA7}} +gScsConfigGuid =3D {0xF4DE6D52, 0xB5C9, 0x48C0, {0xA0, 0x4A, 0x68, 0x54,= 0x20, 0x94, 0x05, 0xD0}} +gScsInfoHobGuid =3D {0x94C5E85B, 0xAA6D, 0x481D, {0x8B, 0xBD, 0x54, 0xAA, = 0xE2, 0x99, 0x78, 0xB2}} +gSdCardConfigGuid =3D {0xD6A3038E, 0x50AE, 0x44B0, {0x93, 0xE2, 0xF7, 0x93= , 0xF5, 0x90, 0x50, 0x27}} +gEmmcConfigGuid =3D {0xE0C6FB5D, 0x5696, 0x47F3, {0x84, 0xE8, 0xCC, 0x6C, = 0x68, 0xA4, 0xB2, 0x1D}} +gUfsConfigGuid =3D {0x3AF25C55, 0x76B4, 0x4367, {0x85, 0xEF, 0x9D, 0x51, 0= x2F, 0x2F, 0x8F, 0xA7}} +gEmmcDxeConfigGuid =3D {0x59440AA6, 0xEB45, 0x4E36, {0xBC, 0x90, 0xBE, 0xF= 9, 0x0C, 0xB0, 0xC8, 0x18}} +gSerialIoConfigGuid =3D {0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA, = 0x09, 0xE5, 0x78, 0x3A, 0xDB}} +gSerialIrqConfigGuid =3D {0x251701E7, 0xE266, 0x4623, {0x99, 0x68, 0x73,= 0x8C, 0xD2, 0x23, 0x10, 0x96}} +gSpiConfigGuid =3D {0x150360EF, 0x99BE, 0x4E43, {0x94, 0xBB, 0xBD, 0x40,= 0x26, 0xCA, 0x34, 0x57}} +gEspiConfigGuid =3D {0x60FBF3B8, 0x96D4, 0x4187, {0x84, 0x9E, 0xAA, 0xF7= , 0x5C, 0x4B, 0xE1, 0xE3}} +gThermalConfigGuid =3D {0x4416506D, 0x1197, 0x4722, {0xA5, 0xB4, 0x46, 0= x11, 0xF9, 0x23, 0x9E, 0xAE}} +gUsbConfigGuid =3D {0xB2DA9CCD, 0x6A8C, 0x4BB6, {0xB3, 0xE6, 0xCD, 0xFB,= 0xB7, 0x66, 0x8B, 0xDE}} +gUsb2PhyConfigGuid =3D {0x576C1134, 0x2E0C, 0xCB7D, {0xCD, 0x3F, 0xAC, 0= x68, 0x2D, 0xAE, 0xD3, 0xF2}} +gUsb3HsioConfigGuid =3D {0xF8AFC238, 0xF176, 0x12CE, {0xBE, 0xF4, 0x69, = 0xF9, 0xB1, 0xAC, 0x40, 0xD5}} +gPchPcieStorageDetectHobGuid =3D {0xC682F3F4, 0x2F46, 0x495E, {0x98, 0xAA,= 0x43, 0x14, 0x4B, 0xA5, 0xA4, 0x85}} +gCnviConfigGuid =3D {0xE53EBEF7, 0x103D, 0x4A70, {0x9B, 0x6A, 0x73, 0xEE, = 0x5F, 0x4C, 0x8D, 0xF5}} +gHsioConfigGuid =3D {0xE53EBEE7, 0x103D, 0x4A71, {0x9B, 0x6A, 0x74, 0xEE, = 0x5F, 0x4C, 0x8D, 0xF5}} +gPchRstHobGuid =3D {0x4ECA680C, 0x660D, 0x48F8, {0xAA, 0xD8, 0x94, 0xD6, = 0x56, 0x10, 0xF9, 0x86}} +gPchInfoHobGuid =3D {0x99FD5E18, 0xE262, 0x4E6A, {0x82, 0x66, 0x77, 0xD0= , 0x36, 0x5F, 0xD6, 0x3E}} +gGpioDxeConfigGuid =3D {0x06985984, 0xAFA3, 0x429C, {0x80, 0xCD, 0x69, 0= x43, 0xF3, 0x38, 0x31, 0x4D}} +gFivrConfigGuid =3D {0x68EE8BD4, 0x05F2, 0x4656, {0xAE, 0xE4, 0xAD, 0x10= , 0xC7, 0x22, 0xC3, 0x4F}} +gThcConfigGuid =3D {0x1B318AD1, 0xAA0D, 0x4764, {0x99, 0xFD, 0xBB, 0x2B,= 0xF4, 0x7F, 0x7E, 0xD6}} +gIehConfigGuid =3D {0x42C4D7F3, 0x981D, 0x4475, {0xA2, 0xAE, 0xAD, 0xCD,= 0xD5, 0xCE, 0x87, 0x1E}} +gRtcConfigGuid =3D {0x0E9259B8, 0x3DDE, 0x40C7, {0xAA, 0x5F, 0x94, 0x82,= 0x9A, 0x86, 0x8F, 0xAF}} +gCnviConfigGuid =3D {0xa660970e, 0x511b, 0x46bb, {0xa7, 0xb8, 0xec, 0xdd,= 0xf5, 0xe2, 0x2d, 0x73}} +gGpioCheckConflictHobGuid =3D {0x5603f872, 0xefac, 0x40ae, {0xb9, 0x7e, 0x= 13, 0xb2, 0xf8, 0x07, 0x80, 0x21}} +gPsfConfigGuid =3D {0x49B12CF6, 0x0A56, 0x4B9F, {0xA8, 0x4C, 0xF5, 0x7D,= 0x21, 0x23, 0x8C, 0x77}} +gHybridStorageConfigGuid =3D {0x265CE069, 0xD8CF, 0x48BE, {0xAE, 0x12, 0x0= 2, 0x4C, 0x25, 0x12, 0xFA, 0xF8}} +gHybridStorageHobGuid =3D {0xFF91F620, 0x069E, 0x4191, {0x83, 0x73, 0x11, = 0x60, 0x9F, 0x24, 0x90, 0xEB}} +gAdrConfigGuid =3D {0x5B36A07C, 0x3BBF, 0x4D53, {0x8A, 0x2D, 0xE1, 0xCF, 0= x97, 0x39, 0x0C, 0x65}} +gSpiConfigGuid =3D {0xD61A6A07, 0xAD25, 0xBFC2, {0x8C, 0x60, 0xD0, 0xD1, 0= xF4, 0x13, 0x14, 0xBC}} + +## +## Fusa +## +gFusaConfigGuid =3D {0xF9225896, 0xA9C8, 0x4543, {0xBA, 0x9E, 0x53, 0x32,= 0xD7, 0xBF, 0x8C, 0x2B}} +gSiFusaInfoGuid =3D {0xcc7876ba, 0xee7b, 0x4bd4, {0x99, 0x4b, 0x7e, 0xc9, = 0x74, 0xc9, 0xd8, 0x43}} + +## +## SecurityPkg +## +## GUID used to "Tcg2PhysicalPresence" variable and "Tcg2PhysicalPresenceF= lags" variable for TPM2 request and response. +# Include/Guid/Tcg2PhysicalPresenceData.h +gEfiTcg2PhysicalPresenceGuid =3D { 0xaeb9c5c1, 0x94f1, 0x4d02, { = 0xbf, 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }} +gEfiTrEEPhysicalPresenceGuid =3D {0xf24643c2, 0xc622, 0x494e, {0= x8a, 0x0d, 0x46, 0x32, 0x57, 0x9c, 0x2d, 0x5b}} +gTcoWdtHobGuid =3D { 0x3e405418, 0x0d8c, 0x4f1a, { = 0xb0, 0x55, 0xbe, 0xf9, 0x08, 0x41, 0x46, 0x8d }} + +## +## UEFI Variable Support (Direct SPI and UFS) +## +gCseVariableStoragePpiInstanceGuid =3D { 0x9513730d, 0x06ce, 0x4cf= 6, { 0x9d, 0x95, 0xb0, 0x76, 0x31, 0xbc, 0xd5, 0xa9}} +gFvbVariableStoragePpiInstanceGuid =3D { 0x5067b88a, 0xaa37, 0x414= d, { 0xa3, 0xca, 0xc8, 0x37, 0xfc, 0xec, 0xd6, 0xf3}} +gCseVariableStorageProtocolInstanceGuid =3D { 0x5d5ede0b, 0x5d93, 0x4aa= e, { 0xa8, 0xec, 0x08, 0x41, 0xd0, 0x53, 0x85, 0xc4}} +gFvbVariableStorageProtocolInstanceGuid =3D { 0xe98252e8, 0xf209, 0x4ef= 5, { 0xab, 0x7e, 0x12, 0x69, 0x45, 0x14, 0x47, 0xbe}} +gPeiVariableCacheHobGuid =3D { 0x35212b29, 0x128a, 0x475= 4, { 0xb9, 0x96, 0x62, 0x45, 0xcc, 0xa8, 0xa0, 0x66}} +gCseVariableStorageSecurePreMemoryDataGuid =3D { 0xa1749e1e, 0x8ce1, 0x431= 0, { 0xbd, 0x3f, 0x64, 0xc9, 0x01, 0xc6, 0x13, 0xc2}} +gCseVariableStorageGeneralDataAreaGuid =3D { 0x6d7a6128, 0x685b, 0x4f7= 5, { 0x87, 0x87, 0xba, 0x93, 0x08, 0x60, 0x75, 0x0c}} +gCseVariableStorageFileSystemGuid =3D { 0xdb798aca, 0x3533, 0x41c= 7, { 0x9a, 0x98, 0x00, 0x31, 0x1b, 0x66, 0x0a, 0x15}} +gBugCheckVariableGuid =3D { 0xba57e015, 0x65b3, 0x4c3= c, { 0xb2, 0x74, 0x65, 0x91, 0x92, 0xf6, 0x99, 0xe3}} + +## +## PreMem Performance +## +gPerfPchPrePolicyGuid =3D {0x3112356F, 0xCC77, 0x4E82, {0x86, 0xD5, 0x= 3E, 0x25, 0xEE, 0x81, 0x92, 0xA4}} +gPerfSiValidateGuid =3D {0x681F96E6, 0xF9CF, 0x464D, {0x97, 0x9A, 0x= B1, 0x11, 0x33, 0xDE, 0x37, 0xA9}} +gPerfPchValidateGuid =3D {0xD0FF37D6, 0xA569, 0x4058, {0xB3, 0xDA, 0x= 29, 0x0B, 0x38, 0xC5, 0x32, 0x25}} +gPerfAmtValidateGuid =3D {0x9E949422, 0x4A7A, 0x4E41, {0xB0, 0xAB, 0x= 3C, 0x0D, 0x88, 0x0A, 0x00, 0xFF}} +gPerfCpuValidateGuid =3D {0xB760CFCC, 0xDEEF, 0x4C7E, {0x99, 0x5B, 0x= ED, 0xFE, 0xF2, 0x23, 0xB2, 0x09}} +gPerfMeValidateGuid =3D {0x8CF7A498, 0x588D, 0x4D39, {0xBD, 0xAC, 0x= 51, 0x0C, 0x31, 0xAF, 0x45, 0xD0}} +gPerfSaValidateGuid =3D {0xA73B382B, 0x62D4, 0x4A19, {0xBB, 0xF9, 0x= 09, 0x3E, 0xC5, 0xA5, 0x93, 0x11}} +gPerfHeciPreMemGuid =3D {0xD815D922, 0x4994, 0x40B3, {0x97, 0xCC, 0x= 07, 0xF3, 0x7D, 0x42, 0xE7, 0x97}} +gPerfPchPreMemGuid =3D {0xBB73E2B1, 0xB9FD, 0x4A80, {0xB8, 0x1A, 0x= 52, 0x39, 0xE9, 0x4D, 0x06, 0x2E}} +gPerfCpuPreMemGuid =3D {0xAC5FCBC6, 0x084D, 0x445D, {0xB3, 0xF3, 0x= CA, 0x16, 0xDE, 0xE9, 0xBB, 0x47}} +gPerfMePreMemGuid =3D {0x6051338E, 0x0FFA, 0x40F7, {0xAF, 0xEF, 0x= AB, 0x86, 0x7A, 0x38, 0xCC, 0xF3}} +gPerfAmtPreMemGuid =3D {0xDB732D50, 0x9BB8, 0x489A, {0xA1, 0xD1, 0x= DD, 0xD2, 0x16, 0x1D, 0x72, 0xB8}} +gPerfAmtPostMemGuid =3D {0x0329D610, 0x4269, 0xD28F, {0x61, 0xBF, 0x= B9, 0xA2, 0xD9, 0xFA, 0x96, 0x93}} +gPerfSaPreMemGuid =3D {0x76F18BDA, 0x2195, 0x4FB6, {0x9A, 0x94, 0x= 0E, 0x0B, 0xAC, 0xDE, 0xEC, 0xAB}} +gPerfEvlGuid =3D {0x8221518B, 0xAC19, 0x4E32, {0xAB, 0x5F, 0x= 00, 0x47, 0x0A, 0x50, 0x69, 0x40}} +gPerfMemGuid =3D {0x2B57B316, 0x5CF7, 0x4847, {0xB0, 0x76, 0x= 6B, 0x5D, 0x23, 0xC3, 0xAA, 0x3E}} + +## +## PostMem Performance +## +gPerfPchPostMemGuid =3D {0x70B67A99, 0x5556, 0x4315, {0xB3, 0x05, 0x= D5, 0xDC, 0x4A, 0x35, 0x63, 0x70}} +gPerfSaPostMemGuid =3D {0x9FF0CE92, 0x883F, 0x43DC, {0x8A, 0x07, 0x= E0, 0xCB, 0x6D, 0x56, 0x7D, 0xE0}} +gPerfS3CpuInitPostMemGuid =3D {0x976262C2, 0xD202, 0x4D12, {0x82, 0xAD, 0x= F4, 0xA9, 0x8F, 0x9B, 0x96, 0x01}} +gPerfSaSecLockPostMemGuid =3D {0x272AC110, 0x0B60, 0x4D07, {0xA5, 0x58, 0x= 6D, 0x73, 0xE2, 0x43, 0x85, 0x95}} +gPerfCpuStrapPostMemGuid =3D {0x8EF4372B, 0x68F0, 0x4957, {0xBC, 0x4D, 0x= 7E, 0x5C, 0xFE, 0xDA, 0xB6, 0x3E}} +gPerfMpPostMemGuid =3D {0xA59BAC5B, 0xC6A4, 0x4AEB, {0x84, 0x32, 0x= 7A, 0x8B, 0x6B, 0x68, 0x5F, 0x37}} +gPerfCpuPostMemGuid =3D {0xE2FE5ED3, 0x1417, 0x451A, {0x95, 0xC9, 0x= D0, 0xB2, 0xB9, 0x7B, 0xE0, 0x54}} +gPerfSaResetPostMemGuid =3D {0xBE152BEE, 0xFD19, 0x4274, {0xA8, 0xBA, 0x= FB, 0x31, 0x42, 0xB5, 0xB5, 0xC3}} +gPerfCpuPowerMgmtGuid =3D {0x9ED307D6, 0x4AEB, 0x44A9, {0x9B, 0x11, 0x= D8, 0x21, 0x84, 0x9A, 0xCB, 0xF7}} +gPerfMePostMemGuid =3D {0x2CC8626D, 0x3387, 0x4817, {0xAB, 0xF6, 0x= 86, 0x9A, 0xF5, 0xF0, 0x51, 0xAA}} +gPerfHdaPostMemGuid =3D {0xB31883B7, 0x5A05, 0x4040, {0x40, 0x80, 0x= 66, 0x8D, 0x29, 0x13, 0xD7, 0x84}} + +## +## Dp-In Guid +## +## Include/DpInDataHob.h +gDpInHobGuid =3D {0x3e110a83, 0xb94b, 0x4648, {0xa2, 0x26, 0x50, 0x9b, 0xd= 5, 0x55, 0xe3, 0x6b}} +## Include/ConfigBlock/Tcss/DpInPreMemConfig.h +gDpInPreMemConfigGuid =3D {0x80c14ba, 0xcc84, 0x4746, {0xbf, 0x6b, 0xd1, 0= xf1, 0x8e, 0xaa, 0xe8, 0x35}} + +[Protocols.common.Private] +## +## SA +## +gSaIotrapSmiProtocolGuid =3D { 0x1861e089, 0xcaa3, 0x473e, { 0x84, 0x32= , 0xdc, 0x1f, 0x94, 0xc6, 0xc1, 0xa6 }} +gCpuPcieIoTrapProtocolGuid =3D { 0xda904080, 0x33ab, 0x48ca, { 0x97, 0x5b= , 0x5f, 0x2f, 0x23, 0x8a, 0x41, 0xb4 }} + +gPchPcieIoTrapProtocolGuid =3D { 0xd66a1cf, 0x79ad, 0x494b, { 0x97, = 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }} + +[Protocols] +## +## MdeModulePkg +## +gEfiSmmVariableProtocolGuid =3D {0xed32d533, 0x99e6, 0x4209, {0x9c, 0xc0= , 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7}} +gEdkiiPlatformSpecificResetFilterProtocolGuid =3D { 0x695d7835, 0x8d47, 0= x4c11, { 0xab, 0x22, 0xfa, 0x8a, 0xcc, 0xe7, 0xae, 0x7a } } +gEdkiiPlatformSpecificResetHandlerProtocolGuid =3D { 0x2df6ba0b, 0x7092, 0= x440d, { 0xbd, 0x4, 0xfb, 0x9, 0x1e, 0xc3, 0xf3, 0xc1 } } + +## +## SystemAgent +## +gBdatAccessGuid =3D {0x9477482c, 0x8717, 0x4725, {0x98, 0= x28, 0x7b, 0xd8, 0xc9, 0xa3, 0x75, 0x6a}} +gIgdOpRegionProtocolGuid =3D {0x9e67aecf, 0x4fbb, 0x4c84, {0x99, 0= xa5, 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}} +gMemInfoProtocolGuid =3D {0xd4d2f201, 0x50e8, 0x4d45, {0x8e, 0= x5, 0xfd, 0x49, 0xa8, 0x2a, 0x15, 0x69}} +gSaPolicyProtocolGuid =3D {0xc6aa1f27, 0x5597, 0x4802, {0x9f, 0= x63, 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}} +gSaNvsAreaProtocolGuid =3D {0x149a10a5, 0x9d06, 0x4c6b, {0xbe, 0= x44, 0x08, 0x92, 0xce, 0x20, 0x61, 0xac}} +gGopPolicyProtocolGuid =3D {0xec2e931b, 0x3281, 0x48a5, {0x81, 0= x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}} +gGen12PolicyProtocolGuid =3D {0x40f60ea0, 0x6c96, 0x4ed3, {0x96, 0= xe5, 0xba, 0x6f, 0x6d, 0x66, 0x28, 0x9f}} +gGen9PolicyProtocolGuid =3D {0xeaaed1ba, 0xf15c, 0x4112, {0xb5, 0= x82, 0x90, 0x63, 0xac, 0xa0, 0x7f, 0x06}} +gGopComponentName2ProtocolGuid =3D {0x651b7ebd, 0xce13, 0x41d0, {0x82, 0= xe5, 0xa0, 0x63, 0xab, 0xbe, 0x9b, 0xb6}} +gGopOverrideProtocolGuid =3D {0x4a89a16e, 0x67b8, 0x4429, {0x8c, 0= x47, 0x43, 0x67, 0x90, 0xf2, 0xf2, 0x69}} +gMemoryAddressEncodeDecodeProtocolGuid =3D {0x603df7ca, 0x1ba8, 0x4c12, {0= xa9, 0x8a, 0x49, 0x6d, 0xfe, 0x77, 0xeb, 0xdf}} + +## +## TBT +## +gITbtPolicyProtocolGuid =3D {0xb0563c42, 0x28ea, 0x40e6, {0x99, 0x8= 4, 0xd5, 0xbf, 0xf8, 0xb0, 0x40, 0x56}} +gITbtNvsAreaProtocolGuid =3D {0xdabf85bd, 0xfbdc, 0x4ed2, {0xb1, 0x0= d, 0xc9, 0x08, 0xd0, 0x8c, 0xee, 0xe8}} +gDisableITbtBmeProtocolGuid =3D {0x89a9adc3, 0x9b7c, 0x4b53, {0x82, = 0xbf, 0x78, 0x72, 0x6b, 0x91, 0x4f, 0x9f}} + +## +## Cpu +## +gCpuInfoProtocolGuid =3D {0xe223cf65, 0xf6ce, 0x4122, {0xb3, 0xaf, 0x4b,= 0xd1, 0x8a, 0xff, 0x40, 0xa1}} +gSmmBiosGuardProtocolGuid =3D {0x17565311, 0x4b71, 0x4340, {0x88, 0xaa, = 0xdc, 0x9f, 0x44, 0x22, 0xe5, 0x3a}} +gCpuNvsAreaProtocolGuid =3D {0xb9cf3f43, 0xbe3e, 0x4e45, {0xa0, 0xbe, 0x= 1a, 0x4, 0x89, 0xdf, 0x1a, 0xc9}} +gDxeCpuPolicyProtocolGuid =3D {0x8282b977, 0x22f9, 0x4134, {0x99, 0x43, = 0x7b, 0xcc, 0x5f, 0x40, 0x33, 0x52}} +gBiosGuardNvsAreaProtocolGuid =3D {0x5df588da, 0x991e, 0x4a7f, {0x80, 0x= 51, 0x70, 0xc7, 0x12, 0xb7, 0xba, 0xb0}} +gSmmResourceConfigProtocolGuid =3D {0xA37FC2D2, 0x822D, 0x4A63, {0x9C, 0x4= 2, 0xBE, 0xB1, 0xD6, 0xEE, 0x85, 0x39}} + +## +## Me +## +gActiveManagementProtocolGuid =3D {0xd25dc167, 0xeb6a, 0x432d, {0x65, = 0x91, 0xbf, 0x80, 0x29, 0xb0, 0x05, 0xbb}} +gAlertStandardFormatProtocolGuid =3D {0x45de9920, 0xcd54, 0x446a, {0xa0, = 0x3c, 0x22, 0xe6, 0xfb, 0xb4, 0x51, 0xe4}} +gHeciProtocolGuid =3D {0x3c7bc880, 0x41f8, 0x4869, {0xae, = 0xfc, 0x87, 0x0a, 0x3e, 0xd2, 0x82, 0x99}} +gHeciFlowProtocolGuid =3D {0x1498d127, 0x123c, 0x4e52, {0x84, = 0x00, 0xcc, 0x3c, 0x9f, 0x79, 0xc4, 0x0e}} +gMebxProtocolGuid =3D {0x01ab1829, 0xcecd, 0x4cfa, {0xa1, = 0x8c, 0xea, 0x75, 0xd6, 0x6f, 0x3e, 0x74}} +gDxeMePolicyGuid =3D {0xa0b5dc52, 0x4f34, 0x3990, {0xd4, = 0x91, 0x10, 0x8b, 0xe8, 0xba, 0x75, 0x42}} +gMeInfoProtocolGuid =3D {0x7523c8e4, 0x4fbe, 0x9661, {0x29, = 0x96, 0x14, 0x97, 0xff, 0x36, 0x2f, 0x3b}} +gPlatformMeHookProtocolGuid =3D {0xbc52476e, 0xf67e, 0x4301, {0xb2, = 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2}} +gMeNvsAreaProtocolGuid =3D {0x3bffecfd, 0xd75f, 0x4975, {0xb8, = 0x88, 0x39, 0x02, 0xbd, 0x69, 0x00, 0x2b}} +gJhiProtocolGuid =3D {0xccba3051, 0xa574, 0x4f9d, {0x96, = 0xf4, 0xec, 0x0d, 0x4a, 0x87, 0xbc, 0x5a}} +gIntegratedTouchHidProtocolGuid =3D {0x3d0479c1, 0x6b19, 0x4191, {0xb8, = 0x09, 0x60, 0x08, 0xdd, 0x07, 0x97, 0x55}} +gIntegratedTouchProtocolGuid =3D {0x2b12e46f, 0x3c24, 0x47ff, {0x8b, = 0x89, 0xc0, 0x60, 0x2c, 0x1c, 0x61, 0x42}} +gMeEopDoneProtocolGuid =3D {0x8d9b3387, 0x73db, 0x456f, {0x88, = 0x9d, 0x6f, 0xfe, 0x90, 0x82, 0x64, 0x09}} +gMeSendEopInFspProtocolGuid =3D {0xcecdba92, 0x76c6, 0x4063, {0xaa, = 0x6b, 0x19, 0xfc, 0x60, 0x5c, 0x70, 0xff}} + +gHeciAccessProtocolGuid =3D {0x3a5aab32, 0xd5a7, 0x4ce8, {0x88, 0= xe2, 0xed, 0x8f, 0x7b, 0x43, 0x23, 0x9d}} +gHeciTransportProtocolGuid =3D {0x9fc932b9, 0x8851, 0x43f7, {0x8a, 0= x58, 0xa8, 0xd9, 0x04, 0x01, 0xcd, 0x78}} +gHeciControlProtocolGuid =3D {0xd86381d8, 0xff7e, 0x462e, {0x9b, 0= x55, 0x02, 0x0a, 0x64, 0x1b, 0xe3, 0x4f}} +gHeciAccessSmmProtocolGuid =3D {0x5da6182c, 0xf679, 0x49eb, {0x96, 0= xf5, 0xe6, 0x24, 0x9b, 0x54, 0x0b, 0x96}} +gHeciTransportSmmProtocolGuid =3D {0xf5f7b292, 0xbb38, 0x4e59, {0xa1, 0= x6e, 0x0f, 0x27, 0x15, 0xd4, 0xb7, 0xf4}} +gHeciControlSmmProtocolGuid =3D {0x7e1e508d, 0x7def, 0x4d69, {0xa9, 0= xb3, 0xa5, 0x23, 0xe8, 0x48, 0xc6, 0x98}} + +## +## Amt +## +gAmtSaveMebxProtocolGuid =3D {0x86682c04, 0xea42, 0x49e5, {0x96, = 0x81, 0xe3, 0x32, 0xaa, 0xb0, 0x9e, 0xd7}} +gDxeAmtPolicyGuid =3D {0x6725e645, 0x4a7f, 0x9969, {0x82, = 0xec, 0xd1, 0x87, 0x21, 0xde, 0x5a, 0x57}} +gAmtReadyToBootProtocolGuid =3D {0xcc9d5c0b, 0x9010, 0x45f1, {0x99, = 0x3c, 0x83, 0x27, 0x67, 0xf1, 0x67, 0x77}} +gMeSmbiosTablesUpdateProtocolGuid =3D {0x5054ee06, 0x4ce0, 0x4acc, {0x9a, = 0x80, 0xdf, 0x73, 0xbf, 0xa5, 0x38, 0xdd}} +gOneClickRecoveryProtocolGuid =3D {0x93598eac, 0xc62b, 0x4dbb, {0x96, = 0x76, 0xe0, 0x5e, 0x8c, 0xc3, 0x84, 0x44}} + +## +## PCH +## +gThcProtocolGuid =3D {0x00860921, 0x7B9B, 0x4EA8, {0xAD, 0x23, 0x3C, 0xCA= , 0x33, 0x9E, 0x7D, 0xFE}} +gPchSpiProtocolGuid =3D {0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0x2= 6, 0x9d, 0xe, 0xf3, 0x4a}} +gWdtProtocolGuid =3D {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0x5= b, 0xe6, 0xcf, 0x09, 0xb1}} +gPchSerialIoUartDebugInfoProtocolGuid =3D {0x2fd2b1bd, 0x0387, 0x4ec6, {= 0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6}} +gEfiSmmSmbusProtocolGuid =3D {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0= x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}} +gPchSmmSpiProtocolGuid =3D {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0xdf= , 0x1, 0x9d, 0x72, 0xc7, 0xe1}} +gPchSmmIoTrapControlGuid =3D {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6, 0= x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}} +gPchTcoSmiDispatchProtocolGuid =3D {0x9e71d609, 0x6d24, 0x47fd, {0xb5, 0= x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}} +gPchPcieSmiDispatchProtocolGuid =3D {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f, = 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}} +gPchAcpiSmiDispatchProtocolGuid =3D {0xd52bb262, 0xf022, 0x49ec, {0x86, = 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}} +gPchSmiDispatchProtocolGuid =3D {0xE6A81BBF, 0x873D, 0x47FD, {0xB6, 0xBE= , 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}} +gPchNvsAreaProtocolGuid =3D {0x2e058b2b, 0xedc1, 0x4431, {0x87, 0xd9, 0x= c6, 0xc4, 0xea, 0x10, 0x2b, 0xe3}} +gPchEspiSmiDispatchProtocolGuid =3D {0xB3C14FF3, 0xBAE8, 0x456C, {0x86, = 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}} +gPchSmmPeriodicTimerControlGuid =3D {0x6906E93B, 0x603B, 0x4A0F, {0x86, = 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}} +gIoTrapExDispatchProtocolGuid =3D {0x5B48E913, 0x707B, 0x4F9D, {0xAF, 0x= 2E, 0xEE, 0x03, 0x5B, 0xCE, 0x39, 0x5D}} +gPchPolicyProtocolGuid =3D {0x543d5c93, 0x6a28, 0x4513, {0x85, = 0x9a, 0x82, 0xa7, 0xb9, 0x12, 0xcb, 0xbe}} +gScsEmmcSoftwareTuningProtocolGuid =3D {0x972215b2, 0x9616, 0x4de4, {0xa9,= 0x75, 0xb0, 0x74, 0x3e, 0xe1, 0x78, 0x54}} + +## +## Hsti +## +## HstiSiliconDxe Driver Entry Point +gHstiProtocolGuid =3D { 0x1b05de41, 0xc93b, 0x4bb4, { 0xad, 0x47, 0x2a, 0x= 78, 0xac, 0xf, 0xc9, 0xe4 }} +## Handler to gather and publish HSTI results on ReadyToBootEvent +gHstiPublishCompleteProtocolGuid =3D {0x0f500be6, 0xece4, 0x4ed8, { 0x90,= 0x81, 0x9a, 0xa9, 0xa5, 0x23, 0xfb, 0x7b}} +gEfiAdapterInformationProtocolGuid =3D { 0xE5DD1403, 0xD622, 0xC24E, {0x84= , 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 }} + +## +## Silicon Policy +## +## Include/Protocol/SiPolicyProtocol.h +gDxeSiPolicyProtocolGuid =3D { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94, 0= x4e, 0x52, 0x10, 0x96, 0x69, 0x5e }} + +## +## DGR +## +gEfiSpaLogOutputProtocolGuid =3D { 0x1d10d46b, 0x0306, 0x454a, { 0x90, 0x8= c, 0x93, 0x65, 0xb3, 0x8a, 0x90, 0x26 }} + +[Ppis.common.Private] +gPchHsioChipsetInitSusTblDataPpiGuid =3D { 0x97ed4e5d, 0x01a5, 0x4a3c, { 0= xb7, 0xe9, 0x1a, 0x4e, 0xa3, 0xdd, 0x23, 0xce }} +gHybridStorageCfgPpiGuid =3D {0x8557e481, 0xc00e, 0x4929, {0xb4, 0x53, 0xf= 6, 0xc2, 0x53, 0x79, 0xb0, 0x13}} + +[Ppis] +## +## MdeModulePkg +## +gPeiCapsulePpiGuid =3D {0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38, 0= x54, 0xd2, 0xe1, 0x32, 0x3d}} +gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7= , 0x43, 0x05, 0xce, 0x74, 0xc5}} +gEdkiiPlatformSpecificResetFilterPpiGuid =3D { 0x8c9f4de3, 0x7b90, 0x47ef,= { 0x93, 0x8, 0x28, 0x7c, 0xec, 0xd6, 0x6d, 0xe8 } } +gEdkiiPlatformSpecificResetNotificationPpiGuid =3D { 0xe09f355d, 0xdae8, 0= x4910, { 0xb1, 0x4a, 0x92, 0x78, 0xf, 0xdc, 0xf7, 0xcb } } +gEdkiiPlatformSpecificResetHandlerPpiGuid =3D { 0x75cf14ae, 0x3441, 0x49dc= , { 0xaa, 0x10, 0xbb, 0x35, 0xa7, 0xba, 0x8b, 0xab } } + +## +## SecurityPkg +## +gPeiTpmInitializedPpiGuid =3D {0xe9db0d58, 0xd48d, 0x47f6, {0x9c, 0x6e, = 0x6f, 0x40, 0xe8, 0x6c, 0x7b, 0x41}} +gPeiTpmInitializationDonePpiGuid =3D {0xa030d115, 0x54dd, 0x447b, { 0x90, = 0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}} +## +## Common +## +## Include/Ppi/SiPolicy.h +gSiPolicyPpiGuid =3D {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x8= 4, 0x8c, 0x5e, 0x86, 0x70}} +## Include/Ppi/SiPolicy.h +gSiPreMemPolicyPpiGuid =3D {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97,= 0xc1, 0x89, 0xd0, 0xab, 0x8d}} +gFspApiModePpiGuid =3D {0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5, = 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}} +## Silicon Initialization PPI is used to export End of Silicon init. +gEndOfSiInitPpiGuid =3D {0xE2E3D5D1, 0x8356, 0x4F96, {0x9C, 0x9E, = 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88}} +gEfiEndOfPeiSignal2PpiGuid =3D {0x22918381, 0xd018, 0x4d7c, {0x9d, 0x62, = 0xf5, 0xa5, 0x70, 0x1c, 0x66, 0x80}} +gFspTempRamExitPpiGuid =3D {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, = 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}} +gFspmArchConfigPpiGuid =3D {0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, = 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}} +gSiPreMemDefaultPolicyInitPpiGuid =3D {0xfec36242, 0xf8d8, 0x4b43, {0x87,= 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}} +gSiPreMemPolicyReadyPpiGuid =3D {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, = 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}} +gSiDefaultPolicyInitPpiGuid =3D {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef,= 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}} +gSiPolicyReadyPpiGuid =3D {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, = 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}} + +## +## UEFI Variable Support (Override Until BP1.5) +## +gEdkiiVariableStoragePpiGuid =3D { 0x90d915c5, 0xe4c1, 0x4da8, {0xa7, 0x= 6f, 0x9, 0xe5, 0x78, 0x91, 0x65, 0x48}} +gEdkiiVariableStorageSelectorPpiGuid =3D { 0x782546d1, 0x03ab, 0x41e4, {= 0xa0, 0x1d, 0x7a, 0x9b, 0x22, 0xba, 0x2e, 0x1e}} +gReadOnlyVariablePreMemoryDescriptorPpiGuid =3D { 0xbe136fc9, 0xc277, 0x= 4dd1, {0xbe, 0x42, 0xce, 0xf0, 0x9f, 0xf4, 0x3f, 0x55}} +gEfiReadyToInstallEndOfPei2PpiGuid =3D {0xeef72924, 0x2db2, 0x4569, { 0x86= , 0x3f, 0xd4, 0x86, 0xae, 0x7a, 0xe4, 0x12}} + +## +## SystemAgent +## +gSsaBiosCallBacksPpiGuid =3D {0x99b56126, 0xe16c, 0x4d9b, {0xbb, 0x71, 0= xaa, 0x35, 0x46, 0x1a, 0x70, 0x2f}} +gSsaBiosServicesPpiGuid =3D {0x55750d10, 0x6d3d, 0x4bf5, {0x89, 0xd8, 0= xe3, 0x5e, 0xf0, 0xb0, 0x90, 0xf4}} +gEnablePeiGraphicsPpiGuid =3D {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0, 0= x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}} +gPeiGraphicsFramebufferReadyPpiGuid =3D {0x590ad868, 0xb0b1, 0x4d20, {0x91= , 0xff, 0xc2, 0xa9, 0xd6, 0x88, 0x81, 0x94}} +gMrcMemoryInitDonePpiGuid =3D {0x0ff07255, 0x67c2, 0x456d, {0x9a, 0x95, 0= xc9, 0x16, 0x2c, 0x23, 0x86, 0x8d}} +## X Compatibility support PPI +gCompatibleMemoryInitPpiGuid =3D {0xca311f82, 0xf490, 0x4b12, {0x9e, 0xe1,= 0x2b, 0x66, 0xa3, 0x6c, 0x3e, 0xa}} +gVmdInitDonePpiGuid =3D {0x42a187c8, 0xca0a, 0x4750, {0x82, 0xfd,= 0xc9, 0xa0, 0xd5, 0x9, 0xfe, 0xd1}} + +## +## TwoLm +## +gMrcMemoryInitDonePpiGuid =3D { 0x598907f5, 0xd5fc, 0x435c, { 0x8a, 0x7f,= 0x53, 0xc5, 0xa4, 0xb5, 0x31, 0xc4}} + +## +## Nvdimm Cache Info +## +gNvdimmCachePpiGuid =3D { 0x1bbc5601, 0xe571, 0x4ae0, { 0xbc, 0x38, 0xb8,= 0x65, 0x0d, 0x50, 0x6f, 0x5b}} + +## +## Cpu +## +gPeiCachePpiGuid =3D {0x09be4bc2, 0x790e, 0x4dea, {0x8b, 0xdc, 0x38, 0x0= 5, 0x16, 0x98, 0x39, 0x44}} +gPeiTxtMemoryUnlockedPpiGuid =3D {0x38cdd10b, 0x767d, 0x4f6e, {0xa7, 0x4= 4, 0x67, 0xee, 0x1d, 0xfe, 0x2f, 0xa5}} +gPeiTxtReadyToRunMemoryInitPpiGuid =3D {0x9ecafd30, 0x29e2, 0x42f6, {0xba,= 0xf3, 0x8b, 0x7d, 0xb8, 0xfe, 0x1f, 0x22}} +gPeiReadyToInstallMpPpiGuid =3D { 0x1a266768, 0xfd43, 0x4e18, { 0xa8, 0x8a= , 0x35, 0xc7, 0x94, 0xc3, 0x91, 0x0e }} +## +## Me +## +gHeciPpiGuid =3D {0xd14319e2, 0x407a, 0x9580, {0x8d, 0xe5, 0x51, 0xa8, 0= xff, 0xc6, 0xd7, 0xd7}} +gMbpSensitivePpiGuid =3D {0xed7c9ce9, 0x5912, 0x4807, {0xec, 0x90, 0x22,= 0x18, 0xbc, 0x7b, 0xfc, 0x6c}} +gHeci3IntegratedTouchControllerGuid =3D {0x3e8d0870, 0x271a, 0x4208, {0x= 8e, 0xb5, 0x9a, 0xcb, 0x94, 0x02, 0xae, 0x04}} +gSiNvmOwnershipAcquiredPpiGuid =3D {0xe5db3d8c, 0xefa4, 0x4308, {0x9a, 0xa= b, 0x6b, 0x97, 0x81, 0x09, 0x98, 0xa0}} +gHeciAccessPpiGuid =3D {0x3a5aab32, 0xd5a7, 0x4ce8, {0x88, 0xe2, 0xed, 0x8= f, 0x7b, 0x43, 0x23, 0x9d}} +gHeciTransportPpiGuid =3D {0x9fc932b9, 0x8851, 0x43f7, {0x8a, 0x58, 0xa8, = 0xd9, 0x04, 0x01, 0xcd, 0x78}} +gHeciControlPpiGuid =3D {0xd86381d8, 0xff7e, 0x462e, {0x9b, 0x55, 0x02, 0= x0a, 0x64, 0x1b, 0xe3, 0x4f}} +gMeBeforeDidSentPpiGuid =3D {0xd497b143, 0xf3ef, 0x4192, {0xa8, 0xc5, 0x5e= , 0xf6, 0xcd, 0x6e, 0x4c, 0x87}} + +## +## PCH +## +gWdtPpiGuid =3D {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c, 0x= 21, 0x83, 0x57, 0x0d}} +gPchSpiPpiGuid =3D {0xdade7ce3, 0x6971, 0x4b75, {0x82, 0x5e, 0xe, 0xe0, = 0xeb, 0x17, 0x72, 0x2d}} +gPeiSmbusPolicyPpiGuid =3D {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb= 7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}} + +## +## TCSS +## +gTcssPeiInitDonePpiGuid =3D {0x5ad291b8, 0xace4, 0x416a, {0xb7, 0x50, 0x7,= 0x63, 0x59, 0xfc, 0xc1, 0x5b}} + +[LibraryClasses] +## @libraryclass +## Common +## +MmPciLib|Include/Library/MmPciLib.h + +## @libraryclass +## SampleCode +## +## CPU +## +CpuPolicyLib|Cpu/Include/Library/CpuPolicyLib.h + +## @libraryclass +## Me +## + +MeChipsetLib|Me/Include/Library/MeChipsetLib.h + +PeiMePolicyLib|Me/Include/Library/PeiMePolicyLib.h +PttHciLib|Me/Include/Library/PttHciLib.h +PttHeciLib|Me/Include/Library/PttHeciLib.h +## @libraryclass +## Pch +## +GpioLib|Include/Library/GpioLib.h +GpioLib|Include/Library/GpioNativeLib.h +PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h +EspiLib|Include/Library/PchEspiLib.h +GbeLib|Include/Library/GbeLib.h +GbeMdiLib|IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h +PchHsioLib|Pch/IncludePrivate/PchHsio.h +PchInfoLib|Pch/Include/Library/PchInfoLib.h +PchP2sbLib|Pch/Include/Library/PchP2sbLib.h +PchPcieRpLib|Pch/Include/Library/PchPcieRpLib.h +PchPcrLib|Pch/Include/Library/PchPcrLib.h +PchPolicyLib|Pch/Include/Library/PchPolicyLib.h +PchSbiAccessLib|Pch/IncludePrivate/Library/PchSbiAccessLib.h +SerialIoAccessLib|Include/Library/SerialIoAccessLib.h +DxePchPolicyLib|Pch/Include/Library/DxePchPolicyLib.h + +## @libraryclass +## Sa +## +DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h +SaPlatformLib|SystemAgent/Include/Library/SaPlatformLib.h +Include/Library/VoltageRegulatorCommands.h + +[PcdsFixedAtBuild] +## From MdeModulePkg.dec +## Progress Code for S3 Suspend start. +## PROGRESS_CODE_S3_SUSPEND_START =3D (EFI_SOFTWARE_SMM_DRIVER | (EFI_OE= M_SPECIFIC | 0x00000000)) =3D 0x03078000 +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart|0x03078000|UINT32|0x300= 01032 +## Progress Code for S3 Suspend end. +## PROGRESS_CODE_S3_SUSPEND_END =3D (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_= SPECIFIC | 0x00000001)) =3D 0x03078001 +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30001= 033 +## +## PcdNemCodeCacheBase is usally the same as PEI FV Base address, +## FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from PlatformPkg.fdf. +## +## Restriction: +## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase + PcdTemporaryRamSize) >= =3D 4K +## 2) PcdTemporaryRamBase >=3D 4G - 64M +## +gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20000009 +## +## NemCodeCacheSize is usally the same as PEI FV Size, +## FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf. +## +## Restriction: +## 1) PcdNemTotalCacheSize =3D NemCodeCacheSize + PcdTemporaryRamSize +## <=3D Maximun CPU NEM total size (Code + Data) +## =3D LLC size - 0.5M +## 2) PcdTemporaryRamSize <=3D Maximum CPU NEM data size +## =3D MLC size +## NOTE: The size restriction may be changed in next generation processor. +## Please refer to Processor BWG for detail. +## +gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x10000001 +gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002 +gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x00010028 +gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x00010029 +gSiPkgTokenSpaceGuid.PcdTopMemoryCacheSize|0x0|UINT32|0x0001002A +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|0xFFE60000|UINT32|0x30000004 +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32|0x30000005 +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0x00000060|UINT32|0x30000013 +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|0x00660000|UINT32|0x3000000= 6 +## +## The CPU Trace Hub's BARs base and size +## +gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarBase|0xfad00000|UINT32|0x30000007 +gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarSize|0x100000|UINT32|0x30000008 +gSiPkgTokenSpaceGuid.PcdCpuTraceHubSwBarBase|0xfc000000|UINT32|0x30000009 +gSiPkgTokenSpaceGuid.PcdCpuTraceHubSwBarSize|0x800000|UINT32|0x3000000A +gSiPkgTokenSpaceGuid.PcdCpuTraceHubRtitBarBase|0xfacfc000|UINT32|0x3000000= B +gSiPkgTokenSpaceGuid.PcdCpuTraceHubRtitBarSize|0x4000|UINT32|0x3000000C +gSiPkgTokenSpaceGuid.PcdCpuTraceHubFwBarBase|0xfae00000|UINT32|0x3000000D +gSiPkgTokenSpaceGuid.PcdCpuTraceHubFwBarSize|0x200000|UINT32|0x3000000E + +gSiPkgTokenSpaceGuid.PcdFspWrapperEnable |FALSE|BOOLEAN|0x3000000F +gSiPkgTokenSpaceGuid.PcdFspBinaryEnable|FALSE|BOOLEAN|0x30000010 +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0|UINT8|0x30000012 + +## +## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection +## value of the struct +## 0x00 EfiGcdAllocateAnySearchBottomUp +## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp +## 0x03 EfiGcdAllocateAnySearchTopDown +## 0x04 EfiGcdAllocateMaxAddressSearchTopDown +## +## below value should not using in this situation +## 0x05 EfiGcdMaxAllocateType : design for max value of struct +## 0x02 EfiGcdAllocateAddress : design for speccification address allocat= e +## +gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000 + +## +## Handshake register value driven to DMA controller PCIE venodr specific= configuration register from FW +## (LC/CM to host) +## +gSiPkgTokenSpaceGuid.PcdITbtToPcieRegister|0xEC|UINT8|0x40000003 +## +## Handshake register value driven from DMA controller PCIE venodr specif= ic configuration register to FW +## (HOST to LC/CM) +## +gSiPkgTokenSpaceGuid.PcdPcieToITbtRegister|0xF0|UINT8|0x40000004 + +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioBase|0x0000004000000000|UINT64|0x40000= 005 +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioSize|0x0000004000000000|UINT64|0x40000= 006 + +gSiPkgTokenSpaceGuid.PcdSmmEntryPointBinFile|{ 0x52, 0xce, 0xc8, 0xe0, 0x5= 1, 0x2b, 0xc2, 0x4c, 0xb3, 0xc7, 0xd2, 0x11, 0xa6, 0x25, 0xc1, 0xba }|VOID*= |0x40000007 +gSiPkgTokenSpaceGuid.PcdSpsBinFile|{ 0xEE, 0xE3, 0x34, 0x71, 0xA6, 0x7F, 0= x89, 0x44, 0x87, 0xA7, 0xAE, 0x38, 0x98, 0x4E, 0xAE, 0xD8 }|VOID*|0x4000000= 8 +gSiPkgTokenSpaceGuid.PcdSpsSmmEntryPointBinFile|{ 0x5B, 0x63, 0x7D, 0x7C, = 0x9C, 0x8B, 0x3C, 0x46, 0x9F, 0x7F, 0x91, 0xF6, 0x09, 0x06, 0x84, 0x8F }|VO= ID*|0x40000009 +gSiPkgTokenSpaceGuid.PcdSpaBinFile|{ 0xE1, 0x19, 0xB7, 0x7B, 0x2A, 0x53, 0= x40, 0x7B, 0xA3, 0x4C, 0xC4, 0xF9, 0xE2, 0x6C, 0x27, 0x74 }|VOID*|0x4000000= A +gSiPkgTokenSpaceGuid.PcdSpaSmmEntryPointBinFile|{ 0xD7, 0xAD, 0xB2, 0x9F, = 0x4D, 0x53, 0x4B, 0xA6, 0x8D, 0x55, 0x5D, 0x28, 0x91, 0x60, 0x10, 0x19 }|VO= ID*|0x4000000B + +## +## - DpIn Silicon Feature +## +# Note: PcdDpInEnable is Default Disable. Override it based on Platform/ = CPU +gSiPkgTokenSpaceGuid.PcdDpInEnable|FALSE|BOOLEAN|0x4000000C +# Note: For PcdMaxDpInExtPortSupported, we can have Maximum value of 0x08= . +# Please Don't exceed beyond that. As it will cause boundary overflow. +# Currently hadrware wise maximum Dp-In External Port supported is 4. +# And it will never exceed the value of 0x08. That's why we don't suppo= rt +# PcdMaxDpInExtPortSupported value more than 0x08 +gSiPkgTokenSpaceGuid.PcdMaxDpInExtPortSupported|0x4|UINT8|0x4000000D + +gSiPkgTokenSpaceGuid.VtdEngine1BaseAddeess|0xFED90000|UINT32|0x50000001 +gSiPkgTokenSpaceGuid.VtdEngine2BaseAddeess|0xFED92000|UINT32|0x50000002 +gSiPkgTokenSpaceGuid.VtdEngine3BaseAddeess|0xFED91000|UINT32|0x50000003 +gSiPkgTokenSpaceGuid.VtdEngine4BaseAddeess|0xFED84000|UINT32|0x50000004 +gSiPkgTokenSpaceGuid.VtdEngine5BaseAddeess|0xFED85000|UINT32|0x50000005 +gSiPkgTokenSpaceGuid.VtdEngine6BaseAddeess|0xFED86000|UINT32|0x50000006 +gSiPkgTokenSpaceGuid.VtdEngine7BaseAddeess|0xFED87000|UINT32|0x50000007 +## +## Those PCDs are used to control build process. +## +gSiPkgTokenSpaceGuid.PcdTraceHubEnable |FALSE|BOOLEAN|0xF000= 0001 +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |FALSE|BOOLEAN|0xF000= 0002 +gSiPkgTokenSpaceGuid.PcdAtaEnable |FALSE|BOOLEAN|0xF000= 0004 +gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE |BOOLEAN|0xF000= 0009 +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE|BOOLEAN|0xF000= 000B +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE |BOOLEAN|0xF000= 000C +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE|BOOLEAN|0xF000= 000F +gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE|BOOLEAN|0xF000= 0011 +gSiPkgTokenSpaceGuid.PcdJhiEnable |FALSE|BOOLEAN|0xF000= 0012 +gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable |FALSE|BOOLEAN|0xF000= 0013 +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE |BOOLEAN|0xF000= 0014 +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE |BOOLEAN|0xF000= 0015 +gSiPkgTokenSpaceGuid.PcdOverclockEnable |FALSE|BOOLEAN|0xF000= 0016 +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable |FALSE|BOOLEAN|0xF000= 0017 +gSiPkgTokenSpaceGuid.PcdSsaFlagEnable |FALSE|BOOLEAN|0xF000= 0018 +gSiPkgTokenSpaceGuid.PcdEvLoaderEnable |FALSE|BOOLEAN|0xF000= 0019 +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE |BOOLEAN|0xF000= 001A +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE |BOOLEAN|0xF000= 001B +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE |BOOLEAN|0xF000= 001C +gSiPkgTokenSpaceGuid.PcdGnaEnable |FALSE |BOOLEAN|0xF00= 0001E +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE |BOOLEAN|0xF000= 0020 +gSiPkgTokenSpaceGuid.PcdBiosGuardEnable |FALSE|BOOLEAN|0xF000= 0021 +gSiPkgTokenSpaceGuid.PcdSimicsEnable |FALSE|BOOLEAN|0xF000= 0022 +gSiPkgTokenSpaceGuid.PcdBdatEnable |FALSE|BOOLEAN|0xF000= 0023 +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE |BOOLEAN|0xF000= 0024 +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE |BOOLEAN|0xF000= 0025 +gSiPkgTokenSpaceGuid.PcdOcWdtEnable |FALSE|BOOLEAN|0xF000= 0029 +gSiPkgTokenSpaceGuid.PcdMinTreeEnable |FALSE|BOOLEAN|0xF000= 002A # To separate modules used in mininal source tree and advanced featur= es +gSiPkgTokenSpaceGuid.PcdBootGuardEnable |FALSE|BOOLEAN|0xF000= 0030 +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |FALSE|BOOLEAN|0xF000= 0033 +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE|BOOLEAN|0xF000= 0037 +gSiPkgTokenSpaceGuid.PcdBfxEnable |FALSE|BOOLEAN|0xF000= 003A +gSiPkgTokenSpaceGuid.PcdThcEnable |FALSE|BOOLEAN|0xF000= 003B + +gSiPkgTokenSpaceGuid.PcdPpamEnable |FALSE|BOOLEAN|0xF000= 003F +gSiPkgTokenSpaceGuid.PcdPsmiEnable |FALSE|BOOLEAN|0xF000= 0042 +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE |BOOLEAN|0xF000= 0043 +gSiPkgTokenSpaceGuid.PcdHybridStorageSupport |FALSE|BOOLEAN|0xF000= 0044 +gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE |BOOLEAN|0xF000= 0045 +gSiPkgTokenSpaceGuid.PcdTmeLibSupported |FALSE|BOOLEAN|0xF000= 0046 +gSiPkgTokenSpaceGuid.PcdAdlLpSupport |FALSE|BOOLEAN|0xF000= 0047 +gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable |FALSE|BOOLEAN|0xF000= 0048 +gSiPkgTokenSpaceGuid.PcdSpaEnable |FALSE|BOOLEAN|0xF000= 0049 + +## PCD for TraceHub +[PcdsDynamic, PcdsPatchableInModule] +## From MdeModulePkg.dec +## Default OEM ID for ACPI table creation, its length must be 0x6 bytes to= follow ACPI specification. +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034 +## Default OEM Table ID for ACPI table creation, it is "EDK2 ". +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|0x= 30001035 +## Default OEM Revision for ACPI table creation. +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x3000103= 6 +## Default Creator ID for ACPI table creation. +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037 +## Default Creator Revision for ACPI table creation. +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x300= 01038 +## ME HECI interface configuration +gMeConfigSpaceGuid.PcdHeciDumpsEnabled|TRUE|BOOLEAN|0x50000001 +gMeConfigSpaceGuid.PcdHeciTimeoutsEnabled|TRUE|BOOLEAN|0x50000002 + + +[PcdsFixedAtBuild, PcdsPatchableInModule] +## This value is used to set the base address of PCH devices +gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 +gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033 +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 + + +## Stack size in the temporary RAM. +## 0 means half of TemporaryRamSize. +gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x00010036 +## +## PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined = in SMBIOS, +## values 0-0x7F will be treated as disable FVI reporting. +## FVI structure uses it as SMBIOS OEM type to provide version information= . +## +gSiPkgTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037 +gSiPkgTokenSpaceGuid.PcdSaPciPrint|FALSE|BOOLEAN|0x00010039 +## +## SMBIOS defaults +## +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSocketDesignation|"U3E1"|VOID*|0x0001= 003a +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSerialNumber|"To Be Filled By O.E.M."= |VOID*|0x0001003b +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultAssetTag|"To Be Filled By O.E.M."|VOI= D*|0x0001003c +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultPartNumber|"To Be Filled By O.E.M."|V= OID*|0x0001003d + +## +## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices +## If PcdPciReservedMemLimit =3D0 Pci Reserved default MMIO Limit is 0xE= 0000000 else use PcdPciReservedMemLimit . +## +gSiPkgTokenSpaceGuid.PcdPciReservedIobase |0x2000 |UINT16|0x00010041 +gSiPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF |UINT16|0x00010042 +gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000 |UINT32|0x00010043 +gSiPkgTokenSpaceGuid.PcdPciDmaAbove4G |FALSE |BOOLEAN|0x00010044 +gSiPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace|FALSE |BOOLEAN|0x00010045 + +## +## Default 8MB TSEG for Release build BIOS when IED disabled (Also a defau= lt) +## +gSiPkgTokenSpaceGuid.PcdTsegSize|0x00800000|UINT32|0x00010046 +## +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM type = (0x80 to 0xFF) defined +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS report= ing. +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS information= . +## +gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047 + +## +## Maximum Address the AP Wakeup Buffer can start. +## +gSiPkgTokenSpaceGuid.PcdCpuApWakeupBufferMaxAddr|0x58000|UINT32|0x00010048 + +## +## Silicon Reference Code versions +## +##Revision:Weekly build number +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x33|UINT8|0x00010051 + +##Build[7:4]:Daily build number. +##Build[3:0]:Patch build number. + +## +## Temp MEM IO resource +## +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |2 |UINT8 |0x0= 0010053 +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |10 |UINT8 |0x0= 0010054 +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr |0xFE600000|UINT32|0x0= 0010055 +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemSize |0x00200000|UINT32|0x0= 0010056 + +## +## This PCD specifies the base address of the HPET timer. +## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and 0xFED= 03000 +## +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress |0xFED00000|UINT32|0x00010057 +## +## This PCD specifies the base address of the IO APIC. +## The acceptable values are 0xFECxx000. +## +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress |0xFEC00000|UINT32|0x00010058 + + +## +## VTD Base Addresses +## + +## Null-terminated string of the Version of Physical Presence interface su= pported by platform. +# @Prompt Version of Physical Presence interface supported by platform. +gSiPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|"1.3"|VOID*|0x0000= 0008 + +## This PCD specifies Master of TraceHub device +gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibMaster|0x0|UINT32|0x00011000 +## This PCD specifies Channel of TraceHub device +gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibChannel|0x0|UINT32|0x00011001 + + +[PcdsPatchableInModule, PcdsFixedAtBuild] +## This value is used to set the base address of MCH +gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFEDC0000|UINT64|0x00010030 +## 128KB window +gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x20000|UINT32|0x50000000 +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor |0x0A|UINT8|0x00010049 +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionValue |0x0000000800260020|UINT= 64|0x00010077 + +##Minor:the program that supported by same core generation. +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMinor |0x00|UINT8|0x00010050 + +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild |0x10|UINT8|0x00010052 +gSiPkgTokenSpaceGuid.PcdRegBarBaseAddress|0xFB000000|UINT32|0x00010059 +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] +## +## SerialIo Uart Configuration +## +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8 |0x00= 210001 # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8 |0x00= 210002 +gSiPkgTokenSpaceGuid.PcdSerialIoUartMode |2 |UINT8 |0x00= 210003 # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit +gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate |115200 |UINT32|0x00= 210004 # 0:Default, Max:6000000 +gSiPkgTokenSpaceGuid.PcdSerialIoUartParity |1 |UINT8 |0x00= 210008 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity +gSiPkgTokenSpaceGuid.PcdSerialIoUartDataBits |8 |UINT8 |0x00= 210009 # 0:Default, 5,6,7,8 +gSiPkgTokenSpaceGuid.PcdSerialIoUartStopBits |1 |UINT8 |0x00= 21000A # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits +gSiPkgTokenSpaceGuid.PcdSerialIoUartAutoFlow |0 |UINT8 |0x00= 21000B # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rt= s/Cts lines enabled; +gSiPkgTokenSpaceGuid.PcdSerialIoUartRxPinMux |0x0 |UINT32|0x00= 21000C # Pin muxing config for UART Rx pin +gSiPkgTokenSpaceGuid.PcdSerialIoUartTxPinMux |0x0 |UINT32|0x00= 210010 # Pin muxing config for UART Tx pin +gSiPkgTokenSpaceGuid.PcdSerialIoUartRtsPinMux |0x0 |UINT32|0x00= 210014 # Pin muxing config for UART Rts pin +gSiPkgTokenSpaceGuid.PcdSerialIoUartCtsPinMux |0x0 |UINT32|0x00= 210018 # Pin muxing config for UART Cts pin +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugMmioBase |0xFE036000 |UINT32|0x00= 21001C # PcdSerialIoUartMode =3D Enabled, need to assign MMIO Resource in S= EC/PEI Phase + +gSiPkgTokenSpaceGuid.PcdLpcUartDebugEnable |0x1 |UINT8 |0x00= 210026 # 0:Disable, 1:Enable +gSiPkgTokenSpaceGuid.PcdDebugInterfaceFlags |0x12 |UINT8 |0x00= 210027 # BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT= 2 - Not used. +gSiPkgTokenSpaceGuid.PcdSerialDebugLevel |0x3 |UINT8 |0x00= 210028 # {0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warni= ngs and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings Info an= d Verbose +gSiPkgTokenSpaceGuid.PcdIsaSerialUartBase |0x0 |UINT8 |0x00= 210029 # 0:0x3F8, 1:0x2F8 + +## UART Lib TimeOut +gSiPkgTokenSpaceGuid.PcdSerialIoUartTimeOut |1000000 |UINT32 |= 0x00210020 # Write TimeOut in Micro Seconds - 0 =3D disabbled, default 1 se= cond, +gSiPkgTokenSpaceGuid.PcdSerialIoUartLibSkipMmioCheck |FALSE |BOOLEAN|= 0x00210024 # If TRUE MMIO sanity checks are skipped + +## UART Dxe Driver IgnoreBaudRateSet +## TRUE - Blocks changing BaudRate, so that driver will not override UART'= s initial configuration. +## Required to support redirection on higher BaudRates. +## FALSE - Allows for UART settings to be changed through the Serial Io Pr= otocol +## +gSiPkgTokenSpaceGuid.PcdSerialIoUartDriverIgnoreBaudRateSet|FALSE|BOOLEAN|= 0x00210025 + +## +## SerialIo 2nd Uart Configuration +## +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartEnable |0 |UINT8 |0x002= 1002A # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartNumber |2 |UINT8 |0x002= 1002B +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMode |2 |UINT8 |0x002= 1002C # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartBaudRate |115200 |UINT32|0x002= 1002D # 0:Default, Max:6000000 +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartParity |1 |UINT8 |0x002= 10031 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartDataBits |8 |UINT8 |0x002= 10032 # 0:Default, 5,6,7,8 +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartStopBits |1 |UINT8 |0x002= 10033 # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartAutoFlow |0 |UINT8 |0x002= 10034 # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts= /Cts lines enabled; +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRxPinMux |0x0 |UINT32|0x002= 10035 # Pin muxing config for UART Rx pin +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartTxPinMux |0x0 |UINT32|0x002= 10039 # Pin muxing config for UART Tx pin +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRtsPinMux |0x0 |UINT32|0x002= 1003D # Pin muxing config for UART Rts pin +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartCtsPinMux |0x0 |UINT32|0x002= 10041 # Pin muxing config for UART Cts pin +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMmioBase |0xFE034000 |UINT32|0x002= 10045 # PcdSerialIoUartMode =3D Enabled, need to assign MMIO Resource in SE= C/PEI Phase + +## +## PCI Express MMIO region length +## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB, 0x= 4000000/64MB +## +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0020000= 1 +## +## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciE= xpressBaseAddress. +## This PCD is added for supporting different PCD type in different phases= . +## +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |0xC0000000|UINT64|0x00200= 002 +## +## PCI Express MMIO temporary region length in SEC phase. +## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB, 0x= 4000000/64MB +## +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000|UINT32|= 0x00200005 + +## Specifies the SMRR2 base address.

+# @Prompt SMRR2 base address. +# @Expression 0x80000001 | (gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base & 0xf= ff) =3D=3D 0 +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base|0|UINT32|0x20000002 + +## Specifies the SMRR2 range size.

+# @Prompt SMRR2 range size. +# @Expression 0x80000001 | (gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size & 0xf= ff) =3D=3D 0 +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size|0|UINT32|0x20000003 + +## Specifies the SMRR2 range cache type. +# If SMRR2 is used to map a flash/ROM based handler, it would be configur= ed as WP.

+# 5: WP(Write Protect).
+# 6: WB(Write Back).
+# @Prompt SMRR2 range cache type. +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2CacheType|5|UINT8|0x20000004 + +## Indidates if SMM PROT MODE feature is supported.

+# TRUE - SMM PROT MODE feature is supported.
+# FALSE - SMM PROT MODE feature is not supported.
+# @Prompt SMM PROT MODE feature. +gSiPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEAN|0x20000008 + +## Specifies the a size of memory region to reserve in SMM for testing onl= y. +# One can look in BIOS serial log for PCD to get region base address. +# Note: A different region may be allocated in release build than debug b= uild. +# @Prompt SMM test region size.\r +gSiPkgTokenSpaceGuid.PcdSmmTestRsvMemorySize|0x0|UINT32|0x2000000E + +[PcdsDynamic] + +## Indidates if SMM Code Access Check feature is supported.

+# TRUE - SMM Code Access Check feature is supported.
+# FALSE - SMM Code Access Check feature is not supported.
+# @Prompt SMM Code Access Check feature. +gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x001000D + +## Causes all UEFI variables to be treated as volatile and hence never wri= tten to non-volatile +## storage. +## This is useful in cases such as a simulation environment that does not = emulate a non-volatile +## storage device or in recovery scenarios where system errors prevent non= -volatile storage from being accessed +gSiPkgTokenSpaceGuid.PcdNvVariableEmulationMode|FALSE|BOOLEAN|0x0010000E + +## Enables or disables storage of UEFI variables using the CSE Variable St= orage drivers +## If disabled at runtime, it must be set before the CSE Variable Storag= e driver loads. +gSiPkgTokenSpaceGuid.PcdEnableCseVariableStorage|FALSE|BOOLEAN|0x0010000F + +## Enables or disables storage of UEFI variables using the FVB Variable St= orage drivers +## If disabled at runtime, it must be set before the FVB Variable Storage= driver loads. +gSiPkgTokenSpaceGuid.PcdEnableFvbVariableStorage|TRUE|BOOLEAN|0x00100010 + --=20 2.24.0.windows.2