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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Please remove EFI_HOB_GUID_TYPE and EFI_HOB_GENERIC_HEADER data structures = below this comment. +// @todo remove and use the MdePkg\Include\Pi\PiHob.h With that=20 Reviewed-by: Sai Chaganty =20 =20 -----Original Message----- From: Luo, Heng =20 Sent: Thursday, February 04, 2021 12:49 AM To: devel@edk2.groups.io Cc: Chaganty, Rangasai V ; Desimone, Nathani= el L Subject: [Patch V2 07/40] TigerlakeSiliconPkg/SystemAgent: Add include head= ers REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * SystemAgent/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDx= eConfig.h | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieDxeC= onfig.h | 114 +++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PramPreM= emConfig.h | 34 ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPe= iConfig.h | 24 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPe= iPreMemConfig.h | 104 +++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatformLi= b.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h = | 264 +++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h = | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++ 8 files changed, 772 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/MemoryDxeConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/MemoryDxeConfig.h new file mode 100644 index 0000000000..451e295b49 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mem= oryDxeConfig.h @@ -0,0 +1,123 @@ +/** @file + Memory DXE Policy definitions + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _MEMORY_DXE_CONFIG_H_ +#define _MEMORY_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define MEMORY_DXE_CONFIG_REVISION 1 + +typedef struct _MEMORY_DXE_CONFIG MEMORY_DXE_CONFIG; + +/** + Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocat= or field. + Implementation of this function is optional, if this function pointer is= NULL then + the reference implementation of DeviceLocator will be used. + + @param[in] This A pointer to this instance of = MEMORY_DXE_CONFIG. + @param[in] Controller Desired Controller to get a De= viceLocator string for. + @param[in] Dimm Desired DIMM to get a DeviceLo= cator string for. + @param[in] MdSocket 0 =3D Memory Down, 1 =3D Socke= ted. + + @retval The DeviceLocator string + @retval NULL If the return value is NULL, t= he default value will be used. +**/ +typedef +CHAR8* +(EFIAPI *MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)( + IN CONST MEMORY_DXE_CONFIG *This, + IN UINT8 Controller, + IN UINT8 Dimm, + IN UINT8 MdSocket + ); + +/** + Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator= field. + Implementation of this function is optional, if this function pointer is= NULL then + the reference implementation of DeviceLocator will be used. + + @param[in] This A pointer to this instance of = MEMORY_DXE_CONFIG. + @param[in] Controller Desired Controller to get a Ba= nkLocator string for. + @param[in] Dimm Desired DIMM to get a BankLoca= tor string for. + @param[in] MdSocket 0 =3D Memory Down, 1 =3D Socke= ted. + + @retval The BankLocator string + @retval NULL If the return value is NULL, t= he default value will be used. +**/ +typedef +CHAR8* +(EFIAPI *MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)( + IN CONST MEMORY_DXE_CONFIG *This, + IN UINT8 Controller, + IN UINT8 Dimm, + IN UINT8 MdSocket + ); + +/** + The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mec= hanical present bit map. + The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. +**/ +struct _MEMORY_DXE_CONFIG { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config= Block Header +/** + Offset 28: + Dimm SPD address + Only Server support 2 channels * 3 slots per channel =3D 6 sockets total= ly + The Desktop and mobile only support 2 channels * 2 slots per channel =3D= 4 sockets totally + So there is mapping rule here for Desktop and mobile that there are no m= ore 4 DIMMS totally in a system: + Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0] + Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1] + Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2] + Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3] + Refer to SmbiosMemory.c for use + If change the mapping rule, please update the Revision number. +**/ + UINT8 *SpdAddressTable; +/** + Offset 36: + Channel A DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -= > DIMM1, ... + if the bit is 1, the related DIMM slot is present. + E.g. if channel A has 2 DIMMs, ChannelASlotMap =3D 0x03; + E.g. if channel A has only 1 DIMMs, ChannelASlotMap =3D 0x01; + Refer to SmbiosMemory.c +**/ + UINT8 ChannelASlotMap; +/** + Offset 37: + Channel B DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -= > DIMM1, ... + if the bit is 1, the related DIMM slot is present. + E.g. if channel B has 2 DIMMs, ChannelBSlotMap =3D 0x03; + E.g. if channel B has only 1 DIMMs, ChannelBSlotMap =3D 0x01; + Refer to SmbiosMemory.c +**/ + UINT8 ChannelBSlotMap; +/** + Offset 38: + MRC execution time measurement: 0=3DDisable, 1=3DEnable +**/ + UINT8 MrcTimeMeasure; +/** + Offset 39: + Fast boot: 0=3DDisable, 1=3DEnable +**/ + UINT8 MrcFastBoot; +/** + Offset 40: + Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocat= or field. +**/ + MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING GetDeviceLocatorString; +/** + Offset 48: + Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator= field. +**/ + MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING GetBankLocatorString; +}; +#pragma pack(pop) + +#endif // _MEMORY_DXE_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/PcieDxeConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include= /ConfigBlock/PcieDxeConfig.h new file mode 100644 index 0000000000..799121f1ab --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pci= eDxeConfig.h @@ -0,0 +1,114 @@ +/** @file + PCIE DXE policy definitions + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PCIE_DXE_CONFIG_H_ +#define _PCIE_DXE_CONFIG_H_ + +#include "CpuPcieInfo.h" + +#pragma pack(push, 1) + +#define PCIE_DXE_CONFIG_REVISION 2 + +typedef struct { + UINT16 VendorId; ///< Offset 0 PCI Config space offset 0 + UINT16 DeviceId; ///< Offset 2 PCI Config space offset 2 +/** + Offset 4: + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are = valid + When clear values in bits 9:0 will be ignored + BIT[14] - Should be set to 0b + BIT[13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in the= se bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multi= plied with + the scale in bits 12:10 +**/ + UINT16 SnoopLatency; +/** + Offset 6: + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are = valid + When clear values in bits 9:0 will be ignored + BIT[14] - Should be set to 0b + BIT[13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in the= se bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be m= ultiplied with + the scale in bits 12:10 +**/ + UINT16 NonSnoopLatency; + UINT8 RevId; ///< Offset 8 PCI Config space offset 8; 0xFF means = all steppings + UINT8 Rsvd0[3]; ///< Offset 9 +} PCIE_LTR_DEV_INFO; + +/// +/// PCIE Power Optimizer config +/// +typedef struct { + UINT16 LtrMaxSnoopLatency; ///< Offset 0 LTR Maximum Snoop Latency: <= b>0x0846=3D70us + UINT16 LtrMaxNoSnoopLatency; ///< Offset 2 LTR Maximum Non-Snoop Latenc= y: 0x0846=3D70us + UINT8 ObffEnable; ///< Offset 4 LTR enable/disable: 0=3DDisa= ble, 1=3DEnable + UINT8 LtrEnable; ///< Offset 5 LTR enable/disable: 0=3DDisa= ble, 1=3DEnable + UINT8 Rsvd0[2]; ///< Offset 6 Reserved +} CPU_PCIE_PWR_OPT; + + +/** + The PCI Express Configuration info includes PCI Resources Range Base and= Limits and the control + for PEG ASPM. + The data elements should be initialized by a Platform Module.\n + @note Optional. These policies will be ignored if there is no PEG= port present on board. + Revision 1: + - Initial version. + Revision 2: + - Adding PEG RTD3 Support Setup Variable + Revision 3: + - Adding CPU PCIE RTD3 Support Setup Variable + - Deprecating PEG RTD3 Support Setup Variable + Revision 4: + - Deprecating CPU PCIE RTD3 Support Setup Variable +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-2= 7 Config Block Header +/** + Offset 28: This field is used to describe the ASPM control for PEG Ports= \n + 0=3DASPM Disabled, 1=3DASPM L0s Enabled, 2=3DASPM L1 Enabled, 3=3DASPM L= 0sL1 Enabled, 4=3DASPM AUTO +**/ + UINT8 PegAspm[SA_PEG_MAX_FUN]; +/** + Offset 32: PCIe Hot Plug Enable/Disable. It has 2 policies. + - Disabled (0x0) : No hotplug. + - Enabled (0x1) : Bios assist hotplug. +**/ + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN]; + CPU_PCIE_PWR_OPT PegPwrOpt[SA_PEG_MAX_FUN]; ///< Offset 36:= This field is used to describe the PCIe LTR/OBFF relevant settings + UINT32 PegRtd3; /// Deprecated = Policy + UINT8 CpuPcieRtd3; ///< Enable/Disa= ble RTD3 Support for CPU PCIE. 0=3DDisable and 1=3DEnable (default) // Dep= recated Policy + UINT8 Rsvd3[3]; +} PCIE_DXE_CONFIG; +#pragma pack(pop) + +#endif // _PCIE_DXE_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/PramPreMemConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Incl= ude/ConfigBlock/PramPreMemConfig.h new file mode 100644 index 0000000000..8947e80b22 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pra= mPreMemConfig.h @@ -0,0 +1,34 @@ +/** @file + Policy definition for Persisted Ram (Pram) Config Block + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _PRAM_PREMEM_CONFIG__H_ +#define _PRAM_PREMEM_CONFIG__H_ +#pragma pack(push, 1) + +#define PRAM_PREMEM_CONFIG_REVISION 1 + +/** + Defines Pram configuration parameters.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + /** + Offset 28: + Size of Pram + If disabled, or if PcdSaOcEnable is disabled, all other policies in this= config block are ignored. + 0=3DDisable, + 1=3D4MB, + 2=3D16MB, + 3=3D64MB + **/ + UINT8 Pram; + UINT8 Rsvd[3]; ///< Offset 29 Reserved for DWORD alignm= ent +} PRAM_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _PRAM_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/SaMiscPeiConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/SaMiscPeiConfig.h new file mode 100644 index 0000000000..203d894df9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaM= iscPeiConfig.h @@ -0,0 +1,24 @@ +/** @file + Policy details for miscellaneous configuration in System Agent + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SA_MISC_PEI_CONFIG_H_ +#define _SA_MISC_PEI_CONFIG_H_ + +#pragma pack(push, 1) + +#define SA_MISC_PEI_CONFIG_REVISION 1 + +/** + This configuration block is to configure SA Miscellaneous variables duri= ng PEI Post-Mem.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header +} SA_MISC_PEI_CONFIG; +#pragma pack(pop) + +#endif // _SA_MISC_PEI_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/SaMiscPeiPreMemConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent= /Include/ConfigBlock/SaMiscPeiPreMemConfig.h new file mode 100644 index 0000000000..8c660b31a9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaM= iscPeiPreMemConfig.h @@ -0,0 +1,104 @@ +/** @file + Policy details for miscellaneous configuration in System Agent + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_ +#define _SA_MISC_PEI_PREMEM_CONFIG_H_ + +#pragma pack(push, 1) + +#ifndef MEM_CFG_MAX_SOCKETS +#define MEM_CFG_MAX_SOCKETS 16 +#endif + +#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 2 + +/** + This configuration block is to configure SA Miscellaneous variables duri= ng PEI Pre-Mem phase like programming + different System Agent BARs, TsegSize, MmioSize required etc. + Revision 1: + - Initial version. + Revision 2: + - Deprecate IedSize. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + /** + Offset 28 Memory DIMMs' SPD address for reading SPD data. + TGL Mapping + 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 + 1 - Controller 0 Channel 0 Dimm 1 - DDR4 + 2 - Controller 0 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5 + 3 - Controller 0 Channel 1 Dimm 1 -------- DDR5 2DPC + 4 - Controller 0 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5 + 6 - Controller 0 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5 + 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5 + 9 - Controller 1 Channel 0 Dimm 1 - DDR4 + 10 - Controller 1 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5 + 11 - Controller 1 Channel 1 Dimm 1 -------- DDR5 2DPC + 12 - Controller 1 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5 + 14 - Controller 1 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5 + **/ + UINT8 SpdAddressTable[MEM_CFG_MAX_SOCKETS]; + VOID *S3DataPtr; ///< Offset 44 Memory data sa= ve pointer for S3 resume. The memory space should be allocated and filled w= ith proper S3 resume data on a resume path + UINT32 SmbusBar; ///< Offset 48 Address of Sys= tem Agent SMBUS BAR: 0xEFA0 + /** + Offset 52 Size of TSEG in bytes. (Must be power of 2) + 0x400000: 4MB for Release build (When IED enabled, it will be 8= MB) + 0x1000000 : 16MB for Debug build (Regardless IED enabled or disab= led) + **/ + UINT32 TsegSize; + /** + Offset 56 + (Test) Size of IED region in bytes. + 0 : IED Disabled (no memory occupied) + 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG) + Note: Enabling IED may also enlarge TsegSize together. + @deprecated + **/ + UINT32 IedSize; + UINT32 SkipExtGfxScan:1; ///< (Test) OFfset 60:= 0 :1=3DSkip External Gfx Device Scan; 0=3DScan for external graphics dev= ices. Set this policy to skip External Graphics card scanning if the pl= atform uses Internal Graphics only. + UINT32 BdatEnable:1; ///< Offset 60:1 :This field = enables the generation of the BIOS DATA ACPI Tables: 0=3DFALSE, 1=3D= TRUE. + UINT32 TxtImplemented:1; ///< OFfset 60:2 :This field = currently is used to tell MRC if it should run after TXT initializatoin com= pleted: 0=3DRun without waiting for TXT, 1=3DRun after TXT initializ= ation by callback + /** + Offset 60:3 : + (Test) Scan External Discrete Graphics Devices for Legacy Only V= GA OpROMs + + When enabled, if the primary graphics device is an external discrete gr= aphics device, Si will scan the + graphics device for legacy only VGA OpROMs. + + This is intended to ease the implementation of a BIOS feature to automa= tically enable CSM if the Primary Gfx device + only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling = CSM won't result in no video being displayed. + This is useful for platforms that implement PCIe slots that allow the e= nd user to install an arbitrary Gfx device. + + This setting will only take effect if SkipExtGfxScan =3D=3D 0. It is i= gnored otherwise. + + - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Defaul= t) + - Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM + **/ + UINT32 ScanExtGfxForLegacyOpRom:1; + UINT32 RsvdBits0 :28; ///< Offset 60:4 :Reserved fo= r future use + UINT8 UserBd; ///< Offset 64 0=3DMobile/= Mobile Halo, 1=3DDesktop/DT Halo, 5=3DULT/ULX/Mobile Halo, 7=3DUP Serve= r + UINT8 LockPTMregs; ///< (Test) Offset 65 = Lock PCU Thermal Management registers: 0=3DFALSE, 1=3DTRUE + UINT8 BdatTestType; ///< Offset 66 When BdatEnabl= e is set to TRUE, this option selects the type of data which will be popula= ted in the BIOS Data ACPI Tables: 0=3DRMT, 1=3DRMT Per Bit, 2=3DMarg= in 2D. + UINT8 CridEnable; ///< Offset 67 For Platforms = supporting Intel(R) SIPP, this policy is use control enable/disable Compati= bility Revision ID (CRID) feature: 0=3DFALSE, 1=3DTRUE + UINT32 AcpiReservedMemorySize; ///< Offset 68 The Size of a = Reserved memory buffer allocated in previous boot for S3 resume used. Origi= nally it is retrieved from AcpiVariableCompatibility variable. + UINT32 OpRomScanTempMmioBar; ///< (Test) Offset 72 = Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExt= GfxForLegacyOpRom feature. MUST BE 16MB ALIGNED! + UINT32 OpRomScanTempMmioLimit; ///< (Test) Offset 76 = Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feat= ure. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >=3D 16MB! + UINT64 AcpiReservedMemoryBase; ///< Offset 80 The Base addre= ss of a Reserved memory buffer allocated in previous boot for S3 resume use= d. Originally it is retrieved from AcpiVariableCompatibility variable. + UINT64 SystemMemoryLength; ///< Offset 88 Total system m= emory length from previous boot, this is required for S3 resume. Originally= it is retrieved from AcpiVariableCompatibility variable. + + UINT8 WrcFeatureEnable; ///< Offset 96: Enable/Disab= le WRC (Write Cache) feature of IOP. When enabled, supports IO devices allo= cating onto the ring and into LLC. + UINT8 Reserved1[3]; ///< Reserved for config blo= ck alignment. + + + // Since the biggest element is UINT64, this structure should be aligned= with 64 bits. + UINT8 Rsvd[4]; ///< Reserved for config bloc= k alignment. + + +} SA_MISC_PEI_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _SA_MISC_PEI_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/= SaPlatformLib.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Lib= rary/SaPlatformLib.h new file mode 100644 index 0000000000..daf3746605 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatf= ormLib.h @@ -0,0 +1,48 @@ +/** @file + Header file for SaPlatformLib. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_PLATFORM_LIB_H_ +#define _SA_PLATFORM_LIB_H_ + + +/** + Checks if SKU is Mobile + + @retval FALSE SKU is not Mobile + @retval TRUE SKU is Mobile +**/ +BOOLEAN +EFIAPI +IsMobileSku ( + VOID + ); + +/** + Checks if SKU is Desktop + + @retval FALSE SKU is not Desktop + @retval TRUE SKU is Desktop +**/ +BOOLEAN +EFIAPI +IsDesktopSku ( + VOID + ); + +/** + Checks if SKU is Server + + @retval FALSE SKU is not Server + @retval TRUE SKU is Server +**/ +BOOLEAN +EFIAPI +IsServerSku ( + VOID + ); + +#endif diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoH= ob.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h new file mode 100644 index 0000000000..b50d7e5188 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h @@ -0,0 +1,264 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_TRACE_CACHE_TYPE 3 + +#define MAX_NODE 2 +#define MAX_CH 4 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be= detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of p= resence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pa= ir and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank p= air. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originate= d from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration m= aximum value. + MrcBootModeDelim =3D INT32_MAX ///< This value ensures the en= um size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#ifndef MRC_DDR_TYPE_WIO2 +#define MRC_DDR_TYPE_WIO2 4 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 5 +#endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's comma= nd rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS l= atency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minim= um CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minim= um four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minim= um active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minim= um RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minim= um Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minim= um per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minim= um row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minim= um internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minim= um write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum= CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the= definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DD= R3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20= bytes + UINT8 RankInDimm; ///< The number of ranks in th= is DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType i= nformation needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType infor= mation needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusW= idth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing in= formation needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed= of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 =3D Memory Do= wn, 1 =3D Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this ch= annel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs tha= t exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values= . + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output char= acteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this co= ntroller should be used. + UINT16 DeviceId; ///< The PCI device id of this= memory controller. + UINT8 RevisionId; ///< The PCI revision id of th= is memory controller. + UINT8 ChannelCount; ///< Number of valid channels = that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel= level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of t= his memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or = LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed= of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock = speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK= value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable= DIMMs are detected, this will indicate which XMP Profiles are common among= all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddre= ss fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 PramSize; + UINT64 PramBase; + UINT64 DismLimit; + UINT64 DismBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol= /SaPolicy.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protoco= l/SaPolicy.h new file mode 100644 index 0000000000..4ff2578038 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPoli= cy.h @@ -0,0 +1,61 @@ +/** @file + Interface definition details between System Agent and platform drivers d= uring DXE phase. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ +#ifndef _SA_POLICY_H_ +#define _SA_POLICY_H_ + +#include +#include +#include +#include +#include +#include + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gSaPolicyProtocolGuid; +extern EFI_GUID gGraphicsDxeConfigGuid; +extern EFI_GUID gPcieDxeConfigGuid; +extern EFI_GUID gMemoryDxeConfigGuid; +extern EFI_GUID gVtdDxeConfigGuid; + +/** + Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external + modules maybe have consumed this macro in their source code. Directly + update the SA_POLICY_PROTOCOL_REVISION version number may cause those + external modules to auto mark themselves wrong version info. + Always create new version macro for new Policy protocol interface. +**/ +#define SA_POLICY_PROTOCOL_REVISION 1 + +#define CPU_PCIE_DEV_END_OF_TABLE 0xFFFF + +#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Snoop Latency +#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Non-Snoop Latency + + +/** + SA DXE Policy + + The SA_POLICY_PROTOCOL producer drvier is recommended to + set all the SA_POLICY_PROTOCOL size buffer zero before init any member pa= rameter, + this clear step can make sure no random value for those unknow new versio= n parameters. + + Make sure to update the Revision if any change to the protocol, including= the existing + internal structure definations.\n + Note: Here revision will be bumped up when adding/removing any config bl= ock under this structure.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31 +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +} SA_POLICY_PROTOCOL; + +#endif --=20 2.24.0.windows.2