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From: "Chaganty, Rangasai V" <rangasai.v.chaganty@intel.com>
To: "Sheng, W" <w.sheng@intel.com>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Ni, Ray" <ray.ni@intel.com>
Subject: Re: [PATCH v3 3/3] IntelSiliconPkg/PlatformVTdInfoSamplePei: Install Null Root Entry Table
Date: Fri, 4 Sep 2020 07:47:39 +0000	[thread overview]
Message-ID: <DM6PR11MB4476EEBD5FAEBCF911A48BD2B62D0@DM6PR11MB4476.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20200831063804.8208-4-w.sheng@intel.com>

Reviewed-by: Sai Chaganty <rangasai.v.chaganty@intel.com>

-----Original Message-----
From: Sheng, W <w.sheng@intel.com> 
Sent: Sunday, August 30, 2020 11:38 PM
To: devel@edk2.groups.io
Cc: Ni, Ray <ray.ni@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>
Subject: [PATCH v3 3/3] IntelSiliconPkg/PlatformVTdInfoSamplePei: Install Null Root Entry Table

BIOS uses TE with a null root entry table to block VT-d engine access to block any DMA traffic in pre-memory phase.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2867

Change-Id: I6c086c1f26e60f781de79cc37677cc5717c5edec
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@intel.com>
Signed-off-by: Sheng Wei <w.sheng@intel.com>
---
 .../PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c  | 16 ++++++++++++++++
 .../PlatformVTdInfoSamplePei.inf                         |  3 ++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
index 6f6c14f7..616a96ce 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei
+++ /PlatformVTdInfoSamplePei.c
@@ -9,6 +9,7 @@
 #include <PiPei.h>
 
 #include <Ppi/VtdInfo.h>
+#include <Ppi/VtdNullRootEntryTable.h>
 
 #include <Library/PeiServicesLib.h>
 #include <Library/DebugLib.h>
@@ -164,6 +165,15 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc = {
   &mPlatformVTdNoIgdSample
 };
 
+// BIOS uses TE with a null root entry table to block VT-d engine access to block any DMA traffic in pre-memory phase.
+EDKII_VTD_NULL_ROOT_ENTRY_TABLE_PPI mNullRootEntryTable = 0xFED20000;
+
+EFI_PEI_PPI_DESCRIPTOR mPlatformNullRootEntryTableDesc = {
+  (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gEdkiiVTdNullRootEntryTableGuid,
+  &mNullRootEntryTable
+};
+
 /**
   Initialize VTd register.
   Initialize the VTd hardware unit which has INCLUDE_PCI_ALL set @@ -344,6 +354,12 @@ PlatformVTdInfoSampleInitialize (
   if (!EFI_ERROR(Status)) {
     SiliconInitialized = TRUE;
   }
+
+  Status = PeiServicesInstallPpi (&mPlatformNullRootEntryTableDesc);
+  if (EFI_ERROR (Status)) {
+    ASSERT_EFI_ERROR (Status);
+  }
+
   DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized));
   if (!SiliconInitialized) {
     Status = PeiServicesNotifyPpi (&mSiliconInitializedNotifyList); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
index dacfdf5e..b35853b6 100644
--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
+++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei
+++ /PlatformVTdInfoSamplePei.inf
@@ -38,7 +38,8 @@
   IoLib
 
 [Ppis]
-  gEdkiiVTdInfoPpiGuid         ## PRODUCES
+  gEdkiiVTdInfoPpiGuid              ## PRODUCES
+  gEdkiiVTdNullRootEntryTableGuid   ## PRODUCES
 
 [Depex]
   gEfiPeiMasterBootModePpiGuid
--
2.16.2.windows.1


      parent reply	other threads:[~2020-09-04  7:47 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20200831063804.8208-1-w.sheng@intel.com>
     [not found] ` <20200831063804.8208-2-w.sheng@intel.com>
2020-09-01 14:30   ` [PATCH v3 1/3] IntelSiliconPkg/VtdInfo: Add Null Root Entry Table PPI Ni, Ray
2020-09-04  7:46   ` Chaganty, Rangasai V
     [not found] ` <20200831063804.8208-3-w.sheng@intel.com>
2020-09-01 14:31   ` [PATCH v3 2/3] IntelSiliconPkg/IntelVTdPmrPei: Fix PMR enabling setting confilct Ni, Ray
2020-09-04  7:47   ` Chaganty, Rangasai V
     [not found] ` <20200831063804.8208-4-w.sheng@intel.com>
2020-09-02  1:43   ` [PATCH v3 3/3] IntelSiliconPkg/PlatformVTdInfoSamplePei: Install Null Root Entry Table Ni, Ray
2020-09-04  7:47   ` Chaganty, Rangasai V [this message]

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