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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed by Jenny Huang -----Original Message----- From: devel@edk2.groups.io On Behalf Of Sheng, W Sent: Tuesday, May 23, 2023 1:11 AM To: devel@edk2.groups.io Cc: Ni, Ray ; Chaganty, Rangasai V ; Huang, Jenny ; Kowalewski, Robert Subject: [edk2-devel] [PATCH] IntelSiliconPkg/IntelVTdDmarPei: Fix build er= ror when disable optimization MSFT:*_*_*_CC_FLAGS =3D /Od will disable build optimization. Signed-off-by: Sheng Wei Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jenny Huang Cc: Robert Kowalewski --- .../VTd/IntelVTdDmarPei/IntelVTdDmar.c | 43 +++++++++++++------ 1 file changed, 31 insertions(+), 12 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index ae9135010..e1b867973 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c @@ -242,6 +242,7 @@ SubmitQueuedInvalidationDescriptor ( VTD_IQA_REG IqaReg; VTD_IQT_REG IqtReg; VTD_IQH_REG IqhReg; + UINT64 IQBassAddress; =20 if (Desc =3D=3D NULL) { return EFI_INVALID_PARAMETER; @@ -249,19 +250,29 @@ SubmitQueuedInvalidationDescriptor ( =20 VtdUnitBaseAddress =3D VTdUnitInfo->VtdUnitBaseAddress; IqaReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_IQA_REG); - if (IqaReg.Bits.IQA =3D=3D 0) { + // + // Get IQA_REG.IQA (Invalidation Queue Base Address) + // + IQBassAddress =3D RShiftU64 (IqaReg.Uint64, 12); + if (IQBassAddress =3D=3D 0) { DEBUG ((DEBUG_ERROR,"Invalidation Queue Buffer not ready [0x%lx]\n", I= qaReg.Uint64)); return EFI_NOT_READY; } IqtReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_IQT_REG); =20 - if (IqaReg.Bits.DW =3D=3D 0) { + // + // Check IQA_REG.DW (Descriptor Width) + // + if ((IqaReg.Uint64 & BIT11) =3D=3D 0) { // // 128-bit descriptor // QueueSize =3D (UINTN) (1 << (IqaReg.Bits.QS + 8)); - Qi128Desc =3D (QI_DESC *) (UINTN) (IqaReg.Bits.IQA << VTD_PAGE_SHIFT); - QueueTail =3D (UINTN) IqtReg.Bits128Desc.QT; + Qi128Desc =3D (QI_DESC *) (UINTN) LShiftU64 (IQBassAddress, VTD_PAGE_S= HIFT); + // + // Get IQT_REG.QT for 128-bit descriptors + // + QueueTail =3D (UINTN) (RShiftU64 (IqtReg.Uint64, 4) & 0x7FFF); Qi128Desc +=3D QueueTail; Qi128Desc->Low =3D Desc->Uint64[0]; Qi128Desc->High =3D Desc->Uint64[1]; @@ -274,14 +285,18 @@ SubmitQueuedInvalidationDescriptor ( Desc->Uint64[0], Desc->Uint64[1])); =20 - IqtReg.Bits128Desc.QT =3D QueueTail; + IqtReg.Uint64 &=3D ~(0x7FFF << 4); + IqtReg.Uint64 |=3D LShiftU64 (QueueTail, 4); } else { // // 256-bit descriptor // QueueSize =3D (UINTN) (1 << (IqaReg.Bits.QS + 7)); - Qi256Desc =3D (QI_256_DESC *) (UINTN) (IqaReg.Bits.IQA << VTD_PAGE_SHI= FT); - QueueTail =3D (UINTN) IqtReg.Bits256Desc.QT; + Qi256Desc =3D (QI_256_DESC *) (UINTN) LShiftU64 (IQBassAddress, VTD_PA= GE_SHIFT); + // + // Get IQT_REG.QT for 256-bit descriptors + // + QueueTail =3D (UINTN) (RShiftU64 (IqtReg.Uint64, 5) & 0x3FFF); Qi256Desc +=3D QueueTail; Qi256Desc->Uint64[0] =3D Desc->Uint64[0]; Qi256Desc->Uint64[1] =3D Desc->Uint64[1]; @@ -298,7 +313,8 @@ SubmitQueuedInvalidationDescriptor ( Desc->Uint64[2], Desc->Uint64[3])); =20 - IqtReg.Bits256Desc.QT =3D QueueTail; + IqtReg.Uint64 &=3D ~(0x3FFF << 5); + IqtReg.Uint64 |=3D LShiftU64 (QueueTail, 5); } =20 // @@ -315,10 +331,13 @@ SubmitQueuedInvalidationDescriptor ( } =20 IqhReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_IQH_REG); - if (IqaReg.Bits.DW =3D=3D 0) { - QueueHead =3D (UINTN) IqhReg.Bits128Desc.QH; + // + // Check IQA_REG.DW (Descriptor Width) and get IQH_REG.QH + // + if ((IqaReg.Uint64 & BIT11) =3D=3D 0) { + QueueHead =3D (UINTN) (RShiftU64 (IqhReg.Uint64, 4) & 0x7FFF); } else { - QueueHead =3D (UINTN) IqhReg.Bits256Desc.QH; + QueueHead =3D (UINTN) (RShiftU64 (IqhReg.Uint64, 5) & 0x3FFF); } } while (QueueTail !=3D QueueHead); =20 @@ -410,7 +429,7 @@ InvalidateIOTLB ( // Queued Invalidation // CapReg.Uint64 =3D MmioRead64 (VTdUnitInfo->VtdUnitBaseAddress + R_CAP_= REG); - QiDesc.Uint64[0] =3D QI_IOTLB_DID(0) | QI_IOTLB_DR(CAP_READ_DRAIN(CapR= eg.Uint64)) | QI_IOTLB_DW(CAP_WRITE_DRAIN(CapReg.Uint64)) | QI_IOTLB_GRAN(1= ) | QI_IOTLB_TYPE; + QiDesc.Uint64[0] =3D QI_IOTLB_DID(0) | (CapReg.Bits.DRD ? QI_IOTLB_DR(= 1) : QI_IOTLB_DR(0)) | (CapReg.Bits.DWD ? QI_IOTLB_DW(1) : QI_IOTLB_DW(0)) = | QI_IOTLB_GRAN(1) | QI_IOTLB_TYPE; QiDesc.Uint64[1] =3D QI_IOTLB_ADDR(0) | QI_IOTLB_IH(0) | QI_IOTLB_AM(0= ); QiDesc.Uint64[2] =3D 0; QiDesc.Uint64[3] =3D 0; --=20 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#105160): https://edk2.groups.io/g/devel/message/105160 Mute This Topic: https://groups.io/mt/99082903/2558558 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [w.sheng@intel.com] -=3D-=3D-=3D-=3D-=3D-=3D