From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web09.6618.1664423664293950726 for ; Wed, 28 Sep 2022 20:54:24 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Dgq1R/fm; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: jenny.huang@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664423664; x=1695959664; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-transfer-encoding:mime-version; bh=8k5zwWc7GtqJ5HpJLwjkxLTwbLJnGyeL/lrkD2Ctwxg=; b=Dgq1R/fmaDodvlTwEnpEWm76uPcf8w1RaRxOk/VySlllJP/L1qD9IyWT g52Eiavy7m6d0yA5azEDU2U3YM88xumpLxzxPi3sEsHT1DvRfbdOssK+3 BdvsozN4KvS0jGc89j7XGlo8bLUf1+0g3VMAKZo/cgQ3KU+lJjgOeKTOu JgvwbNy/BoLSQ3lBDMKhRYYbdsBZgXvahrUHLaIEdlip/8G1czztt7B6q MywzX98QiJMQ7XEBgJEhEdRkT/7VItwneATKydOfMm+lNCHmW0h97/N4Q A0G937IfwluZ7Q6unYra2DZzgB1F4SuS/I8DByVuqN/m+Qz3URL81PngU Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10484"; a="303271603" X-IronPort-AV: E=Sophos;i="5.93,354,1654585200"; d="scan'208";a="303271603" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Sep 2022 20:54:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10484"; a="867219304" X-IronPort-AV: E=Sophos;i="5.93,354,1654585200"; d="scan'208";a="867219304" Received: from orsmsx602.amr.corp.intel.com ([10.22.229.15]) by fmsmga006.fm.intel.com with ESMTP; 28 Sep 2022 20:54:23 -0700 Received: from orsmsx608.amr.corp.intel.com (10.22.229.21) by ORSMSX602.amr.corp.intel.com (10.22.229.15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Wed, 28 Sep 2022 20:54:23 -0700 Received: from orsmsx608.amr.corp.intel.com (10.22.229.21) by ORSMSX608.amr.corp.intel.com (10.22.229.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Wed, 28 Sep 2022 20:54:22 -0700 Received: from orsedg603.ED.cps.intel.com (10.7.248.4) by orsmsx608.amr.corp.intel.com (10.22.229.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31 via Frontend Transport; Wed, 28 Sep 2022 20:54:22 -0700 Received: from NAM02-DM3-obe.outbound.protection.outlook.com (104.47.56.42) by edgegateway.intel.com (134.134.137.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2375.31; Wed, 28 Sep 2022 20:54:21 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=d97oMhMpMllFKuBsKrKtAwhRJWM/IsZhtBqvKmFPFhcscwCYPjl/LHBYliD1AlAh7iEE7bFxGPus2CxAgMyTt6QjJIILHfUPfuVNmDEmCYDx9AsoZYai6cgvSvS7QBegHClxDl5axD4Ujf0Rokacu1fsII5L9F9+TT0WENxlpas23GHXNstNsSA49Y12kr1hRziFanTLMpoZtgPaNEVS3kj2CjWiqUl7KC4hqa/O8ApY23jzqIXWDJ/hq+bUmtQb/pXOwvyd+rQIJVQgANHc1gzqeyWC3Ov7BDDmkhiucwShiPyr/At73TLJWcep5lBJZpoKi8oJaA58ocgQ1pegdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=Nhf98hzyzMkbfYwPUjL8I1JmsdyWJ1Rt1CPCCgeBGlE=; b=g2DyocnsmYa+EG8JyxhJxf2qY65pguHXNO9XDTA8zAqMzJN9Lov/qEA3a3zkOmhCywKQ8LU6MQrQTdoG8gXHNLUjL6SBDxtuUdqB9zCHg23ryppISdPPV2x5gIuIH5OTIB2aGjIeZsLrCOnLPIb+6VinqEMLWYuqYnU/XSc7QDABzqFnzEGJi2tONgYOUDWUWBi/Vr0Nh1TSGOXvo7Jef1KASQyyHxgPxzQBfNVqB7VraWXqM8PZLEiU+sRVgg96UjpWbDP5gs4KCPCk/W9pGnhZ+Mzw2Q6eq7TBTL1t8s4nXyEqNuo6Oq+ml2G7JwF1lsggf6E3DfmpAvLDkv2tUQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Received: from DM6PR11MB4627.namprd11.prod.outlook.com (2603:10b6:5:2a2::19) by IA1PR11MB6371.namprd11.prod.outlook.com (2603:10b6:208:3ad::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5654.26; Thu, 29 Sep 2022 03:54:19 +0000 Received: from DM6PR11MB4627.namprd11.prod.outlook.com ([fe80::5c4:1838:6e33:db1e]) by DM6PR11MB4627.namprd11.prod.outlook.com ([fe80::5c4:1838:6e33:db1e%9]) with mapi id 15.20.5676.017; Thu, 29 Sep 2022 03:54:19 +0000 From: "Huang, Jenny" To: "devel@edk2.groups.io" , "Sheng, W" CC: "Ni, Ray" , "Chaganty, Rangasai V" , "Kowalewski, Robert" Subject: Re: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Enable ADM when change TTM Thread-Topic: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Enable ADM when change TTM Thread-Index: AQHYwQR+YwMYhT53OUSQxj/p+0KR6a316+pg Date: Thu, 29 Sep 2022 03:54:19 +0000 Message-ID: References: <1711EAB1819FAD8B.21447@groups.io> In-Reply-To: <1711EAB1819FAD8B.21447@groups.io> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.6.500.17 dlp-reaction: no-action dlp-product: dlpe-windows authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: DM6PR11MB4627:EE_|IA1PR11MB6371:EE_ x-ms-office365-filtering-correlation-id: 0fd96f19-4e76-409a-069d-08daa1ce497e x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: PYKt5qc8sUQna8qtVqyf/yrlSqivjMPIcTIWhrH2p7mt19yG+XwJNJLq+ZGmwwm8NtacA1cqc3dT9UqsEpoVbTTq78QX3+m0OzKVw+MTpwTSPCdFxvYkV5CV+EwfTo1g+a0H3VIGn7+MqLeZMAhDhWJ7GWJfTvK/uqFCba0YD/1E46ur3R8nkWBH54J9jWv8pRdRDgkPzBY5/hdSmtc8qO398cxOqnUnR1NZzK/Biyo1aE8zrD2ywgx2TJKbnczm1xfG0SH4J4U/3Madlq2ATClLwRMKqYAWiAbHLSR4LpaqE3XpYjoyXHsSOODIBRRUlY9MbL404bJLxPl3xSd7UUtOwGj+tv7gXD8vT1glOlh3k96kWbNK6IB4jG9BVcVanQXgGAQ8WKRD+x4urwHQpD2l4RLBGpt7x9zHZIIf7YlohooI15/qdeHTMA0acUr6qr+JcVDwCVjTEC0YPyAhUOA79LK+Il6F2NENhg6GAwsJQr0yI7yVIOtbrGo/wfYKJy5yoYUjdDqsReBwmP0BipBK9rS/8NoHnvujUMzNVVHEsuivTKrQCqgBbNM2IZ2clwnW9UGPQG7FAreMfzeMMaI7apgBdHeAVDyiGwq3C79vmCqtL5Pn8mbP0pegP3mofalhQVdyh/hRGvbzqXQVVoSHwo1THkKLzRKNAKYMPBUApLtBnpv9P4e87MnyH0uGikA7KYYfV6CNeLm95aB+DAlsOSGBM9CAGqo0Hvw3I8ukFiIqT7KX0la6a6thSjpsxCAh0/jX6yrAosUzRXmdtxWfiV565qsf6XBlxFS5HFkMvw8hTQamNkTiI2mNsqpBqZsztjx+lFZr7wElwJatSQ== x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:DM6PR11MB4627.namprd11.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230022)(39860400002)(366004)(136003)(376002)(396003)(346002)(451199015)(122000001)(2906002)(66446008)(52536014)(53546011)(6636002)(30864003)(6506007)(82960400001)(7696005)(66946007)(41300700001)(83380400001)(478600001)(9686003)(76116006)(38100700002)(26005)(966005)(55016003)(38070700005)(107886003)(8936002)(110136005)(54906003)(66899015)(71200400001)(33656002)(86362001)(66476007)(64756008)(8676002)(4326008)(316002)(186003)(5660300002)(66556008)(579004);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?9bT2D8D/k1VtrtDmUhxDilWwHst3fKmcnr7pp3uii8hadmJZ6ww4oDnm6Nyo?= =?us-ascii?Q?zeYhV0GakPm0UnP0I8Qvx92TF1WZtTwU7kSw3L1Wec9Yexu6Crq+NQBCdxh4?= =?us-ascii?Q?fDpglqDhwyfAhW5DFsvEWklen+f3dlll7JAheJ48kjdBzOrZQqqD3a6p//At?= =?us-ascii?Q?MzyRj36BgPhLO3+4MsJ526NsKw7p+DGaHhhc9Tc/8bWMMECzYZk1Zusop+zm?= =?us-ascii?Q?UxwdRZoMkwbR0+5hmg99NtXgSchob+wl818pXTNNWiVfQHmzQQJ9VZJu/5+v?= =?us-ascii?Q?dC9Nj7O4W1Tl9APQSmzdJvhLWWB7ci9rpJTKP7OHnqPpMHYAUiFI1J490UtJ?= =?us-ascii?Q?EV0mF0mpGyE7NGeItQM65Dsku2PnMwQQyVT1cdOEE84wDrUGFMhvTXqHoIuY?= =?us-ascii?Q?3UlTfavoo1gJI4o+kCHAX8yVPpzGlWXk3v6y4hZqTjqiVJVFncP+iUl4TZIB?= =?us-ascii?Q?EBVtaYls4BNh5UYPt4eMkPbH9Mgu+QbmbptPFgcqwEpq6Fxfx7A6ztNPgp6V?= =?us-ascii?Q?x4NQJuNGNq9jRwzHiBiLKVDN/zBWYu5Uo9en9A96t6lCeU3jO5CLKIzErgHC?= =?us-ascii?Q?4+pIjd/D7057Z8kcOQWHowPz4N0Q9fBMyzalJLq09yD2sPmBnE3jzAWYOnAW?= =?us-ascii?Q?YHcZYPcVqnkE/6Af632OyyOkFkz87V9AzTNlqFplTm8NW5qnh/cgDYOw8kjM?= =?us-ascii?Q?EfMFrLwgsbec28sjVvqD2YQ9MIYto4bsksYCZB2+xF7rPFfFRmyjKtyNDduK?= =?us-ascii?Q?uVfXIihWZMNAwKczEBLW0gzggVKEQxoyqhUfLI/9dfgy7I3StdRpXKfNNrTr?= =?us-ascii?Q?jvrgv3EmGhDoWM6752kn+XYitzkwnjpzci+FR/18bjYksgMIOIX1uyuDd1Wx?= =?us-ascii?Q?okkdzoUYzB0LA8ovtkdJ7TswVvQjEqLxpzTb7dcjc29SHHBE1ozkKjYJRsV6?= =?us-ascii?Q?e49tbrTzpNkg0RgkDoXnqacD3E+HrVCSMxy3i/wAcY6PLHcC816IU+JX3gwY?= =?us-ascii?Q?li/W2Oh6Uz0lTc7JtC/HiWJFgLJWGKoWzVMDASh0ieTG/i6Rdn2bBnPG4d3D?= =?us-ascii?Q?jBxcKhvtaxMhC68PMket902XsvR/TGi81tKYdlgsiIYpnrEQkPMVLi5Yj74q?= =?us-ascii?Q?2sKFf3fzY4HJUjrSqGvp60/wy4z8Az+vloJnD+//u6uch65L/rxH2x40uoR5?= =?us-ascii?Q?jC4668WzFIbkSlN2Qpy7oiXBZj1LOJgyKljUrieA0WC6FWz6q++qMkG1dsjV?= =?us-ascii?Q?68Fu7O3xS44RRLdMB/1DkOh1QTywLFKmkVmFDJJY2mfgdl68Rt1zsezuDv6K?= =?us-ascii?Q?4CBsgwErH6tjFXBvl418U7oZ1GKluKdYQU/pfWQx95393X2xLe8ZZne3LCUf?= =?us-ascii?Q?58wVPEIFlUBDzoHdqTK9xsG3Gcyynaf1lzv3trEKkv0Gl9manJx2ZPMO8Xj0?= =?us-ascii?Q?YIGdfkDsIjq9K9YNkAp8GdqzBrgSRNtKlNU8ovKVRrxaUsPuvBKdli00u8Ti?= =?us-ascii?Q?UnpbcmPt7xO44YgnxeDzdOWqwcAq4/XaE1pcz5Kq7cDvWhAQ/r8C3OJhoAVR?= =?us-ascii?Q?S7B0ZBvRpfyiMxLRndit20kWKdtZIVp+Qtk5oylM?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM6PR11MB4627.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0fd96f19-4e76-409a-069d-08daa1ce497e X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Sep 2022 03:54:19.4052 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: FTkC1PHfwVI7E9WINM5CAO4odEFXeMvSrjyq3TXRxtvyPbCXnUgjPZt1kpTB5Xs2EOJ1U0BXo+eiOsduGvHqjQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB6371 Return-Path: jenny.huang@intel.com X-OriginatorOrg: intel.com Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Jenny Huang -----Original Message----- From: devel@edk2.groups.io On Behalf Of Sheng, W Sent: Monday, September 5, 2022 1:49 AM To: devel@edk2.groups.io Cc: Huang, Jenny ; Ni, Ray ; Chaga= nty, Rangasai V ; Kowalewski, Robert Subject: [edk2-devel] [PATCH] IntelSiliconPkg/VTd: Enable ADM when change T= TM In Abort DMA Mode(ADM), hardware will abort all DMA operations without the = need to set up a roottable. Enable Abort DMA Mode, when change Translation = Table Mode(TTM) Change-Id: I74207fe96ef7a57d89a355d40dfbdd36186f06c3 Signed-off-by: Sheng Wei Cc: Jenny Huang Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Robert Kowalewski --- .../VTd/IntelVTdDmarPei/IntelVTdDmar.c | 157 +++++++++++----- .../Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf | 1 + .../Feature/VTd/IntelVTdDxe/VtdReg.c | 169 +++++++++++++----- .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 12 +- 4 files changed, 245 insertions(+), 94 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index b5b78f779..24beccd26 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTd +++ Dmar.c @@ -361,6 +361,68 @@ InvalidateIOTLB ( return EFI_SUCCESS; } =20 +/** + Clear Global Command Register Bits + + @param[in] VtdUnitBaseAddress The base address of the VTd engine. + @param[in] BitMask Bit mask. +**/ +VOID +ClearGlobalCommandRegisterBits ( + IN UINTN VtdUnitBaseAddress, + IN UINT32 BitMask + ) +{ + UINT32 Reg32; + UINT32 Status; + UINT32 Command; + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & (~BitMask)); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + DEBUG((DEBUG_INFO, "Clear GCMD_REG bits 0x%x.\n", BitMask)); + + // + // Poll on Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & BitMask) =3D=3D BitMask); +} + +/** + Set Global Command Register Bits + + @param[in] VtdUnitBaseAddress The base address of the VTd engine. + @param[in] BitMask Bit mask. +**/ +VOID +SetGlobalCommandRegisterBits ( + IN UINTN VtdUnitBaseAddress, + IN UINT32 BitMask + ) +{ + UINT32 Reg32; + UINT32 Status; + UINT32 Command; + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | BitMask); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + DEBUG((DEBUG_INFO, "Set GCMD_REG bits 0x%x.\n", BitMask)); + + // + // Poll on Status bit of Global status register to become not zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & BitMask) =3D=3D 0); +} + /** Enable DMAR translation in pre-mem phase. =20 @@ -383,13 +445,10 @@ EnableDmarPreMem ( DEBUG ((DEBUG_INFO, "RTADDR_REG : 0x%016lx \n", RtaddrRegValue)); MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, RtaddrRegValue); =20 - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_SRTP); - DEBUG ((DEBUG_INFO, "EnableDmarPreMem: waiting for RTPS bit to be set...= \n")); - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP); + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); DEBUG ((DEBUG_INFO, "EnableDmarPreMem: R_GSTS_REG =3D 0x%x \n", Reg32)); =20 // @@ -405,12 +464,7 @@ EnableDmarPreMem ( // // Enable VTd // - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_TE); - DEBUG ((DEBUG_INFO, "EnableDmarPreMem: Waiting B_GSTS_REG_TE ...\n")); - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 DEBUG ((DEBUG_INFO, "VTD () enabled!<<<<<<\n")); =20 @@ -434,22 +488,43 @@ EnableDmar ( { UINT32 Reg32; UINTN VtdUnitBaseAddress; + BOOLEAN TEWasEnabled; =20 VtdUnitBaseAddress =3D VTdUnitInfo->VtdUnitBaseAddress; =20 DEBUG ((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%x] \n", VtdUnitBase= Address)); =20 - DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable)); - MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) RootEntryTable)= ; + // + // Check TE was enabled or not. + // + TEWasEnabled =3D ((MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG) &=20 + B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); =20 - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_SRTP); + if (TEWasEnabled && (VTdUnitInfo->ECapReg.Bits.ADMS =3D=3D 1) &&=20 + PcdGetBool (PcdVTdSupportAbortDmaMode)) { + // + // For implementations reporting Enhanced SRTP Support (ESRTPS)=20 + field as + // Clear in the Capability register, software must not modify this=20 + field while + // DMA remapping is active (TES=3D1 in Global Status register). + // + if (VTdUnitInfo->CapReg.Bits.ESRTPS =3D=3D 0) { + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress,=20 + B_GMCD_REG_TE); + } + + // + // Enable ADM + // + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)=20 + (RootEntryTable | V_RTADDR_REG_TTM_ADM)); + + DEBUG((DEBUG_INFO, "Enable Abort DMA Mode...\n")); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); + + } else { + DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable)); + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)=20 + RootEntryTable); + + } =20 DEBUG ((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n"))= ; - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); - DEBUG ((DEBUG_INFO, "EnableDmar: R_GSTS_REG =3D 0x%x \n", Reg32)); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP); =20 // // Init DMAr Fault Event and Data registers @@ -471,15 +546,19 @@ EnableDmar ( // InvalidateIOTLB (VTdUnitInfo); =20 + if (TEWasEnabled && (VTdUnitInfo->ECapReg.Bits.ADMS =3D=3D 1) &&=20 + PcdGetBool (PcdVTdSupportAbortDmaMode)) { + if (VTdUnitInfo->CapReg.Bits.ESRTPS =3D=3D 0) { + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress,=20 + B_GMCD_REG_TE); + } + + DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable)); + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)=20 + RootEntryTable); + } + // // Enable VTd // - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_TE); - DEBUG ((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n")); - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 DEBUG ((DEBUG_INFO, "VTD () enabled!<<<<<<\n")); =20 @@ -500,8 +579,6 @@ DisableDmar ( ) { UINT32 Reg32; - UINT32 Status; - UINT32 Command; =20 DEBUG ((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", VtdUnitBas= eAddress)); =20 @@ -516,28 +593,12 @@ DisableDmar ( // // Set TE (Translation Enable: BIT31) of Global command register to zero // - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits - Command =3D (Status & ~B_GMCD_REG_TE); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); - - // - // Poll on TE Status bit of Global status register to become zero - // - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 // // Set SRTP (Set Root Table Pointer: BIT30) of Global command register i= n order to update the root table pointerDisable VTd // - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits - Command =3D (Status | B_GMCD_REG_SRTP); - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); - do { - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP); =20 Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32)); @@ -568,12 +629,12 @@ EnableVTdTranslationProtectionBlockDma ( =20 DEBUG ((DEBUG_INFO, "EnableVTdTranslationProtectionBlockDma - 0x%08x\n",= VtdUnitBaseAddress)); =20 - DEBUG ((DEBUG_INFO, "PcdVTdSupportAbortDmaMode : %d\n", FixedPcdGetBool = (PcdVTdSupportAbortDmaMode))); + DEBUG ((DEBUG_INFO, "PcdVTdSupportAbortDmaMode : %d\n", PcdGetBool=20 + (PcdVTdSupportAbortDmaMode))); =20 ECapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_ECAP_REG); DEBUG ((DEBUG_INFO, "ECapReg.ADMS : %d\n", ECapReg.Bits.ADMS)); =20 - if ((ECapReg.Bits.ADMS =3D=3D 1) && FixedPcdGetBool (PcdVTdSupportAbortD= maMode)) { + if ((ECapReg.Bits.ADMS =3D=3D 1) && PcdGetBool=20 + (PcdVTdSupportAbortDmaMode)) { // // Use Abort DMA Mode // diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTd= Dxe.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe= .inf index 387f90e37..b152831c0 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe. +++ inf @@ -75,6 +75,7 @@ [Pcd] gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask ## CONSUMES gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdVTdSupportAbortDmaMode ## CONSUMES =20 [Depex] gEfiPciRootBridgeIoProtocolGuid diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index c7a56cf57..396aa4a70 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -475,6 +475,92 @@ DisablePmr ( return ; } =20 +/** + Clear Global Command Register Bits + + @param[in] VtdUnitBaseAddress The base address of the VTd engine. + @param[in] BitMask Bit mask. +**/ +VOID +ClearGlobalCommandRegisterBits ( + IN UINTN VtdUnitBaseAddress, + IN UINT32 BitMask + ) +{ + UINT32 Reg32; + UINT32 Status; + UINT32 Command; + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & (~BitMask)); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + DEBUG((DEBUG_INFO, "Clear GCMD_REG bits 0x%x.\n", BitMask)); + + // + // Poll on Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & BitMask) =3D=3D BitMask); +} + +/** + Set Global Command Register Bits + + @param[in] VtdUnitBaseAddress The base address of the VTd engine. + @param[in] BitMask Bit mask. +**/ +VOID +SetGlobalCommandRegisterBits ( + IN UINTN VtdUnitBaseAddress, + IN UINT32 BitMask + ) +{ + UINT32 Reg32; + UINT32 Status; + UINT32 Command; + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | BitMask); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + DEBUG((DEBUG_INFO, "Set GCMD_REG bits 0x%x.\n", BitMask)); + + // + // Poll on Status bit of Global status register to become not zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & BitMask) =3D=3D 0); +} + +/** + Update Root Table Address Register + + @param[in] VtdIndex The index used to identify a VTd engine. + @param[in] EnableADM TRUE - Enable ADM in TTM bits +**/ +VOID +UpdateRootTableAddressRegister ( + IN UINTN VtdIndex, + IN BOOLEAN EnableADM + ) +{ + UINT64 Reg64; + + if (mVtdUnitInformation[VtdIndex].ExtRootEntryTable !=3D NULL) { + DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n",=20 + mVtdUnitInformation[VtdIndex].ExtRootEntryTable)); + Reg64 =3D=20 + (UINT64)(UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable |=20 + (EnableADM ? V_RTADDR_REG_TTM_ADM : BIT11); + } else { + DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n",=20 + mVtdUnitInformation[VtdIndex].RootEntryTable)); + Reg64 =3D (UINT64)(UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable= =20 + | (EnableADM ? V_RTADDR_REG_TTM_ADM : 0); + } + MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress +=20 + R_RTADDR_REG, Reg64); +} + /** Enable DMAR translation. =20 @@ -488,25 +574,43 @@ EnableDmar ( { UINTN Index; UINT32 Reg32; + UINTN VtdUnitBaseAddress; + BOOLEAN TEWasEnabled; =20 for (Index =3D 0; Index < mVtdUnitNumber; Index++) { - DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] \n", Index)); + VtdUnitBaseAddress =3D mVtdUnitInformation[Index].VtdUnitBaseAddress; + DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] BAR=20 + [0x%x]\n", Index, VtdUnitBaseAddress)); + + // + // Check TE was enabled or not. + // + TEWasEnabled =3D ((MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG) &=20 + B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + + if (TEWasEnabled && (mVtdUnitInformation[Index].ECapReg.Bits.ADMS=20 + =3D=3D 1) && PcdGetBool (PcdVTdSupportAbortDmaMode)) { + // + // For implementations reporting Enhanced SRTP Support (ESRTPS)=20 + field as + // Clear in the Capability register, software must not modify=20 + this field while + // DMA remapping is active (TES=3D1 in Global Status register). + // + if (mVtdUnitInformation[Index].CapReg.Bits.ESRTPS =3D=3D 0) { + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress,=20 + B_GMCD_REG_TE); + } + + // + // Enable ADM + // + UpdateRootTableAddressRegister (Index, TRUE); + + DEBUG((DEBUG_INFO, "Enable Abort DMA Mode...\n")); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 - if (mVtdUnitInformation[Index].ExtRootEntryTable !=3D NULL) { - DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[= Index].ExtRootEntryTable)); - MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADD= R_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].ExtRootEntryTable | BIT11)= ; } else { - DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[Ind= ex].RootEntryTable)); - MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADD= R_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].RootEntryTable); - } + UpdateRootTableAddressRegister (Index, FALSE); =20 - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Reg32 | B_GMCD_REG_SRTP); + } =20 DEBUG((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n")= ); - do { - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP); =20 // // Init DMAr Fault Event and Data registers @@ -528,15 +632,19 @@ EnableDmar ( // InvalidateIOTLB (Index); =20 + if (TEWasEnabled && (mVtdUnitInformation[Index].ECapReg.Bits.ADMS=20 + =3D=3D 1) && PcdGetBool (PcdVTdSupportAbortDmaMode)) { + if (mVtdUnitInformation[Index].CapReg.Bits.ESRTPS =3D=3D 0) { + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress,=20 + B_GMCD_REG_TE); + } + + UpdateRootTableAddressRegister (Index, FALSE); + } + // // Enable VTd // - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Reg32 | B_GMCD_REG_TE); - DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n")); - do { - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0); + DEBUG ((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n")); + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE); =20 DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index)); } @@ -565,8 +673,6 @@ DisableDmar ( UINTN Index; UINTN SubIndex; UINT32 Reg32; - UINT32 Status; - UINT32 Command; =20 for (Index =3D 0; Index < mVtdUnitNumber; Index++) { DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index)); @@ -582,32 +688,15 @@ DisableDmar ( // // Set TE (Translation Enable: BIT31) of Global command register to ze= ro // - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits - Command =3D (Status & ~B_GMCD_REG_TE); - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); - - // - // Poll on TE Status bit of Global status register to become zero - // - do { - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + ClearGlobalCommandRegisterBits=20 + (mVtdUnitInformation[Index].VtdUnitBaseAddress, B_GMCD_REG_TE); =20 // // Set SRTP (Set Root Table Pointer: BIT30) of Global command register= in order to update the root table pointerDisable VTd // - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits - Command =3D (Status | B_GMCD_REG_SRTP); - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); - - do { - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + SetGlobalCommandRegisterBits=20 + (mVtdUnitInformation[Index].VtdUnitBaseAddress, B_GSTS_REG_RTPS); =20 Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); - DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32)); + DEBUG ((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32)); =20 DEBUG ((DEBUG_INFO,"VTD (%d) Disabled!<<<<<<\n",Index)); =20 diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index c36d130a0..9166e599a 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -135,12 +135,6 @@ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32= |0x0000000A gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|0x00660000|UINT= 32|0x0000000B =20 - ## Indicates if VTd Abort DMA Mode is supported.

- # TRUE - Support VTd abort DMA mode. - # FALSE - Not support VTd abort DMA mode. - # @Prompt VTd abort DMA mode support. - gIntelSiliconPkgTokenSpaceGuid.PcdVTdSupportAbortDmaMode|FALSE|BOOLEAN|0= x0000000C - [PcdsFixedAtBuild, PcdsPatchableInModule] ## Error code for VTd error.

# EDKII_ERROR_CODE_VTD_ERROR =3D (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPE= CIFIC | 0x00000000)) =3D 0x02008000
@@ -178,3 +172,9 @@ # @Prompt The VTd PEI DMA buffer size for S3. gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000|UINT3= 2|0x00000004 =20 + ## Indicates if VTd Abort DMA Mode is supported.

+ # TRUE - Support VTd abort DMA mode. + # FALSE - Not support VTd abort DMA mode. + # @Prompt VTd abort DMA mode support. + =20 + gIntelSiliconPkgTokenSpaceGuid.PcdVTdSupportAbortDmaMode|FALSE|BOOLEAN + |0x0000000C + -- 2.26.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93138): https://edk2.groups.io/g/devel/message/93138 Mute This Topic: https://groups.io/mt/93474620/2558558 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [w.sheng@intel.com] -=3D-=3D-=3D-=3D-=3D-=3D