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a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1551381320; bh=AhZAAMD9K8hnpZs+XzPud3TLPACqjEjm2u2+d/+LEJk=; h=X-PGP-Universal:From:To:Subject:Thread-Topic:Thread-Index:Date: Message-ID:References:In-Reply-To:Accept-Language:X-MS-Has-Attach: X-MS-TNEF-Correlator:msip_labels:authentication-results: x-originating-ip:x-ms-publictraffictype: x-ms-office365-filtering-correlation-id:x-microsoft-antispam: x-ms-traffictypediagnostic:x-ms-exchange-purlcount: x-microsoft-exchange-diagnostics:x-microsoft-antispam-prvs: x-forefront-prvs:x-forefront-antispam-report:received-spf: x-ms-exchange-senderadcheck:x-microsoft-antispam-message-info: MIME-Version:X-MS-Exchange-CrossTenant-Network-Message-Id: X-MS-Exchange-CrossTenant-originalarrivaltime: X-MS-Exchange-CrossTenant-fromentityheader: X-MS-Exchange-CrossTenant-id:X-MS-Exchange-CrossTenant-mailboxtype: X-MS-Exchange-Transport-CrossTenantHeadersStamped:X-OriginatorOrg: Content-Language:Content-Type:Content-Transfer-Encoding; b=pTHB07GN+RkpKtVNottJjl1OA0YO+JKK8syG6hJ7yjtix/101i5ZUaMMtDTXqoEPj 2/85Gq1ApZmDUuvJUblk7xlNOCPGVt6n8B6fsRTLNaO5o6jVwUlXqik/tGAYvr8O1O dTEmlYgalw6D2OAcSdh287hmTP/N+BxtDM3a2luhwLiKpeG/vrFt5eVQaJ39DPXFY1 nIR/o3sWnpoFuFhXUi25VCjU3Mq9ktLie7g1y6qtRh5pIFipvj3U2gP64N8QYJ6Jw8 2PaIA71cF4oTP3M+4vot6sqJqR/yp88OPmoHUGUAI7qlLIVi5YK4HB8huIrUcRkKFX Dz1Kk16Fj2FDA== Subject: Re: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bit systems X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 28 Feb 2019 19:15:12 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello Eugene, My patch enabled support for SDHC 4.0 and above in general including supp= ort for 64b ADMA descriptor. The check for V3 capability for 64b DMA was = already there and similar check was implemented for V4 capability for 64b= =20DMA. Earlier, if any of the V3 controller did not support 64b DMA, we = were not enabling it in PCI layer. With my change, if any of the controll= er did not support 64b DMA in V3 as well as V4 capability, we are not ena= bling it in PCI layer. This check in my opinion is better because we only disable 64b DMA PCI su= pport when both V3 and V4 have it disabled. Thanks Ashish -----Original Message----- From: Cohen, Eugene =20 Sent: Thursday, February 28, 2019 4:24 AM To: Wu, Hao A ; edk2-devel@lists.01.org Cc: Ashish Singhal Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bi= t systems Hao, > I remember the commit b5547b9ce97e80c3127682a2a5d4b9bd14af353e from=20 > Ashish only handles the controllers with version greater or equal to 4.= 00. Right - that commit added support for SDHC 4.0 and above. The original d= river supported SDHC 3.0 albeit only with SDMA and 32-bit ADMA support. With that commit two descriptor types are supported the 32-bit ADMA descr= iptor (SD_MMC_HC_ADMA_32_DESC_LINE which is 64-bits in size) and the V4 6= 4-bit ADMA descriptor (SD_MMC_HC_ADMA_64_DESC_LINE which is 128-bits in s= ize). However the commit mistakenly added a check for the V3 capability for 64-= bit DMA and used it to set the PCI DUAL_ADDRESS_CYCLE attributre which th= en does not the 32-bit compatible bounce buffer mechanism. Later, when w= e attempt an ADMA data transfer we hit an ASSERT because the PCI DMA subs= ystem is not using bounce buffers to provide 32-bit DMA compatible memory= . So the patch I submitted simply removes the unnecessary check of the V= 3 64-bit DMA capability check so the PCI DUAL_ADDRESS_CYCLE attribute is = not set allowing 32-bit DMA to succeed on these platforms. > And the ADMA2 (96-bit Descriptor) mode for V3 controllers is selected=20 > by setting the 'DMA Select' filed in the Host Control 1 Register to=20 > 11b. But the currently behavior of the driver is setting the field to=20 > 10b, which I think will not switch to the ADMA2 (96-bit Descriptor) mod= e for V3. Correct, right now for a V3 controller only 32-bit DMA is supported. An = enhancement for V3 64-bit ADMA would improve performance on controllers t= hat support that mode by eliminating the bounce buffer and associated mem= ory copies. I think we should file a BZ for SD HCI V3 64-bit ADMA suppor= t - if you agree I would be happy to do that. I should point out that we have done extensive testing of this change on = our host controller. Thanks, Eugene --- From: Wu, Hao A Sent: Wednesday, February 27, 2019 8:25 PM To: Cohen, Eugene ; edk2-devel@lists.01.org Cc: Ashish Singhal Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC v3 64-bi= t systems Loop Ashish in. Some comments below. > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of = > Cohen, Eugene > Sent: Wednesday, February 27, 2019 6:59 PM > To: mailto:edk2-devel@lists.01.org; Wu, Hao A > Subject: [edk2] [PATCH] MdeModulePkg/SdMmcPciHcDxe: Fix DMA on SDHC > v3 64-bit systems >=20 > The SdMmcPciHcDriverBindingStart function was checking two different=20 > capability bits in determining whether 64-bit DMA modes were=20 > supported, one mode is defined in the SDHC version > 3 specification (using 96-bit descriptors) and another is defined in=20 > the SDHC version 4 specification (using 128-bit descriptors). Since=20 > the currently implementation of 64-bit > ADMA2 only supports the SDHC version 4 implementation it is incorrect=20 > to check the V3 64-bit capability bit since this will activate V4=20 > ADMA2 on V3 controllers. I remember the commit b5547b9ce97e80c3127682a2a5d4b9bd14af353e from Ashis= h only handles the controllers with version greater or equal to 4.00. And the ADMA2 (96-bit Descriptor) mode for V3 controllers is selected by = setting the 'DMA Select' filed in the Host Control 1 Register to 11b. But= =20the currently behavior of the driver is setting the field to 10b, whic= h I think will not switch to the ADMA2 (96-bit Descriptor) mode for V3. Maybe there is something I miss here. Could you help to provide some more= =20detail on the issue you met? Thanks. Best Regards, Hao Wu >=20 > Cc: Hao Wu > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Eugene Cohen > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > index b474f8d..5bc91c5 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > @@ -666,8 +666,7 @@ SdMmcPciHcDriverBindingStart ( // If any of the=20 > slots does not support 64b system bus // do not enable 64b DMA in the=20 > PCI layer. > // > - if (Private->Capability[Slot].SysBus64V3 =3D=3D 0 && > - Private->Capability[Slot].SysBus64V4 =3D=3D 0) { > + if (Private->Capability[Slot].SysBus64V4 =3D=3D 0) { > Support64BitDma =3D FALSE; > } >=20 > -- > 2.7.4 > _______________________________________________ > edk2-devel mailing list > mailto:edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel -------------------------------------------------------------------------= ---------- This email message is for the sole use of the intended recipient(s) and m= ay contain confidential information. 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