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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hi Hao, That is right. Also, I have addressed your comments and have submitted v2= =20patch. Thanks Ashish -----Original Message----- From: Wu, Hao A =20 Sent: Tuesday, March 5, 2019 8:01 PM To: Ashish Singhal ; edk2-devel@lists.01.org Cc: eugene@hp.com Subject: RE: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Add V3 64b DMA Support Hi Ashish, One thing to confirm, for the updated checks within SdMmcPciHcDriverBindingStart(): > if ((Private->ControllerVersion[Slot] =3D=3D SD_MMC_HC_CTRL_VER_300 &&= > Private->Capability[Slot].SysBus64V3 =3D=3D 0) || > (Private->ControllerVersion[Slot] =3D=3D SD_MMC_HC_CTRL_VER_400 &&= > Private->Capability[Slot].SysBus64V3 =3D=3D 0) || > (Private->ControllerVersion[Slot] >=3D SD_MMC_HC_CTRL_VER_410 && > Private->Capability[Slot].SysBus64V4 =3D=3D 0)) { > Support64BitDma =3D FALSE; > } When the SDHC with version greater than 4.10, the check is only performed= =20against the 'SysBus64V4' bit. My understanding of the purpose is that:= 1. For SDHC with version 4.00, the support of V3 mode and V4 mode of 64-b= it System Address are reflect by bit 'SysBus64V3'. Thus, I can infer that= =20the possible support case is both or neither. 2. The spec states that SDHC with version greater than 4.10 divides the V= 3 mode and V4 mode support into 2 bits (SysBus64V3, SysBus64V4) so that t= he V3 mode support can be optional. So based on 1 & 2, we do not even bother to check the 'SysBus64V3' bit wh= en HC version >=3D 4.10. Is that right? I verified the patch on SDHC version 3.00 with 64-bit System Address Supp= ort. Hope more configurations are available for testing on Eugene's side.= Besides, some minor comments below: > -----Original Message----- > From: Ashish Singhal [mailto:ashishsingha@nvidia.com] > Sent: Saturday, March 02, 2019 2:30 AM > To: edk2-devel@lists.01.org > Cc: Wu, Hao A; eugene@hp.com; Ashish Singhal > Subject: [PATCH] MdeModulePkg/SdMmcPciHcDxe: Add V3 64b DMA Support Please help to add the below Bugzilla tracker for reference: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1583 I have updated the above tracker to match the purpose of the proposed pat= ch. >=20 > Driver was supporting only 32b DMA support for V3 controllers. Add=20 > support for 64b DMA as well for completeness. >=20 > For V4.0 64b support, driver was looking at incorrect capability=20 > register bit. Fix for that is present as well. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ashish Singhal > --- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 10 +- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 +- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 199 > ++++++++++++++------- > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 29 ++- > 4 files changed, 170 insertions(+), 74 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > index b474f8d..9b7b88c 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c > @@ -6,7 +6,7 @@ >=20 > It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use. >=20 > - Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. > + Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. > Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. > This program and the accompanying materials > are licensed and made available under the terms and conditions of=20 > the BSD License @@ -666,8 +666,12 @@ SdMmcPciHcDriverBindingStart ( > // If any of the slots does not support 64b system bus > // do not enable 64b DMA in the PCI layer. > // > - if (Private->Capability[Slot].SysBus64V3 =3D=3D 0 && > - Private->Capability[Slot].SysBus64V4 =3D=3D 0) { > + if ((Private->ControllerVersion[Slot] =3D=3D SD_MMC_HC_CTRL_VER_30= 0 && > + Private->Capability[Slot].SysBus64V3 =3D=3D 0) || > + (Private->ControllerVersion[Slot] =3D=3D SD_MMC_HC_CTRL_VER_40= 0 && > + Private->Capability[Slot].SysBus64V3 =3D=3D 0) || > + (Private->ControllerVersion[Slot] >=3D SD_MMC_HC_CTRL_VER_410 = && > + Private->Capability[Slot].SysBus64V4 =3D=3D 0)) { > Support64BitDma =3D FALSE; > } >=20 > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > index 1bb701a..68d8a5c 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h > @@ -2,7 +2,7 @@ >=20 > Provides some data structure definitions used by the SD/MMC host=20 > controller driver. >=20 > -Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. > +Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. > Copyright (c) 2015, Intel Corporation. All rights reserved.
This = > program and the accompanying materials are licensed and made=20 > available under the terms and conditions of the BSD License @@ -145,13 = > +145,15 @@ typedef struct { > EFI_PHYSICAL_ADDRESS DataPhy; > VOID *DataMap; > SD_MMC_HC_TRANSFER_MODE Mode; > + SD_MMC_HC_ADMA_LEGTH Length; Maybe: SD_MMC_HC_ADMA_LENGTH_MODE AdmaLengthMode; is better to avoid confusion. >=20 > EFI_EVENT Event; > BOOLEAN Started; > UINT64 Timeout; >=20 > SD_MMC_HC_ADMA_32_DESC_LINE *Adma32Desc; > - SD_MMC_HC_ADMA_64_DESC_LINE *Adma64Desc; > + SD_MMC_HC_ADMA_64_V3_DESC_LINE *Adma64V3Desc; > + SD_MMC_HC_ADMA_64_V4_DESC_LINE *Adma64V4Desc; > EFI_PHYSICAL_ADDRESS AdmaDescPhy; > VOID *AdmaMap; > UINT32 AdmaPages; > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > index d73fa10..a6d2395 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > @@ -6,7 +6,7 @@ >=20 > It would expose EFI_SD_MMC_PASS_THRU_PROTOCOL for upper layer use. >=20 > - Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. > + Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. > Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved. > This program and the accompanying materials > are licensed and made available under the terms and conditions of=20 > the BSD License @@ -1010,18 +1010,32 @@ SdMmcHcInitV4Enhancements ( > if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_400) { > HostCtrl2 =3D SD_MMC_HC_V4_EN; > // > - // Check if V4 64bit support is available > + // Check if controller version V4.0 > // > - if (Capability.SysBus64V4 !=3D 0) { > - HostCtrl2 |=3D SD_MMC_HC_64_ADDR_EN; > - DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n")); > + if (ControllerVer =3D=3D SD_MMC_HC_CTRL_VER_400) { > + // > + // Check if 64bit support is available > + // > + if (Capability.SysBus64V3 !=3D 0) { > + HostCtrl2 |=3D SD_MMC_HC_64_ADDR_EN; > + DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"))= ; > + } > } > // > // Check if controller version V4.10 or higher > // > - if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_410) { > - HostCtrl2 |=3D SD_MMC_HC_26_DATA_LEN_ADMA_EN; > - DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA > support\n")); > + else if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_410) { > + // > + // Check if 64bit support is available > + // > + if (Capability.SysBus64V4 !=3D 0) { > + HostCtrl2 |=3D SD_MMC_HC_64_ADDR_EN; > + DEBUG ((DEBUG_INFO, "Enabled V4 64 bit system bus support\n"))= ; > + } > + if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_410) { I think the above 'if' statement can be removed. > + HostCtrl2 |=3D SD_MMC_HC_26_DATA_LEN_ADMA_EN; > + DEBUG ((DEBUG_INFO, "Enabled V4 26 bit data length ADMA > support\n")); > + } > } > Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeo= f=20 > (HostCtrl2), &HostCtrl2); > if (EFI_ERROR (Status)) { > @@ -1393,14 +1407,10 @@ BuildAdmaDescTable ( > EFI_PCI_IO_PROTOCOL *PciIo; > EFI_STATUS Status; > UINTN Bytes; > - BOOLEAN AddressingMode64; > - BOOLEAN DataLength26; > UINT32 AdmaMaxDataPerLine; > UINT32 DescSize; > VOID *AdmaDesc; >=20 > - AddressingMode64 =3D FALSE; > - DataLength26 =3D FALSE; > AdmaMaxDataPerLine =3D ADMA_MAX_DATA_PER_LINE_16B; > DescSize =3D sizeof (SD_MMC_HC_ADMA_32_DESC_LINE); > AdmaDesc =3D NULL; > @@ -1410,27 +1420,16 @@ BuildAdmaDescTable ( > PciIo =3D Trb->Private->PciIo; >=20 > // > - // Detect whether 64bit addressing is supported. > - // > - if (ControllerVer >=3D SD_MMC_HC_CTRL_VER_400) { > - Status =3D SdMmcHcCheckMmioSet(PciIo, Trb->Slot, > SD_MMC_HC_HOST_CTRL2, sizeof(UINT16), > - SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN,= > SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN); > - if (!EFI_ERROR (Status)) { > - AddressingMode64 =3D TRUE; > - DescSize =3D sizeof (SD_MMC_HC_ADMA_64_DESC_LINE); > - } > - } > - // > // Check for valid ranges in 32bit ADMA Descriptor Table > // > - if (!AddressingMode64 && > + if ((Trb->Mode =3D=3D SdMmcAdma32bMode) && > ((Data >=3D 0x100000000ul) || ((Data + DataLen) > 0x100000000ul)= )) { > return EFI_INVALID_PARAMETER; > } > // > // Check address field alignment > // > - if (AddressingMode64) { > + if (Trb->Mode !=3D SdMmcAdma32bMode) { > // > // Address field shall be set on 64-bit boundary (Lower 3-bit is=20 > always set to 0) > // > @@ -1445,13 +1444,19 @@ BuildAdmaDescTable ( > DEBUG ((DEBUG_INFO, "The buffer [0x%x] to construct ADMA desc=20 > is not aligned to 4 bytes boundary!\n", Data)); > } > } > + > // > - // Detect whether 26bit data length is supported. > + // Configure 64b ADMA. > // > - Status =3D SdMmcHcCheckMmioSet(PciIo, Trb->Slot,=20 > SD_MMC_HC_HOST_CTRL2, sizeof(UINT16), > - SD_MMC_HC_26_DATA_LEN_ADMA_EN, > SD_MMC_HC_26_DATA_LEN_ADMA_EN); > - if (!EFI_ERROR (Status)) { > - DataLength26 =3D TRUE; > + if (Trb->Mode =3D=3D SdMmcAdma64bV3Mode) { > + DescSize =3D sizeof (SD_MMC_HC_ADMA_64_V3_DESC_LINE); }else if=20 > + (Trb->Mode =3D=3D SdMmcAdma64bV4Mode) { > + DescSize =3D sizeof (SD_MMC_HC_ADMA_64_V4_DESC_LINE); } // //=20 > + Configure 26b data length. > + // > + if (Trb->Length =3D=3D SdMmcAdmaLen26b) { > AdmaMaxDataPerLine =3D ADMA_MAX_DATA_PER_LINE_26B; > } >=20 > @@ -1492,7 +1497,7 @@ BuildAdmaDescTable ( > return EFI_OUT_OF_RESOURCES; > } >=20 > - if ((!AddressingMode64) && > + if ((Trb->Mode =3D=3D SdMmcAdma32bMode) && > (UINT64)(UINTN)Trb->AdmaDescPhy > 0x100000000ul) { > // > // The ADMA doesn't support 64bit addressing. > @@ -1511,19 +1516,26 @@ BuildAdmaDescTable ( >=20 > Remaining =3D DataLen; > Address =3D Data; > - if (!AddressingMode64) { > + if (Trb->Mode =3D=3D SdMmcAdma32bMode) { > Trb->Adma32Desc =3D AdmaDesc; > - Trb->Adma64Desc =3D NULL; > + Trb->Adma64V3Desc =3D NULL; > + Trb->Adma64V4Desc =3D NULL; > + } else if (Trb->Mode =3D=3D SdMmcAdma64bV3Mode) { > + Trb->Adma64V3Desc =3D AdmaDesc; > + Trb->Adma32Desc =3D NULL; > + Trb->Adma64V4Desc =3D NULL; > } else { > - Trb->Adma64Desc =3D AdmaDesc; > + Trb->Adma64V4Desc =3D AdmaDesc; > Trb->Adma32Desc =3D NULL; > + Trb->Adma64V3Desc =3D NULL; > } Suggest to remove those NULL assignments to: Trb->Adma32Desc Trb->Adma64Desc Trb->Adma64V3Desc Since in SdMmcCreateTrb(), 'Trb' is allocated by: =20 Trb =3D AllocateZeroPool (sizeof (SD_MMC_HC_TRB)); > + > for (Index =3D 0; Index < Entries; Index++) { > - if (!AddressingMode64) { > + if (Trb->Mode =3D=3D SdMmcAdma32bMode) { > if (Remaining <=3D AdmaMaxDataPerLine) { > Trb->Adma32Desc[Index].Valid =3D 1; > Trb->Adma32Desc[Index].Act =3D 2; > - if (DataLength26) { > + if (Trb->Length =3D=3D SdMmcAdmaLen26b) { > Trb->Adma32Desc[Index].UpperLength =3D (UINT16)RShiftU64=20 > (Remaining, 16); > } > Trb->Adma32Desc[Index].LowerLength =3D (UINT16)(Remaining &=20 > MAX_UINT16); @@ -1532,32 +1544,53 @@ BuildAdmaDescTable ( > } else { > Trb->Adma32Desc[Index].Valid =3D 1; > Trb->Adma32Desc[Index].Act =3D 2; > - if (DataLength26) { > + if (Trb->Length =3D=3D SdMmcAdmaLen26b) { > Trb->Adma32Desc[Index].UpperLength =3D 0; > } > Trb->Adma32Desc[Index].LowerLength =3D 0; > Trb->Adma32Desc[Index].Address =3D (UINT32)Address; > } > + } else if (Trb->Mode =3D=3D SdMmcAdma64bV3Mode) { > + if (Remaining <=3D AdmaMaxDataPerLine) { > + Trb->Adma64V3Desc[Index].Valid =3D 1; > + Trb->Adma64V3Desc[Index].Act =3D 2; > + if (Trb->Length =3D=3D SdMmcAdmaLen26b) { > + Trb->Adma64V3Desc[Index].UpperLength =3D (UINT16)RShiftU64 > (Remaining, 16); > + } > + Trb->Adma64V3Desc[Index].LowerLength =3D (UINT16)(Remaining &= > MAX_UINT16); > + Trb->Adma64V3Desc[Index].LowerAddress =3D (UINT32)Address; > + Trb->Adma64V3Desc[Index].UpperAddress =3D (UINT32)RShiftU64 > (Address, 32); > + break; > + } else { > + Trb->Adma64V3Desc[Index].Valid =3D 1; > + Trb->Adma64V3Desc[Index].Act =3D 2; > + if (Trb->Length =3D=3D SdMmcAdmaLen26b) { > + Trb->Adma64V3Desc[Index].UpperLength =3D 0; > + } > + Trb->Adma64V3Desc[Index].LowerLength =3D 0; > + Trb->Adma64V3Desc[Index].LowerAddress =3D (UINT32)Address; > + Trb->Adma64V3Desc[Index].UpperAddress =3D (UINT32)RShiftU64 > (Address, 32); > + } > } else { > if (Remaining <=3D AdmaMaxDataPerLine) { > - Trb->Adma64Desc[Index].Valid =3D 1; > - Trb->Adma64Desc[Index].Act =3D 2; > - if (DataLength26) { > - Trb->Adma64Desc[Index].UpperLength =3D (UINT16)RShiftU64 > (Remaining, 16); > + Trb->Adma64V4Desc[Index].Valid =3D 1; > + Trb->Adma64V4Desc[Index].Act =3D 2; > + if (Trb->Length =3D=3D SdMmcAdmaLen26b) { > + Trb->Adma64V4Desc[Index].UpperLength =3D (UINT16)RShiftU64 > (Remaining, 16); > } > - Trb->Adma64Desc[Index].LowerLength =3D (UINT16)(Remaining & > MAX_UINT16); > - Trb->Adma64Desc[Index].LowerAddress =3D (UINT32)Address; > - Trb->Adma64Desc[Index].UpperAddress =3D (UINT32)RShiftU64 (Add= ress, > 32); > + Trb->Adma64V4Desc[Index].LowerLength =3D (UINT16)(Remaining &= > MAX_UINT16); > + Trb->Adma64V4Desc[Index].LowerAddress =3D (UINT32)Address; > + Trb->Adma64V4Desc[Index].UpperAddress =3D (UINT32)RShiftU64 > (Address, 32); > break; > } else { > - Trb->Adma64Desc[Index].Valid =3D 1; > - Trb->Adma64Desc[Index].Act =3D 2; > - if (DataLength26) { > - Trb->Adma64Desc[Index].UpperLength =3D 0; > + Trb->Adma64V4Desc[Index].Valid =3D 1; > + Trb->Adma64V4Desc[Index].Act =3D 2; > + if (Trb->Length =3D=3D SdMmcAdmaLen26b) { > + Trb->Adma64V4Desc[Index].UpperLength =3D 0; > } > - Trb->Adma64Desc[Index].LowerLength =3D 0; > - Trb->Adma64Desc[Index].LowerAddress =3D (UINT32)Address; > - Trb->Adma64Desc[Index].UpperAddress =3D (UINT32)RShiftU64 (Add= ress, > 32); > + Trb->Adma64V4Desc[Index].LowerLength =3D 0; > + Trb->Adma64V4Desc[Index].LowerAddress =3D (UINT32)Address; > + Trb->Adma64V4Desc[Index].UpperAddress =3D (UINT32)RShiftU64 > (Address, 32); > } > } >=20 > @@ -1568,7 +1601,13 @@ BuildAdmaDescTable ( > // > // Set the last descriptor line as end of descriptor table > // > - AddressingMode64 ? (Trb->Adma64Desc[Index].End =3D 1) : (Trb- > >Adma32Desc[Index].End =3D 1); > + if (Trb->Mode =3D=3D SdMmcAdma32bMode) { > + Trb->Adma32Desc[Index].End =3D 1; > + } else if (Trb->Mode =3D=3D SdMmcAdma64bV3Mode) { > + Trb->Adma64V3Desc[Index].End =3D 1; } else { > + Trb->Adma64V4Desc[Index].End =3D 1; } > return EFI_SUCCESS; > } >=20 > @@ -1665,7 +1704,20 @@ SdMmcCreateTrb ( > if (Trb->DataLen =3D=3D 0) { > Trb->Mode =3D SdMmcNoData; > } else if (Private->Capability[Slot].Adma2 !=3D 0) { > - Trb->Mode =3D SdMmcAdmaMode; > + Trb->Mode =3D SdMmcAdma32bMode; > + Trb->Length =3D SdMmcAdmaLen16b; > + if ((Private->ControllerVersion[Slot] =3D=3D=20 > + SD_MMC_HC_CTRL_VER_300) > && > + (Private->Capability[Slot].SysBus64V3 =3D=3D 1)) { > + Trb->Mode =3D SdMmcAdma64bV3Mode; > + } else if (((Private->ControllerVersion[Slot] =3D=3D > SD_MMC_HC_CTRL_VER_400) && > + (Private->Capability[Slot].SysBus64V3 =3D=3D 1)) || > + ((Private->ControllerVersion[Slot] >=3D=20 > + SD_MMC_HC_CTRL_VER_410) > && > + (Private->Capability[Slot].SysBus64V4 =3D=3D 1))) { > + Trb->Mode =3D SdMmcAdma64bV4Mode; > + } > + if (Private->ControllerVersion[Slot] >=3D SD_MMC_HC_CTRL_VER_410= ) { > + Trb->Length =3D SdMmcAdmaLen26b; > + } > Status =3D BuildAdmaDescTable (Trb, Private->ControllerVersion[S= lot]); > if (EFI_ERROR (Status)) { > PciIo->Unmap (PciIo, Trb->DataMap); @@ -1719,11 +1771,18 @@=20 > SdMmcFreeTrb ( > Trb->Adma32Desc > ); > } > - if (Trb->Adma64Desc !=3D NULL) { > + if (Trb->Adma64V3Desc !=3D NULL) { > + PciIo->FreeBuffer ( > + PciIo, > + Trb->AdmaPages, > + Trb->Adma64V3Desc > + ); > + } > + if (Trb->Adma64V4Desc !=3D NULL) { > PciIo->FreeBuffer ( > PciIo, > Trb->AdmaPages, > - Trb->Adma64Desc > + Trb->Adma64V4Desc > ); > } > if (Trb->DataMap !=3D NULL) { > @@ -1891,27 +1950,35 @@ SdMmcExecTrb ( > if (EFI_ERROR (Status)) { > return Status; > } > + > + if (Private->ControllerVersion[Trb->Slot] >=3D=20 > + SD_MMC_HC_CTRL_VER_400) > { > + Status =3D SdMmcHcCheckMmioSet(PciIo, Trb->Slot, > SD_MMC_HC_HOST_CTRL2, sizeof(UINT16), > + SD_MMC_HC_64_ADDR_EN, SD_MMC_HC_64_AD= DR_EN); > + if (!EFI_ERROR (Status)) { > + AddressingMode64 =3D TRUE; > + } > + } > + > // > // Set Host Control 1 register DMA Select field > // > - if (Trb->Mode =3D=3D SdMmcAdmaMode) { > + if ((Trb->Mode =3D=3D SdMmcAdma32bMode) || > + (Trb->Mode =3D=3D SdMmcAdma64bV4Mode)) { > HostCtrl1 =3D BIT4; > Status =3D SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, = > sizeof (HostCtrl1), &HostCtrl1); > if (EFI_ERROR (Status)) { > return Status; > } > + } else if (Trb->Mode =3D=3D SdMmcAdma64bV3Mode) { > + HostCtrl1 =3D BIT4|BIT3; > + Status =3D SdMmcHcOrMmio (PciIo, Trb->Slot, SD_MMC_HC_HOST_CTRL1, > sizeof (HostCtrl1), &HostCtrl1); > + if (EFI_ERROR (Status)) { > + return Status; > + } > } >=20 > SdMmcHcLedOnOff (PciIo, Trb->Slot, TRUE); >=20 > - if (Private->ControllerVersion[Trb->Slot] >=3D=20 > SD_MMC_HC_CTRL_VER_400) { > - Status =3D SdMmcHcCheckMmioSet(PciIo, Trb->Slot, > SD_MMC_HC_HOST_CTRL2, sizeof(UINT16), > - SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN,= > SD_MMC_HC_V4_EN|SD_MMC_HC_64_ADDR_EN); > - if (!EFI_ERROR (Status)) { > - AddressingMode64 =3D TRUE; > - } > - } > - > if (Trb->Mode =3D=3D SdMmcSdmaMode) { > if ((!AddressingMode64) && > ((UINT64)(UINTN)Trb->DataPhy >=3D 0x100000000ul)) { @@ -1929,7= =20 > +1996,9 @@ SdMmcExecTrb ( > if (EFI_ERROR (Status)) { > return Status; > } > - } else if (Trb->Mode =3D=3D SdMmcAdmaMode) { > + } else if ((Trb->Mode =3D=3D SdMmcAdma32bMode) || > + (Trb->Mode =3D=3D SdMmcAdma64bV3Mode) || > + (Trb->Mode =3D=3D SdMmcAdma64bV4Mode)) { > AdmaAddr =3D (UINT64)(UINTN)Trb->AdmaDescPhy; > Status =3D SdMmcHcRwMmio (PciIo, Trb->Slot, > SD_MMC_HC_ADMA_SYS_ADDR, FALSE, sizeof (AdmaAddr), &AdmaAddr); > if (EFI_ERROR (Status)) { > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > index d157f2c..3a05456 100644 > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > @@ -2,7 +2,7 @@ >=20 > Provides some data structure definitions used by the SD/MMC host=20 > controller driver. >=20 > -Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. > +Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. > Copyright (c) 2015, Intel Corporation. All rights reserved.
This = > program and the accompanying materials are licensed and made=20 > available under the terms and conditions of the BSD License @@ -80,16=20 > +80,25 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER=20 > EXPRESS OR IMPLIED. >=20 > // > // The transfer modes supported by SD Host Controller -// Simplified=20 > Spec 3.0 Table 1-2 // typedef enum { > SdMmcNoData, > SdMmcPioMode, > SdMmcSdmaMode, > - SdMmcAdmaMode > + SdMmcAdma32bMode, > + SdMmcAdma64bV3Mode, > + SdMmcAdma64bV4Mode > } SD_MMC_HC_TRANSFER_MODE; >=20 > // > +// The ADMA transfer lengths supported by SD Host Controller //=20 > +typedef enum { > + SdMmcAdmaLen16b, > + SdMmcAdmaLen26b > +} SD_MMC_HC_ADMA_LEGTH; Typo 'LEGTH' -> 'LENGTH' Also, how about 'SD_MMC_HC_ADMA_LENGTH_MODE'? Best Regards, Hao Wu > + > +// > // The maximum data length of each descriptor line // > #define ADMA_MAX_DATA_PER_LINE_16B SIZE_64KB > @@ -122,8 +131,20 @@ typedef struct { > UINT32 LowerLength:16; > UINT32 LowerAddress; > UINT32 UpperAddress; > +} SD_MMC_HC_ADMA_64_V3_DESC_LINE; > + > +typedef struct { > + UINT32 Valid:1; > + UINT32 End:1; > + UINT32 Int:1; > + UINT32 Reserved:1; > + UINT32 Act:2; > + UINT32 UpperLength:10; > + UINT32 LowerLength:16; > + UINT32 LowerAddress; > + UINT32 UpperAddress; > UINT32 Reserved1; > -} SD_MMC_HC_ADMA_64_DESC_LINE; > +} SD_MMC_HC_ADMA_64_V4_DESC_LINE; >=20 > #define SD_MMC_SDMA_BOUNDARY 512 * 1024 > #define SD_MMC_SDMA_ROUND_UP(x, n) (((x) + n) & ~(n - 1)) > -- > 2.7.4 -------------------------------------------------------------------------= ---------- This email message is for the sole use of the intended recipient(s) and m= ay contain confidential information. Any unauthorized review, use, disclosure or di= stribution is prohibited. If you are not the intended recipient, please contact the= =20sender by reply email and destroy all copies of the original message. -------------------------------------------------------------------------= ----------