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23 Oct 2024 10:00:15 -0700 Resent-From: foster.nong@intel.com Reply-To: devel@edk2.groups.io,foster.nong@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: xCbQ5yuvDtyWVnsLMWPpql6Mx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20240830 header.b=UW1fqh0L; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 45.79.224.7 as permitted sender) smtp.mailfrom=bounce@groups.io V2 is fix the coding style issue. Below is PR. https://github.com/tianocore/edk2/pull/6342 -----Original Message----- From: Nong, Foster =20 Sent: Friday, October 18, 2024 8:55 AM To: devel@edk2.groups.io Cc: Nong, Foster ; Kinney, Michael D ; Liming Gao ; Ni, Ray Subject: [PATCH v2 2/2] MdeModulePkg:New Pcd to platform constrain BarSize REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4868 1. Define a new dynamic PCD in MdeModulePkg gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableMaxBarSize 2. Modify PciProgramResizableBar() to implement configure BAR Size within platform constrain provided in PcdPcieResizableMaxBarSize Signed-off-by: Foster Nong Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 25 +++++++++++++++++--- MdeModulePkg/MdeModulePkg.dec | 5 ++++ 3 files changed, 28 insertions(+), 3 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bu= s/Pci/PciBusDxe/PciBusDxe.inf index e317169d9c..f038b6eef2 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -107,6 +107,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## CONSUME= S gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## SOMETIM= ES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport ## CONSUME= S + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableMaxBarSize ## CONSUME= S =20 [UserExtensions.TianoCore."ExtraFiles"] PciBusDxeExtra.uni diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciLib.c index dc5fd27665..95f331d0af 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c @@ -1797,6 +1797,7 @@ PciProgramResizableBar ( { EFI_PCI_IO_PROTOCOL *PciIo; UINT64 Capabilities; + UINT64 CapabilitiesMask; UINT32 Index; UINT32 Offset; INTN Bit; @@ -1804,12 +1805,17 @@ PciProgramResizableBar ( PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Entries[PCI_MAX_B= AR]; =20 ASSERT (PciIoDevice->ResizableBarOffset !=3D 0); - + // + // PCIE SPEC v6.0 section 7.8.6.3 Resizable BAR Control Register + // Bits[13:8] BAR Size define 43(8 EB) as maximum + // + CapabilitiesMask =3D LShiftU64 (1, MIN (PcdGet8 (PcdPcieResizableMaxBarS= ize), 43) + 1) - 1; DEBUG (( DEBUG_INFO, - " Programs Resizable BAR register, offset: 0x%08x, number: %d\n", + " Programs Resizable BAR register, offset: 0x%08x, number: %d, PcdPc= ieResizableMaxBarSize: %d\n", PciIoDevice->ResizableBarOffset, - PciIoDevice->ResizableBarNumber + PciIoDevice->ResizableBarNumber, + PcdGet8 (PcdPcieResizableMaxBarSize) )); =20 if ((PciIoDevice->ResizableBarNumber > PCI_MAX_BAR) || (PciIoDevice->Res= izableBarNumber =3D=3D 0)) { @@ -1853,9 +1859,22 @@ PciProgramResizableBar ( // Bit 0 is set: supports operating with the BAR sized to 1 MB // Bit 1 is set: supports operating with the BAR sized to 2 MB // Bit n is set: supports operating with the BAR sized to (2^n) MB + // Platform may impose limitation on the BAR size it supports using Pc= dPcieResizableMaxBarSize. // Capabilities =3D LShiftU64 (Entries[Index].ResizableBarControl.Bits.Ba= rSizeCapability, 28) | Entries[Index].ResizableBarCapability.Bits.BarSizeCap= ability; + Capabilities &=3D CapabilitiesMask; + + if (Capabilities =3D=3D 0) { + DEBUG (( + DEBUG_ERROR, + " WARNING: Resizable BAR Entry[%d] skip, Capabilities=3D0x%llx Cap= abilitiesMask=3D0x%llx\n", + Index, + Entries[Index].ResizableBarCapability.Bits.BarSizeCapability, + CapabilitiesMask + )); + continue; + } =20 if (ResizableBarOp =3D=3D PciResizableBarMax) { Bit =3D HighBitSet64 (Capabilities); diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 1324b6d100..59fa506bd8 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2264,6 +2264,11 @@ # @Prompt The value is use for Usb Network rate limiting supported. gEfiMdeModulePkgTokenSpaceGuid.PcdUsbNetworkRateLimitingFactor|100|UINT3= 2|0x10000028 =20 + # This PCD set maximum size of all PCIE Resizable BARs + # The max size equals to (2^PcdPcieResizableMaxBarSize) MB + # @Prompt Maximum size of PCIE Resizable BARs + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableMaxBarSize|0x2B|UINT8|0x0= 0030009 + [PcdsPatchableInModule] ## Specify memory size with page number for PEI code when # Loading Module at Fixed Address feature is enabled. --=20 2.37.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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