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Thanks! -----Original Message----- From: Nong, Foster =20 Sent: Wednesday, November 29, 2023 2:57 PM To: devel@edk2.groups.io Cc: Nong, Foster ; Kinney, Michael D ; Gao, Liming ; Ni, Ray ; Chris Li Subject: [PATCH v1] MdePkg: Add Cxl30.h into IndustryStandard REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4516 1) Add CXL 3.0 header file to comply with CXL 3.0 specification 2) CXL 3.0 header will embed Cxl20.h 3) Updated Cxl.h to point to 3.0 header file Signed-off-by: Foster Nong Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni Cc: Chris Li --- MdePkg/Include/IndustryStandard/Cxl.h | 2 +- MdePkg/Include/IndustryStandard/Cxl30.h | 315 ++++++++++++++++++++ 2 files changed, 316 insertions(+), 1 deletion(-) diff --git a/MdePkg/Include/IndustryStandard/Cxl.h b/MdePkg/Include/Industr= yStandard/Cxl.h index 9ad3242e25..cb623a355d 100755 --- a/MdePkg/Include/IndustryStandard/Cxl.h +++ b/MdePkg/Include/IndustryStandard/Cxl.h @@ -12,7 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #ifndef _CX= L_MAIN_H_ #define _CXL_MAIN_H_ -#include +#includ= e // // CXL assigned new Vendor ID //diff --git = a/MdePkg/Include/IndustryStandard/Cxl30.h b/MdePkg/Include/IndustryStandard= /Cxl30.h new file mode 100644 index 0000000000..feb6b9c52f --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Cxl30.h @@ -0,0 +1,315 @@ +/** @file+ CXL 3.0 Register definitions++ This file contains the registe= r definitions based on the Compute Express Link+ (CXL) Specification Revis= ion 3.0.++ Copyright (c) 2023, Intel Corporation. All rights reserved.
= ++ SPDX-License-Identifier: BSD-2-Clause-Patent++**/+#ifndef CXL30_H_+#def= ine CXL30_H_++#include ++//+// CXL Cache Memory C= apability IDs+// Compute Express Link Specification Revision 3.0 - Chapter = 8.2.4 Table 8-22+//+#define CXL_CACHE_MEM_CAPABILITY_ID_TIMEOUT_AND_ISOLATI= ON 0x0009+#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED = 0x000A+#define CXL_CACHE_MEM_CAPABILITY_ID_BI_ROUTE_TABLE = 0x000B+#define CXL_CACHE_MEM_CAPABILITY_ID_BI_DECODER = 0x000C+#define CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_ROUTE_TABLE = 0x000D+#define CXL_CACHE_MEM_CAPABILITY_ID_CACHE_ID_DECODER = 0x000E+#define CXL_CACHE_MEM_CAPABILITY_ID_EXTENDED_HDM_DECODER = 0x000F++//+// CXL_Capability_Version+// Compute Express ink Specifica= tion Revision 3.0 - Chapter 8.2.4.5+//+#define CXL_HDM_DECODER_VERSION_30 = 0x3++//+// CXL CXL HDM Decoder n Control+// = Compute Express Link Specification Revision 3.0 - 8.2.4.19.7+//+//+// Bit4.= .7: Interleave Ways (IW)+//+#define CXL_HDM_16_WAY_INTERLEAVING = 0x4+#define CXL_HDM_3_WAY_INTERLEAVING = 0x8+#define CXL_HDM_6_WAY_INTERLEAVING = 0x9+#define CXL_HDM_12_WAY_INTERLEAVING = 0xA++//+// Ensure proper structure formats+//+#pragma pack(1)++//+// CX= L.cachemem Extended Register Capability+// Compute Express Link Specificati= on Revision 3.0 - Chapter 8.2.4.24+//+typedef union {+ struct {+ UINT3= 2 ExtendedRangesBitmap : 16; // Bit 0..15+ UINT32 Reserve= d : 16; // Bit 16..31+ } Bits;+ UINT32 Uint32;+} CX= L_CM_EXTENTED_REGISTER_CAPABILITY;++#define CXL_CM_EXTENTED_RANGES_BITMAP = (BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7 | BIT8 | BIT9 | BIT10 | BIT11 | = BIT12 | BIT13 | BIT15)++//+// CXL BI Route Table Capability+// Compute Expr= ess Link Specification Revision 3.0 - Chapter 8.2.4.25+//+typedef union {+= struct {+ UINT32 ExplicitBiRtCommitRequired :1; /= / bit 0+ UINT32 Reserved :31; // b= it 1..31+ } Bits;+ UINT32 Uint32;+} CXL_BI_RT_CAPABILITY;++typedef uni= on {+ struct {+ UINT32 BiRtCommit := 1; // bit 0+ UINT32 Reserved :31= ; // bit 1..31+ } Bits;+ UINT32 Uint32;+} CXL_BI_RT_CONTROL;++typedef= union {+ struct {+ UINT32 BiRtCommitted = :1; // bit 0+ UINT32 BiRtErrorNotCommitted = :1; // bit 1+ UINT32 Reserved1 :6;= // bit 2..7+ UINT32 BiRtCommitTimeoutScale :4;= // bit 8..11+ UINT32 BiRtCommitTimeoutBase :4= ; // bit 12..15+ UINT32 Reserved2 = :16; // bit 16..31+ } Bits;+ UINT32 Uint32;+} CXL_BI_RT_STATUS;++typed= ef struct {+ CXL_BI_RT_CAPABILITY BiRtC= ap; // offset 0x00+ CXL_BI_RT_CONTROL = BiRtControl; // offset 0x04+ CXL_BI_RT_STATUS = BiRtStatus; // offset 0x08+} CXL_BI_ROUTE_TABLE_CAP= ABILITY;++//+// CXL BI Decoder Capability+// Compute Express Link Specifica= tion Revision 3.0 - Chapter 8.2.4.26+//+typedef union {+ struct {+ UIN= T32 HdmDCapable :1; // bit 0+ UINT32= ExplicitBiDecoderCommitRequired :1; // bit 1+ UINT32 R= eserved :30; // bit 2..31+ } Bits;+ = UINT32 Uint32;+} CXL_BI_DECODER_CAP;++typedef union {+ struct {+ UIN= T32 BiForward :1; // bit 0+ UINT32= BiEnable :1; // bit 1+ UINT32 B= iDecoderCommit :1; // bit 2+ UINT32 Rese= rved :29; // bit 3..31+ } Bits;+ UIN= T32 Uint32;+} CXL_BI_DECODER_CONTROL;++typedef union {+ struct {+ UI= NT32 BiDecoderCommitted :1; // bit 0+ UINT3= 2 BiDecoderErrorNotCommitted :1; // bit 1+ UINT32 = Reserved1 :6; // bit 2..7+ UINT32 = BiDecoderCommitTimeoutScale :4; // bit 8..11+ UINT32 = BiDecoderCommitTimeoutBase :4; // bit 12..15+ UINT3= 2 Reserved2 :16; // bit 16..31+ } Bit= s;+ UINT32 Uint32;+} CXL_BI_DECODER_STATUS;++typedef struct {+ CXL_BI_= DECODER_CAP BiDecoderCap; // offse= t 0x00+ CXL_BI_DECODER_CONTROL BiDecoderControl; = // offset 0x04+ CXL_BI_DECODER_STATUS Bi= DecoderStatus; // offset 0x08+} CXL_BI_DECODER_CAPABILITY;++//+// = CXL Cache ID Route Table Capability+// Compute Express Link Specification R= evision 3.0 - Chapter 8.2.4.27+//+typedef union {+ struct {+ UINT32 = CacheIdTargetCount : 5; // Bit 0..4+ UINT32 = Reserved1 : 3; // Bit 5..7+ UINT32 = HdmDType2DeviceMaxCount : 4; // Bit 8..11+ UINT32 = Reserved2 : 4; // Bit 12..15+ UINT32 = ExplicitCacheIdRtCommitRequired : 1; // Bit 16+ UINT32 = Reserved3 : 15; // Bit 17:31+ } Bits;+ UINT3= 2 Uint32;+} CXL_CACHE_ID_RT_CAPABILITY;++typedef union {+ struct = {+ UINT32 CacheIdRtCommit : 1; // Bit 0+ UINT32 = Reserved : 31; // Bit 1..31+ } Bits;+ UINT32 = Uint32;+} CXL_CACHE_ID_RT_CONTROL;++typedef union {+ struct {+ = UINT32 CacheIdRtCommitted : 1; // Bit 0+ UINT32 = CacheIdRtErrNotCommitted : 1; // Bit 1+ UINT32 Reserved1 = : 6; // Bit 2..7+ UINT32 CacheIdRtCommitTimeout= Scale : 4; // Bit 8..11+ UINT32 CacheIdRtCommitTimeoutBase : 4= ; // Bit 12..15+ UINT32 Reserved2 : 16; // B= it 16..31+ } Bits;+ UINT32 Uint32;+} CXL_CACHE_ID_RT_STATUS;++ty= pedef union {+ struct {+ UINT16 Valid : 1;= // Bit 0+ UINT16 Reserved : 7; // Bit 1..7+= UINT16 PortNumber : 8; // Bit 8..15+ } Bits;+= UINT16 Uint16;+} CXL_CACHE_ID_RT_TARGET;++typedef struct {+ CXL= _CACHE_ID_RT_CAPABILITY CacheIdRtCap; // offset 0x00+ CXL= _CACHE_ID_RT_CONTROL CacheIdRtControl; // offset 0x04+ CXL= _CACHE_ID_RT_STATUS CacheIdRtStatus; // offset 0x08+ UIN= T32 Reserved; // offset 0x0C+ CXL= _CACHE_ID_RT_TARGET CacheIdRtTarget[]; // offset 0x10+} CXL= _CACHE_ID_ROUTE_TABLE_CAPABILITY;++//+// CXL Cache ID Decoder Capability+//= Compute Express Link Specification Revision 3.0 - Chapter 8.2.4.28+//+typ= edef union {+ struct {+ UINT32 ExplicitCacheIdDecoderCommitRequi= red : 1; // Bit 0+ UINT32 Reserved = : 31; // Bit 1..31+ } Bits;+ UINT32 Uint32;+} CXL_CAC= HE_ID_DECODER_CAP;++typedef union {+ struct {+ UINT32 ForwardCac= heId : 1; // Bit 0+ UINT32 AssignCacheId = : 1; // Bit 1+ UINT32 HdmDType2DevicePresent : 1; // B= it 2+ UINT32 CacheIdDecoderCommit : 1; // Bit 3+ UINT3= 2 Reserved1 : 4; // Bit 4..7+ UINT32 Hd= mDType2DeviceCacheId : 4; // Bit 8..11+ UINT32 Reserved2 = : 4; // Bit 12..15+ UINT32 LocalCacheId = : 4; // Bit 16..19+ UINT32 Reserved3 : = 4; // Bit 20..23+ UINT32 TrustLevel : 2; // Bi= t 24..25+ UINT32 Reserved4 : 6; // Bit 26..31+= } Bits;+ UINT32 Uint32;+} CXL_CACHE_ID_DECODER_CONTROL;++typede= f union {+ struct {+ UINT32 CacheIdDecoderCommitted = : 1; // Bit 0+ UINT32 CacheIdDecoderErrorNotCommitted : 1= ; // Bit 1+ UINT32 Reserved1 : 6; = // Bit 2..7+ UINT32 CacheIdDecoderCommitTimeoutScale : 4; /= / Bit 8..11+ UINT32 CacheIdDecoderCommitTimeoutBase : 4; /= / Bit 12..15+ UINT32 Reserved2 : 16; = // Bit 16..31+ } Bits;+ UINT32 Uint32;+} CXL_CACHE_ID_DECODER_ST= ATUS;++typedef struct {+ CXL_CACHE_ID_DECODER_CAP CacheIdDecode= rCap; // offset 0x00+ CXL_CACHE_ID_DECODER_CONTROL CacheIdDec= oderControl; // offset 0x04+ CXL_CACHE_ID_DECODER_STATUS CacheId= DecoderStatus; // offset 0x08+} CXL_CACHE_ID_DECODER_CAPABILITY;++//+// = CXL Timeout and Isolation Capability Structure+// Compute Express Link Spec= ification Revision 3.0 - Chapter 8.2.4.23+//+typedef union {+ struct {+ = UINT32 CxlmemTransactionTimeoutRangesSupported : 4; // Bits 3:0+ UI= NT32 CxlmemTransactionTimeoutSupported : 1; // Bits 4+ UINT32 R= eserved1 : 3; // Bits 7:5+ UINT32 Cxlca= cheTransactionTimeoutRangesSupported : 4; // Bits 11:8+ UINT32 Cxlcache= TransactionTimeoutSupported : 1; // Bits 12+ UINT32 Reserved2 = : 3; // Bits 15:13+ UINT32 CxlmemIsolation= Supported : 1; // Bits 16+ UINT32 CxlmemIsolationLinkd= ownSupported : 1; // Bits 17+ UINT32 CxlcacheIsolationSupporte= d : 1; // Bits 18+ UINT32 CxlcacheIsolationLinkdownSuppo= rted : 1; // Bits 19+ UINT32 Reserved3 = : 5; // Bits 24:20+ UINT32 IsolationErrCorSignalingSupported = : 1; // Bits 25+ UINT32 IsolationInterruptSupported = : 1; // Bits 26+ UINT32 IsolationInterruptMessageNumber : 5; = // Bits 31:27+ } Bits;+ UINT32 = Data32;+} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY;++typedef union {= + struct {+ UINT32 CxlmemTransactionTimeoutValue : 4; // Bits 3:0+ = UINT32 CxlmemTransactionTimeoutEnable : 1; // Bits 4+ UINT32 Reser= ved1 : 3; // Bits 7:5+ UINT32 CxlcacheTransactio= nTimeoutValue : 4; // Bits 11:8+ UINT32 CxlcacheTransactionTimeoutEnab= le : 1; // Bits 12+ UINT32 Reserved2 : 3; // Bi= ts 15:13+ UINT32 CxlmemIsolationEnable : 1; // Bits 16+ U= INT32 CxlmemIsolationLinkdownEnable : 1; // Bits 17+ UINT32 Cxlcache= IsolationEnable : 1; // Bits 18+ UINT32 CxlcacheIsolationLinkd= ownEnable : 1; // Bits 19+ UINT32 Reserved3 : 5= ; // Bits 24:20+ UINT32 IsolationErrCorSignalingEnable : 1; // Bits = 25+ UINT32 IsolationInterruptEnable : 1; // Bits 26+ UINT32 = Reserved4 : 5; // Bits 31:27+ } Bits;+ UINT32 = Data32;+} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION= _CONTROL;++typedef union {+ struct {+ UINT32 CxlmemTransactionTimeout = : 1; // Bits 0+ UINT32 Reserved1 : 3; //= Bits 3:1+ UINT32 CxlcacheTransactionTimeout : 1; // Bits 4+ U= INT32 Reserved2 : 3; // Bits 7:5+ UINT32 CxlmemI= solationStatus : 1; // Bits 8+ UINT32 CxlmemIsolationLinkdow= nStatus : 1; // Bits 9+ UINT32 Reserved3 : 2; = // Bits 11:10+ UINT32 CxlcacheIsolationStatus : 1; // Bits 1= 2+ UINT32 CxlcacheIsolationLinkdownStatus : 1; // Bits 13+ UINT32 C= xlRpBusy : 1; // Bits 14+ UINT32 Reserved4 = : 17; // Bits 31:15+ } Bits;+ UINT32 = Data32;+} CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS;++typede= f struct {+ CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY TimeoutAndIsol= ationCap;+ UINT32 Reserved;+ CXL= _3_0_CXL_TIMEOUT_AND_ISOLATION_CONTROL TimeoutAndIsolationControl;+ = CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_STATUS TimeoutAndIsolationStatus;+= } CXL_3_0_CXL_TIMEOUT_AND_ISOLATION_CAPABILITY_STRUCTURE;++#pragma pack()++= #endif--=20 2.37.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#112720): https://edk2.groups.io/g/devel/message/112720 Mute This Topic: https://groups.io/mt/102880442/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-