From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=jiewen.yao@intel.com; receiver=edk2-devel@lists.01.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9ACCE2097F579 for ; Wed, 7 Nov 2018 01:13:04 -0800 (PST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Nov 2018 01:13:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.54,475,1534834800"; d="scan'208";a="106597823" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by orsmga002.jf.intel.com with ESMTP; 07 Nov 2018 01:13:04 -0800 Received: from fmsmsx114.amr.corp.intel.com (10.18.116.8) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 7 Nov 2018 01:13:03 -0800 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by FMSMSX114.amr.corp.intel.com (10.18.116.8) with Microsoft SMTP Server (TLS) id 14.3.408.0; Wed, 7 Nov 2018 01:13:03 -0800 Received: from shsmsx102.ccr.corp.intel.com ([169.254.2.84]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.214]) with mapi id 14.03.0415.000; Wed, 7 Nov 2018 17:13:01 +0800 From: "Yao, Jiewen" To: "Ni, Ruiyu" CC: "edk2-devel@lists.01.org" , "Dong, Eric" Thread-Topic: [PATCH v2] UefiCpuPkg/SmmCpu: Block access-out only when static paging is used Thread-Index: AQHUdnf/xO/Kqp2Eo0OJoXrrdT7hsaVEBzmT Date: Wed, 7 Nov 2018 09:13:00 +0000 Message-ID: References: <20181107085907.158392-1-ruiyu.ni@intel.com> In-Reply-To: <20181107085907.158392-1-ruiyu.ni@intel.com> Accept-Language: zh-CN, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: MIME-Version: 1.0 Subject: Re: [PATCH v2] UefiCpuPkg/SmmCpu: Block access-out only when static paging is used X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 07 Nov 2018 09:13:04 -0000 Content-Language: zh-CN Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable reviewed-by: jiewen.yao@intel.com thank you! Yao, Jiewen > =1B$B:_=1B(B 2018=1B$BG/=1B(B11=1B$B7n=1B(B7=1B$BF|!$2<8a=1B(B4:58=1B$B!$= =1B(BNi, Ruiyu =1B$B=20 > From: Jiewen Yao >=20 > When static paging is disabled, page table for below 4GB is created > and page table for above 4GB is created dynamically in page fault > handler. >=20 > Today's implementation only allow SMM access-out to below types of > memory address no matter static paging is enabled or not: > 1. Reserved, run time and ACPI NVS type > 2. MMIO >=20 > But certain platform feature like RAS may need to access other types > of memory from SMM. Today's code blocks these platforms. > This patch simplifies the policy to only block when static paging > is used so that the static paging can be disabled in these platforms > to meet their SMM access-out need. >=20 > Setting PcdCpuSmmStaticPageTable to FALSE can disable the static > paging. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Jiewen Yao > Signed-off-by: Ruiyu Ni > Cc: Eric Dong > Cc: Jiewen Yao > Acked-by: Laszlo Ersek > --- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCp= uDxeSmm/X64/PageTbl.c > index 5bb7d57238..117502dafa 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > @@ -1,7 +1,7 @@ > /** @file > Page Fault (#PF) handler for X64 processors >=20 > -Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
> +Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
> Copyright (c) 2017, AMD Incorporated. All rights reserved.
>=20 > This program and the accompanying materials > @@ -890,7 +890,7 @@ SmiPFHandler ( > CpuDeadLoop (); > } >=20 > - if (IsSmmCommBufferForbiddenAddress (PFAddress)) { > + if (mCpuSmmStaticPageTable && IsSmmCommBufferForbiddenAddress (PFAdd= ress)) { > DumpCpuContext (InterruptType, SystemContext); > DEBUG ((DEBUG_ERROR, "Access SMM communication forbidden address (0= x%lx)!\n", PFAddress)); > DEBUG_CODE ( > --=20 > 2.16.1.windows.1 >=20