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From: "Marvin Häuser" <mhaeuser@posteo.de>
To: "S, Ashraf Ali" <ashraf.ali.s@intel.com>
Cc: devel@edk2.groups.io, chasel.chiu@intel.com,
	Nate DeSimone <nathaniel.l.desimone@intel.com>,
	star.zeng@intel.com
Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.
Date: Sun, 19 Mar 2023 09:36:56 +0000	[thread overview]
Message-ID: <E4601C5E-4189-4AB1-B3E1-688B80C72269@posteo.de> (raw)
In-Reply-To: <DM4PR11MB52805F21FC419FEEE9780CD8D7839@DM4PR11MB5280.namprd11.prod.outlook.com>

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Yes - it does. Most (if not all?) operations on 32-bit registers zero-extend the corresponding 64-bit register. This is an AMD64 / Intel 64 design to combat partial register stall. Please consult the SDM (or at least try it out).

What I didn’t realize is that “mov eax, eax” apparently defeats register renaming optimisations: https://stackoverflow.com/a/45660140

Best regards,
Marvin

> On 19. Mar 2023, at 10:07, S, Ashraf Ali <ashraf.ali.s@intel.com> wrote:
> 
> Hi.,
>  
> Nope, it will not clear the upper 32bit right.
>  
>  
> From: Marvin Häuser <mhaeuser@posteo.de> 
> Sent: Sunday, March 19, 2023 3:38 AM
> To: S, Ashraf Ali <ashraf.ali.s@intel.com>; devel@edk2.groups.io
> Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.
>  
> Hi Ashraf,
> 
> ”mov eax, eax” does clear the high 32 Bits of rax.
> 
> Best regards,
> Marvin

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  reply	other threads:[~2023-03-19  9:37 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-17 17:20 [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings Chiu, Chasel
2023-03-18 13:04 ` [edk2-devel] " Ashraf Ali S
2023-03-18 22:07   ` Marvin Häuser
2023-03-19  9:07     ` Ashraf Ali S
2023-03-19  9:36       ` Marvin Häuser [this message]
2023-03-19 16:57         ` Ashraf Ali S
2023-03-18 22:06 ` Marvin Häuser
2023-03-20  6:03 ` Ni, Ray
2023-03-20  7:31   ` Pedro Falcato
2023-03-21 23:05     ` Nate DeSimone
2023-03-22  0:17       ` Chiu, Chasel

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