From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mout01.posteo.de (mout01.posteo.de [185.67.36.65]) by mx.groups.io with SMTP id smtpd.web11.13845.1679218620030889476 for ; Sun, 19 Mar 2023 02:37:00 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@posteo.de header.s=2017 header.b=oW9Crb4Z; spf=pass (domain: posteo.de, ip: 185.67.36.65, mailfrom: mhaeuser@posteo.de) Received: from submission (posteo.de [185.67.36.169]) by mout01.posteo.de (Postfix) with ESMTPS id 13FF824025C for ; Sun, 19 Mar 2023 10:36:57 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=posteo.de; s=2017; t=1679218618; bh=q0kd5iUyJz2zrdWz5QIri/Dbkow+Cg+WtPxSKK76R+M=; h=Subject:From:Cc:Date:To:From; b=oW9Crb4ZIifDuhR+nMAKc66BW4qPfmmPYIk7t5/TM21ZUHceNFm2UOhqqOU3ZOel9 U0kIdoqrHQPuljcw04qQ/tBmT26R5E/VB2PQIaDbY/x75r5liaOs6vg9ehBsYaE1Fk ZeGpDG5an2qyBM2dj0rmEtsO05HEZqK2eD2aug9aKUiH/PY1HoIOUp1kXupr1diuiu +ply904wmPfG2aQYvotw+jMYOa1qdbrQ1D+qao5ScQ69vFFkO+hF+R3+5qde6V48ir ff62Z+oGGWDIDXwcF45+5xRR46uEjHYAPk3MbUFjHEUjuOynpgEfJx/EoZtBMmzTh1 sqTExRCGNa+bw== Received: from customer (localhost [127.0.0.1]) by submission (posteo.de) with ESMTPSA id 4PfXnh6nBtz9rxS; Sun, 19 Mar 2023 10:36:56 +0100 (CET) Mime-Version: 1.0 (1.0) Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings. From: =?UTF-8?B?TWFydmluIEjDpHVzZXI=?= In-Reply-To: Cc: devel@edk2.groups.io, chasel.chiu@intel.com, Nate DeSimone , star.zeng@intel.com Date: Sun, 19 Mar 2023 09:36:56 +0000 Message-Id: References: To: "S, Ashraf Ali" Content-Type: multipart/alternative; boundary=Apple-Mail-66FB6399-015D-4BD9-97D1-F886E7C5BC64 Content-Transfer-Encoding: 7bit --Apple-Mail-66FB6399-015D-4BD9-97D1-F886E7C5BC64 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Yes - it does. Most (if not all?) operations on 32-bit registers zero-extend= the corresponding 64-bit register. This is an AMD64 / Intel 64 design to co= mbat partial register stall. Please consult the SDM (or at least try it out)= . What I didn=E2=80=99t realize is that =E2=80=9Cmov eax, eax=E2=80=9D apparen= tly defeats register renaming optimisations: https://stackoverflow.com/a/456= 60140 Best regards, Marvin > On 19. Mar 2023, at 10:07, S, Ashraf Ali wrote: > =EF=BB=BF > Hi., > =20 > Nope, it will not clear the upper 32bit right. > =20 > =20 > From: Marvin H=C3=A4user =20 > Sent: Sunday, March 19, 2023 3:38 AM > To: S, Ashraf Ali ; devel@edk2.groups.io > Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warn= ings. > =20 > Hi Ashraf, >=20 > =E2=80=9Dmov eax, eax=E2=80=9D does clear the high 32 Bits of rax. >=20 > Best regards, > Marvin --Apple-Mail-66FB6399-015D-4BD9-97D1-F886E7C5BC64 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: quoted-printable
Yes - it does. Most (if not all?) operations on 32-bit registers z= ero-extend the corresponding 64-bit register. This is an AMD64 / Intel 64 de= sign to combat partial register stall. Please consult the SDM (or at least t= ry it out).

What I didn=E2=80= =99t realize is that =E2=80=9Cmov eax, eax=E2=80=9D apparently defeats regis= ter renaming optimisations: https://stackoverflow.com/a/45660140

Best regards,
Marvin

On 19. Mar 2023, at 10:07, S, Ashraf A= li <ashraf.ali.s@intel.com> wrote:

=EF=BB=BF

Hi.,

 

Nope, it will not clear the upper 32bit right.

 

 

From: Marvin H=C3=A4user <mhaeuser@posteo.d= e>
Sent: Sunday, March 19, 2023 3:38 AM
To: S, Ashraf Ali <ashraf.ali.s@intel.com>; devel@edk2.groups.i= o
Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build= warnings.

 

Hi Ashraf,

=E2=80=9Dmov eax, eax=E2=80=9D does clear the high 32 Bits of rax.

Best regards,
Marvin

= --Apple-Mail-66FB6399-015D-4BD9-97D1-F886E7C5BC64--