From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.100; helo=mga07.intel.com; envelope-from=benjamin.you@intel.com; receiver=edk2-devel@lists.01.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DC12B20954B8C for ; Thu, 15 Mar 2018 01:17:09 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Mar 2018 01:23:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,308,1517904000"; d="scan'208";a="34064289" Received: from fmsmsx103.amr.corp.intel.com ([10.18.124.201]) by FMSMGA003.fm.intel.com with ESMTP; 15 Mar 2018 01:23:32 -0700 Received: from fmsmsx111.amr.corp.intel.com (10.18.116.5) by FMSMSX103.amr.corp.intel.com (10.18.124.201) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 15 Mar 2018 01:23:32 -0700 Received: from shsmsx152.ccr.corp.intel.com (10.239.6.52) by fmsmsx111.amr.corp.intel.com (10.18.116.5) with Microsoft SMTP Server (TLS) id 14.3.319.2; Thu, 15 Mar 2018 01:23:32 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.235]) by SHSMSX152.ccr.corp.intel.com ([169.254.6.129]) with mapi id 14.03.0319.002; Thu, 15 Mar 2018 16:23:02 +0800 From: "You, Benjamin" To: Heyi Guo , "edk2-devel@lists.01.org" CC: Yi Li , "Ma, Maurice" , "Agyeman, Prince" , "Ni, Ruiyu" , Laszlo Ersek , Ard Biesheuvel Thread-Topic: [PATCH v7 1/6] CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init Thread-Index: AQHTvCOYtD17dAIhSkua96Bz50WEL6PQ9N7Q Date: Thu, 15 Mar 2018 08:23:01 +0000 Message-ID: References: <1521093843-48615-1-git-send-email-heyi.guo@linaro.org> <1521093843-48615-2-git-send-email-heyi.guo@linaro.org> In-Reply-To: <1521093843-48615-2-git-send-email-heyi.guo@linaro.org> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_NT x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiZThjZTJmOTktMGY1OS00OWM5LTliYjgtZjM2NTI1MWU3N2FjIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX05UIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE3LjIuNS4xOCIsIlRydXN0ZWRMYWJlbEhhc2giOiJRVFRtTG1GWmw5WEo3N015bTBIQlp4dGFEYWh3UjZkUkpuQk9XZUExUGMyR1QzNk1kM3YzYUtrcXdDMFwvYStZYiJ9 dlp-product: dlpe-windows dlp-version: 11.0.0.116 dlp-reaction: no-action x-originating-ip: [10.239.127.40] MIME-Version: 1.0 Subject: Re: [PATCH v7 1/6] CorebootPayloadPkg/PciHostBridgeLib: clear aperture vars for (re)init X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Mar 2018 08:17:10 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Benjamin You > -----Original Message----- > From: Heyi Guo [mailto:heyi.guo@linaro.org] > Sent: Thursday, March 15, 2018 2:04 PM > To: edk2-devel@lists.01.org > Cc: Heyi Guo ; Yi Li ; Ma, > Maurice ; Agyeman, Prince > ; You, Benjamin ; Ni, > Ruiyu ; Laszlo Ersek ; Ard Biesheu= vel > > Subject: [PATCH v7 1/6] CorebootPayloadPkg/PciHostBridgeLib: clear apertu= re > vars for (re)init >=20 > Use ZeroMem() to initialize (or re-initialize) all fields in temporary > PCI_ROOT_BRIDGE_APERTURE variables to zero. This is not mandatory but > helpful for future extension: when we add new fields to > PCI_ROOT_BRIDGE_APERTURE and the default value of these fields can > safely be zero, this code will not suffer from an additional change. >=20 > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Heyi Guo > Signed-off-by: Yi Li > Reviewed-by: Ni Ruiyu > Cc: Maurice Ma > Cc: Prince Agyeman > Cc: Benjamin You > Cc: Ruiyu Ni > Cc: Laszlo Ersek > Cc: Ard Biesheuvel > --- >=20 > Notes: > v6: > - Move ZeroMem() into the loop just as Laszlo commented on OvmfPkg > [Laszlo] > - Minor changes in commit message >=20 > CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 7 > ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) >=20 > diff --git > a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > index 6d94ff72c956..18dcbafdf0c6 100644 > --- a/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > +++ b/CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c > @@ -328,8 +328,13 @@ ScanForRootBridges ( > for (PrimaryBus =3D 0; PrimaryBus <=3D PCI_MAX_BUS; PrimaryBus =3D Sub= Bus + 1) { > SubBus =3D PrimaryBus; > Attributes =3D 0; > + > + ZeroMem (&Io, sizeof (Io)); > + ZeroMem (&Mem, sizeof (Mem)); > + ZeroMem (&MemAbove4G, sizeof (MemAbove4G)); > + ZeroMem (&PMem, sizeof (PMem)); > + ZeroMem (&PMemAbove4G, sizeof (PMemAbove4G)); > Io.Base =3D Mem.Base =3D MemAbove4G.Base =3D PMem.Base =3D > PMemAbove4G.Base =3D MAX_UINT64; > - Io.Limit =3D Mem.Limit =3D MemAbove4G.Limit =3D PMem.Limit =3D > PMemAbove4G.Limit =3D 0; > // > // Scan all the PCI devices on the primary bus of the PCI root bridg= e > // > -- > 2.7.4