From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ma1-aaemail-dr-lapp02.apple.com (ma1-aaemail-dr-lapp02.apple.com [17.171.2.68]) by mx.groups.io with SMTP id smtpd.web10.586.1594572847883960993 for ; Sun, 12 Jul 2020 09:54:08 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@apple.com header.s=20180706 header.b=F5FuMGB+; spf=pass (domain: apple.com, ip: 17.171.2.68, mailfrom: afish@apple.com) Received: from pps.filterd (ma1-aaemail-dr-lapp02.apple.com [127.0.0.1]) by ma1-aaemail-dr-lapp02.apple.com (8.16.0.42/8.16.0.42) with SMTP id 06CGrAkk042491; Sun, 12 Jul 2020 09:54:06 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=apple.com; h=from : message-id : content-type : mime-version : subject : date : in-reply-to : cc : to : references; s=20180706; bh=ncYlt16lEVl3YkGOP+uvmTycdD22TQvq1yZ5HYZDbWk=; b=F5FuMGB+Cou5Wm7LVWMuFE4I+n6MX0zGUJjaAYXlKHu5D2LlseCHgBjxwcttTz3CuqR9 Tkm5Ss/zULMakOXFXyE6IA+6hz0WaHDw7lmRaJNYKMb2TvAolyfQy0HeJQ+dggG+2zQ4 6p2+zYq1JZ8KK43s2h8JMi5nHiWmgCD6YOQBIVaHZpuewLidYqV1ZkKPEI4TEARUQbKh xPL65jSVAK/he8mHc16W6vWmgKD+W3dPiIKp+GLVa9qJvKqys0RlwOdgefQeqE7JOBN2 q9OS4o7DwUvONBA5Ehsfz9hRQV186RHLUL1oTb2PGsLoxPlriyY7DyCbAJ3CXOI81QU2 Ug== Received: from rn-mailsvcp-mta-lapp04.rno.apple.com (rn-mailsvcp-mta-lapp04.rno.apple.com [10.225.203.152]) by ma1-aaemail-dr-lapp02.apple.com with ESMTP id 327a3rmycy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NO); Sun, 12 Jul 2020 09:54:06 -0700 Received: from rn-mailsvcp-mmp-lapp03.rno.apple.com (rn-mailsvcp-mmp-lapp03.rno.apple.com [17.179.253.16]) by rn-mailsvcp-mta-lapp04.rno.apple.com (Oracle Communications Messaging Server 8.1.0.5.20200312 64bit (built Mar 12 2020)) with ESMTPS id <0QDD00FI88A5LB60@rn-mailsvcp-mta-lapp04.rno.apple.com>; Sun, 12 Jul 2020 09:54:05 -0700 (PDT) Received: from process_milters-daemon.rn-mailsvcp-mmp-lapp03.rno.apple.com by rn-mailsvcp-mmp-lapp03.rno.apple.com (Oracle Communications Messaging Server 8.1.0.5.20200312 64bit (built Mar 12 2020)) id <0QDD00100880IY00@rn-mailsvcp-mmp-lapp03.rno.apple.com>; Sun, 12 Jul 2020 09:54:05 -0700 (PDT) X-Va-A: X-Va-T-CD: 678bf7de5df0d9ff994f556fd1b44182 X-Va-E-CD: 01093fc030ab03d36fd5e7ee208a4cd6 X-Va-R-CD: a3f879d2c1accc6e75c86140cc99a4ed X-Va-CD: 0 X-Va-ID: ffc5ba24-fb7a-455c-84c9-ff3948a734af X-V-A: X-V-T-CD: 678bf7de5df0d9ff994f556fd1b44182 X-V-E-CD: 01093fc030ab03d36fd5e7ee208a4cd6 X-V-R-CD: a3f879d2c1accc6e75c86140cc99a4ed X-V-CD: 0 X-V-ID: c9513ee5-a1c1-4315-a1b8-235c9dc5f7c9 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-12_08:2020-07-10,2020-07-12 signatures=0 Received: from [17.235.56.38] (unknown [17.235.56.38]) by rn-mailsvcp-mmp-lapp03.rno.apple.com (Oracle Communications Messaging Server 8.1.0.5.20200312 64bit (built Mar 12 2020)) with ESMTPSA id <0QDD00PB68A39L00@rn-mailsvcp-mmp-lapp03.rno.apple.com>; Sun, 12 Jul 2020 09:54:05 -0700 (PDT) From: "Andrew Fish" Message-id: MIME-version: 1.0 (Mac OS X Mail 13.4 \(3608.80.23.2.2\)) Subject: Re: [edk2-devel] [edk2-discuss] Need memory barriers in IoLib for AARCH64 Date: Sun, 12 Jul 2020 09:54:03 -0700 In-reply-to: Cc: Mike Kinney , "liming.gao@intel.com" To: devel@edk2.groups.io, wasim.khan@nxp.com References: X-Mailer: Apple Mail (2.3608.80.23.2.2) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235,18.0.687 definitions=2020-07-12_08:2020-07-10,2020-07-12 signatures=0 Content-type: multipart/alternative; boundary="Apple-Mail=_D5FA0296-71F8-407C-A80B-669324162540" --Apple-Mail=_D5FA0296-71F8-407C-A80B-669324162540 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 > On Jul 11, 2020, at 10:17 PM, Wasim Khan wrote: >=20 > Hello=20 >=20 > Any comments ? >=20 I don=E2=80=99t see IoLibArm.c in master? I see IoLibNoIo.c.=20 The MMIO function look like ARM assembler with the correct barrier instruc= tions. The IO operations in this lib are the x86 in/out instructions, so th= ey just ASSERT on ARM.=20 On the X86 MemoryFence() is just a serializing intrinsic for the compiler = to prevent optimizations from breaking the code, kind of like how you need = to make MMIO as volatile in C.=20 Thanks, Andrew Fish >> -----Original Message----- >> From: Wasim Khan >> Sent: Friday, July 10, 2020 6:20 PM >> To: michael.d.kinney@intel.com; liming.gao@intel.com; devel@edk2.groups= .io >> Subject: [edk2-discuss] Need memory barriers in IoLib for AARCH64 >>=20 >> Hello, >>=20 >> MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf: >> IoLib library uses IoLibArm.c for AARCH64/ARM architecture and IoLib.c = for >> other architectures. >>=20 >> While IoLib.c already has memory barriers in MmioWrite functions, there >> barriers are missing in IoLibArm.c Is there any reason for **not** addi= ng these >> memory barriers in IoLibArm.c to guarantee that all MMIO operations are >> serialized ? >>=20 >> I am facing some issues and I need to add memory barriers in IoLibArm.c= for >> AARCH64 also . >>=20 >>=20 >> Regards, >> Wasim >=20 >=20 >=20 --Apple-Mail=_D5FA0296-71F8-407C-A80B-669324162540 Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=utf-8

On Jul 11, 2= 020, at 10:17 PM, Wasim Khan <wasim.khan@nxp.com> wrote:

Hello 

Any comments ?

=

I don=E2=80=99t see IoLibArm.c in maste= r? I see IoLibNoIo.c. 

The MM= IO function look like ARM assembler with the correct barrier instructions. = The IO operations in this lib are the x86 in/out instructions, so they just= ASSERT on ARM. 

On the X86 M= emoryFence() is just a serializing intrinsic for the compiler to prevent op= timizations from breaking the code, kind of like how you need to make MMIO = as volatile in C. 

Thanks,

Andrew Fish

-----Original Me= ssage-----
From: Wasim Khan
Sent: Friday, July = 10, 2020 6:20 PM
To: michael.d.kinney@intel.com; liming.gao@intel.com; devel@edk2.groups.io
Subject: = [edk2-discuss] Need memory barriers in IoLib for AARCH64

Hello,

MdePkg/Library/BaseIoLibIntr= insic/BaseIoLibIntrinsic.inf:
IoLib library uses IoLibArm.c f= or AARCH64/ARM architecture and IoLib.c for
other architectur= es.

While IoLib.c already has memory barriers = in MmioWrite functions, there
barriers are missing in IoLibAr= m.c Is there any reason for **not** adding these
memory barri= ers in IoLibArm.c to guarantee that all MMIO operations are
s= erialized ?

I am facing some issues and I need= to add memory barriers in IoLibArm.c for
AARCH64 also .


Regards,
Wasim



--Apple-Mail=_D5FA0296-71F8-407C-A80B-669324162540--