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From: "Kinney, Michael D" <michael.d.kinney@intel.com>
To: "Fan, Jeff" <jeff.fan@intel.com>,
	"edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
	"Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Tian, Feng" <feng.tian@intel.com>,
	"Mudusuru, Giri P" <giri.p.mudusuru@intel.com>,
	Laszlo Ersek <lersek@redhat.com>
Subject: Re: [Patch v5 01/48] UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions
Date: Tue, 2 Aug 2016 17:17:36 +0000	[thread overview]
Message-ID: <E92EE9817A31E24EB0585FDF735412F5647F2B06@ORSMSX113.amr.corp.intel.com> (raw)
In-Reply-To: <1470128388-17960-2-git-send-email-jeff.fan@intel.com>

Jeff,

The copyright dates need to be updated to 2016 in the following 2 files:

  SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h
  SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c

With those updates,

Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>

Mike

> -----Original Message-----
> From: Fan, Jeff
> Sent: Tuesday, August 2, 2016 1:59 AM
> To: edk2-devel@lists.01.org
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Tian, Feng <feng.tian@intel.com>;
> Mudusuru, Giri P <giri.p.mudusuru@intel.com>; Laszlo Ersek <lersek@redhat.com>
> Subject: [Patch v5 01/48] UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted
> definitions
> 
> #define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_APIC_BASE
> defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it
> and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h.
> 
> Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE defined
> in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it and
> update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from
> ArchitecturalMsr.h.
> 
> v5:
>   1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMsr.h.
> 
> Cc: Michael Kinney <michael.d.kinney@intel.com>
> Cc: Feng Tian <feng.tian@intel.com>
> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jeff Fan <jeff.fan@intel.com>
> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
> ---
>  .../DebugAgent/DebugAgentCommon/DebugAgent.h       |  1 +
>  .../Library/DebugAgent/DebugAgentCommon/DebugMp.c  |  5 ++-
>  UefiCpuPkg/CpuMpPei/CpuMpPei.h                     |  1 +
>  UefiCpuPkg/CpuMpPei/PeiMpServices.c                | 20 ++++-----
>  UefiCpuPkg/Include/Register/LocalApic.h            | 20 +--------
>  UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c     | 29 ++++++------
>  .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c        | 51 +++++++++++-----------
>  7 files changed, 58 insertions(+), 69 deletions(-)
> 
> diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h
> b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h
> index 64e4c3e..18b93a3 100644
> --- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h
> +++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h
> @@ -34,6 +34,7 @@
>  #include <Library/PrintLib.h>
>  #include <Library/PeCoffGetEntryPointLib.h>
>  #include <Library/PeCoffExtraActionLib.h>
> +#include <Register/ArchitecturalMsr.h>
> 
>  #include <TransferProtocol.h>
>  #include <ImageDebugSupport.h>
> diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
> b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
> index bdb6742..db9eb6a 100644
> --- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
> +++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c
> @@ -141,6 +141,8 @@ IsBsp (
>    IN UINT32  ProcessorIndex
>    )
>  {
> +  MSR_IA32_APIC_BASE_REGISTER  MsrApicBase;
> +
>    //
>    // If there are less than 2 CPUs detected, then the currently executing CPU
>    // must be the BSP.  This avoids an access to an MSR that may not be supported
> @@ -150,7 +152,8 @@ IsBsp (
>      return TRUE;
>    }
> 
> -  if (AsmMsrBitFieldRead64 (MSR_IA32_APIC_BASE_ADDRESS, 8, 8) == 1) {
> +  MsrApicBase.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
> +  if (MsrApicBase.Bits.BSP == 1) {
>      if (mDebugMpContext.BspIndex != ProcessorIndex) {
>        AcquireMpSpinLock (&mDebugMpContext.MpContextSpinLock);
>        mDebugMpContext.BspIndex = ProcessorIndex;
> diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
> index b2e578b..0d1a14a 100644
> --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h
> +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h
> @@ -25,6 +25,7 @@
> 
>  #include <Register/Cpuid.h>
>  #include <Register/LocalApic.h>
> +#include <Register/Msr.h>
> 
>  #include <Library/BaseLib.h>
>  #include <Library/BaseMemoryLib.h>
> diff --git a/UefiCpuPkg/CpuMpPei/PeiMpServices.c b/UefiCpuPkg/CpuMpPei/PeiMpServices.c
> index e784377..e06fdf1 100644
> --- a/UefiCpuPkg/CpuMpPei/PeiMpServices.c
> +++ b/UefiCpuPkg/CpuMpPei/PeiMpServices.c
> @@ -1,7 +1,7 @@
>  /** @file
>    Implementation of Multiple Processor PPI services.
> 
> -  Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
> +  Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
>    This program and the accompanying materials
>    are licensed and made available under the terms and conditions of the BSD License
>    which accompanies this distribution.  The full text of the license may be found at
> @@ -729,9 +729,9 @@ PeiSwitchBSP (
>    IN  BOOLEAN                  EnableOldBSP
>    )
>  {
> -  PEI_CPU_MP_DATA         *PeiCpuMpData;
> -  UINTN                   CallerNumber;
> -  MSR_IA32_APIC_BASE      ApicBaseMsr;
> +  PEI_CPU_MP_DATA              *PeiCpuMpData;
> +  UINTN                        CallerNumber;
> +  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;
> 
>    PeiCpuMpData = GetMpHobData ();
>    if (PeiCpuMpData == NULL) {
> @@ -774,9 +774,9 @@ PeiSwitchBSP (
>    //
>    // Clear the BSP bit of MSR_IA32_APIC_BASE
>    //
> -  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> -  ApicBaseMsr.Bits.Bsp = 0;
> -  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
> +  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
> +  ApicBaseMsr.Bits.BSP = 0;
> +  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
> 
>    PeiCpuMpData->BSPInfo.State = CPU_SWITCH_STATE_IDLE;
>    PeiCpuMpData->APInfo.State  = CPU_SWITCH_STATE_IDLE;
> @@ -805,9 +805,9 @@ PeiSwitchBSP (
>    //
>    // Set the BSP bit of MSR_IA32_APIC_BASE on new BSP
>    //
> -  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> -  ApicBaseMsr.Bits.Bsp = 1;
> -  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
> +  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
> +  ApicBaseMsr.Bits.BSP = 1;
> +  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
>    //
>    // Set old BSP enable state
>    //
> diff --git a/UefiCpuPkg/Include/Register/LocalApic.h
> b/UefiCpuPkg/Include/Register/LocalApic.h
> index 346cce6..cfb6d76 100644
> --- a/UefiCpuPkg/Include/Register/LocalApic.h
> +++ b/UefiCpuPkg/Include/Register/LocalApic.h
> @@ -1,7 +1,7 @@
>  /** @file
>    IA32 Local APIC Definitions.
> 
> -  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
> +  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
>    This program and the accompanying materials
>    are licensed and made available under the terms and conditions of the BSD License
>    which accompanies this distribution.  The full text of the license may be found at
> @@ -16,11 +16,6 @@
>  #define __LOCAL_APIC_H__
> 
>  //
> -// Definitions for IA32 architectural MSRs
> -//
> -#define MSR_IA32_APIC_BASE_ADDRESS              0x1B
> -
> -//
>  // Definition for Local APIC registers and related values
>  //
>  #define XAPIC_ID_OFFSET                         0x20
> @@ -53,19 +48,6 @@
>  #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
>  #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
> 
> -typedef union {
> -  struct {
> -    UINT32  Reserved0:8;     ///< Reserved.
> -    UINT32  Bsp:1;           ///< Processor is BSP.
> -    UINT32  Reserved1:1;     ///< Reserved.
> -    UINT32  Extd:1;          ///< Enable x2APIC mode.
> -    UINT32  En:1;            ///< xAPIC global enable/disable.
> -    UINT32  ApicBaseLow:20;  ///< APIC Base physical address. The actual field width
> depends on physical address width.
> -    UINT32  ApicBaseHigh:32;
> -  } Bits;
> -  UINT64    Uint64;
> -} MSR_IA32_APIC_BASE;
> -
>  //
>  // Local APIC Version Register.
>  //
> diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> index 1fca66e..8d0fb02 100644
> --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
> @@ -3,7 +3,7 @@
> 
>    This local APIC library instance supports xAPIC mode only.
> 
> -  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
> +  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
>    This program and the accompanying materials
>    are licensed and made available under the terms and conditions of the BSD License
>    which accompanies this distribution.  The full text of the license may be found at
> @@ -15,6 +15,7 @@
>  **/
> 
>  #include <Register/Cpuid.h>
> +#include <Register/Msr.h>
>  #include <Register/LocalApic.h>
> 
>  #include <Library/BaseLib.h>
> @@ -67,7 +68,7 @@ GetLocalApicBaseAddress (
>    VOID
>    )
>  {
> -  MSR_IA32_APIC_BASE  ApicBaseMsr;
> +  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;
> 
>    if (!LocalApicBaseAddressMsrSupported ()) {
>      //
> @@ -77,10 +78,10 @@ GetLocalApicBaseAddress (
>      return PcdGet32 (PcdCpuLocalApicBaseAddress);
>    }
> 
> -  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> +  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
> 
> -  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
> -           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
> +  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
> +           (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
>  }
> 
>  /**
> @@ -97,7 +98,7 @@ SetLocalApicBaseAddress (
>    IN UINTN                BaseAddress
>    )
>  {
> -  MSR_IA32_APIC_BASE  ApicBaseMsr;
> +  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;
> 
>    ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
> 
> @@ -108,12 +109,12 @@ SetLocalApicBaseAddress (
>      return;
>    }
> 
> -  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> +  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
> 
> -  ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);
> -  ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
> +  ApicBaseMsr.Bits.ApicBase   = (UINT32) (BaseAddress >> 12);
> +  ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
> 
> -  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
> +  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
>  }
> 
>  /**
> @@ -246,18 +247,18 @@ GetApicMode (
>  {
>    DEBUG_CODE (
>      {
> -      MSR_IA32_APIC_BASE  ApicBaseMsr;
> +      MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;
> 
>        //
>        // Check to see if the CPU supports the APIC Base Address MSR
>        //
>        if (LocalApicBaseAddressMsrSupported ()) {
> -        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> +        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
>          //
>          // Local APIC should have been enabled
>          //
> -        ASSERT (ApicBaseMsr.Bits.En != 0);
> -        ASSERT (ApicBaseMsr.Bits.Extd == 0);
> +        ASSERT (ApicBaseMsr.Bits.EN != 0);
> +        ASSERT (ApicBaseMsr.Bits.EXTD == 0);
>        }
>      }
>    );
> diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> index 38f5370..4c42696 100644
> --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
> @@ -4,7 +4,7 @@
>    This local APIC library instance supports x2APIC capable processors
>    which have xAPIC and x2APIC modes.
> 
> -  Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>
> +  Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
>    This program and the accompanying materials
>    are licensed and made available under the terms and conditions of the BSD License
>    which accompanies this distribution.  The full text of the license may be found at
> @@ -16,6 +16,7 @@
>  **/
> 
>  #include <Register/Cpuid.h>
> +#include <Register/Msr.h>
>  #include <Register/LocalApic.h>
> 
>  #include <Library/BaseLib.h>
> @@ -68,7 +69,7 @@ GetLocalApicBaseAddress (
>    VOID
>    )
>  {
> -  MSR_IA32_APIC_BASE  ApicBaseMsr;
> +  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;
> 
>    if (!LocalApicBaseAddressMsrSupported ()) {
>      //
> @@ -78,10 +79,10 @@ GetLocalApicBaseAddress (
>      return PcdGet32 (PcdCpuLocalApicBaseAddress);
>    }
> 
> -  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> +  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
> 
> -  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +
> -           (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);
> +  return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) +
> +           (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12);
>  }
> 
>  /**
> @@ -98,7 +99,7 @@ SetLocalApicBaseAddress (
>    IN UINTN                BaseAddress
>    )
>  {
> -  MSR_IA32_APIC_BASE  ApicBaseMsr;
> +  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;
> 
>    ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);
> 
> @@ -109,12 +110,12 @@ SetLocalApicBaseAddress (
>      return;
>    }
> 
> -  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> +  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
> 
> -  ApicBaseMsr.Bits.ApicBaseLow  = (UINT32) (BaseAddress >> 12);
> -  ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
> +  ApicBaseMsr.Bits.ApicBase   = (UINT32) (BaseAddress >> 12);
> +  ApicBaseMsr.Bits.ApicBaseHi = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));
> 
> -  AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
> +  AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
>  }
> 
>  /**
> @@ -301,7 +302,7 @@ GetApicMode (
>    VOID
>    )
>  {
> -  MSR_IA32_APIC_BASE  ApicBaseMsr;
> +  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;
> 
>    if (!LocalApicBaseAddressMsrSupported ()) {
>      //
> @@ -310,12 +311,12 @@ GetApicMode (
>      return LOCAL_APIC_MODE_XAPIC;
>    }
> 
> -  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> +  ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
>    //
>    // Local APIC should have been enabled
>    //
> -  ASSERT (ApicBaseMsr.Bits.En != 0);
> -  if (ApicBaseMsr.Bits.Extd != 0) {
> +  ASSERT (ApicBaseMsr.Bits.EN != 0);
> +  if (ApicBaseMsr.Bits.EXTD != 0) {
>      return LOCAL_APIC_MODE_X2APIC;
>    } else {
>      return LOCAL_APIC_MODE_XAPIC;
> @@ -339,8 +340,8 @@ SetApicMode (
>    IN UINTN  ApicMode
>    )
>  {
> -  UINTN               CurrentMode;
> -  MSR_IA32_APIC_BASE  ApicBaseMsr;
> +  UINTN                        CurrentMode;
> +  MSR_IA32_APIC_BASE_REGISTER  ApicBaseMsr;
> 
>    if (!LocalApicBaseAddressMsrSupported ()) {
>      //
> @@ -355,9 +356,9 @@ SetApicMode (
>        case LOCAL_APIC_MODE_XAPIC:
>          break;
>        case LOCAL_APIC_MODE_X2APIC:
> -        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> -        ApicBaseMsr.Bits.Extd = 1;
> -        AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
> +        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
> +        ApicBaseMsr.Bits.EXTD = 1;
> +        AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
>          break;
>        default:
>          ASSERT (FALSE);
> @@ -369,12 +370,12 @@ SetApicMode (
>          //  Transition from x2APIC mode to xAPIC mode is a two-step process:
>          //    x2APIC -> Local APIC disabled -> xAPIC
>          //
> -        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);
> -        ApicBaseMsr.Bits.Extd = 0;
> -        ApicBaseMsr.Bits.En = 0;
> -        AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
> -        ApicBaseMsr.Bits.En = 1;
> -        AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);
> +        ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE);
> +        ApicBaseMsr.Bits.EXTD = 0;
> +        ApicBaseMsr.Bits.EN = 0;
> +        AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
> +        ApicBaseMsr.Bits.EN = 1;
> +        AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64);
>          break;
>        case LOCAL_APIC_MODE_X2APIC:
>          break;
> --
> 2.7.4.windows.1



  reply	other threads:[~2016-08-02 17:17 UTC|newest]

Thread overview: 71+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-02  8:59 [Patch v5 00/48] MP Initialize Library Jeff Fan
2016-08-02  8:59 ` [Patch v5 01/48] UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions Jeff Fan
2016-08-02 17:17   ` Kinney, Michael D [this message]
2016-08-02  8:59 ` [Patch v5 02/48] UefiCpuPkg/MpInitLib: Add microcode definitions defined in IA32 SDM Jeff Fan
2016-08-02 15:20   ` Mudusuru, Giri P
2016-08-02  8:59 ` [Patch v5 03/48] UefiCpuPkg/CpuS3DataDxe: Move StartupVector allocation to EndOfDxe() Jeff Fan
2016-08-02  8:59 ` [Patch v5 04/48] UefiCpuPkg/MpInitLib: Add MP Initialize library class definition Jeff Fan
2016-08-02  8:59 ` [Patch v5 05/48] UefiCpuPkg/MpInitLib: Add two instances PeiMpInitLib and DxeMpInitLib Jeff Fan
2016-08-02  8:59 ` [Patch v5 06/48] UefiCpuPkg/MpInitLib: Add AP assembly code and MP_CPU_EXCHANGE_INFO Jeff Fan
2016-08-02  8:59 ` [Patch v5 07/48] UefiCpuPkg/MpInitLib: Fix typo and clean up the code Jeff Fan
2016-08-02  8:59 ` [Patch v5 08/48] UefiCpuPkg/MpInitLib: Add EnableExecuteDisable in MP_CPU_EXCHANGE_INFO Jeff Fan
2016-08-02  8:59 ` [Patch v5 09/48] UefiCpuPkg/MpInitLib: Add AsmRelocateApLoop() assembly code Jeff Fan
2016-08-02  8:59 ` [Patch v5 10/48] UefiCpuPkg/MpInitLib: Add MP_ASSEMBLY_ADDRESS_MAP Jeff Fan
2016-08-02  8:59 ` [Patch v5 11/48] UefiCpuPkg/MpInitLib: Get ApLoopMode and MointorFilter size Jeff Fan
2016-08-02  8:59 ` [Patch v5 12/48] UefiCpuPkg/MpInitLib: Allocate and initialize memory of MP Data buffer Jeff Fan
2016-08-02  8:59 ` [Patch v5 13/48] UefiCpuPkg/MpInitLib: Initialize CPU_AP_DATA for CPU APs Jeff Fan
2016-08-02  8:59 ` [Patch v5 14/48] UefiCpuPkg/MpInitLib: Add CPU_VOLATILE_REGISTERS & worker functions Jeff Fan
2016-08-02  8:59 ` [Patch v5 15/48] UefiCpuPkg/MpInitLib: Add MicrocodeDetect() and load microcode on BSP Jeff Fan
2016-08-02  8:59 ` [Patch v5 16/48] UefiCpuPkg/MpInitLib: Save CPU MP Data pointer Jeff Fan
2016-08-02  8:59 ` [Patch v5 17/48] UefiCpuPkg/MpInitLib: Register one End of PEI callback function Jeff Fan
2016-08-02  8:59 ` [Patch v5 18/48] UefiCpuPkg/MpInitLib: Register one period event to check APs status Jeff Fan
2016-08-02  8:59 ` [Patch v5 19/48] UefiCpuPkg/MpInitLib: Allocate AP reset vector buffer under 1MB Jeff Fan
2016-08-02  8:59 ` [Patch v5 20/48] UefiCpuPkg/MpInitLib: Add ApWakeupFunction() executed by assembly code Jeff Fan
2016-08-02  8:59 ` [Patch v5 21/48] UefiCpuPkg/MpInitLib: Fill MP_CPU_EXCHANGE_INFO fields Jeff Fan
2016-08-02  8:59 ` [Patch v5 22/48] UefiCpuPkg/MpInitLib: Add WakeUpAP() Jeff Fan
2016-08-02  8:59 ` [Patch v5 23/48] UefiCpuPkg/MpInitLib: Send INIT-SIPI-SIPI to get processor count Jeff Fan
2016-08-02  8:59 ` [Patch v5 24/48] UefiCpuPkg/MpInitLib: Enable x2APIC mode on BSP/APs Jeff Fan
2016-08-02  8:59 ` [Patch v5 25/48] UefiCpuPkg/MpInitLib: Sort processor by ascending order of APIC ID Jeff Fan
2016-08-02  8:59 ` [Patch v5 26/48] UefiCpuPkg/MpInitLib: Skip collect processor count if GUIDed HOB exist Jeff Fan
2016-08-02  8:59 ` [Patch v5 27/48] UefiCpuPkg/MpInitLib: Implementation of MpInitLibGetNumberOfProcessors() Jeff Fan
2016-08-02  8:59 ` [Patch v5 28/48] UefiCpuPkg/MpInitLib: Implementation of MpInitLibGetProcessorInfo() Jeff Fan
2016-08-02  8:59 ` [Patch v5 29/48] UefiCpuPkg/MpInitLib: Implementation of MpInitLibWhoAmI() Jeff Fan
2016-08-02  8:59 ` [Patch v5 30/48] UefiCpuPkg/MpInitLib: Implementation of MpInitLibSwitchBSP() Jeff Fan
2016-08-02  8:59 ` [Patch v5 31/48] UefiCpuPkg/MpInitLib: Implementation of MpInitLibEnableDisableAP() Jeff Fan
2016-08-02  8:59 ` [Patch v5 32/48] UefiCpuPkg/MpInitLib: Check APs Status and update APs status Jeff Fan
2016-08-02  8:59 ` [Patch v5 33/48] UefiCpuPkg/MpInitLib: Implementation of MpInitLibStartupThisAP() Jeff Fan
2016-08-02  8:59 ` [Patch v5 34/48] UefiCpuPkg/MpInitLib: Implementation of MpInitLibStartupAllAPs() Jeff Fan
2016-08-02  8:59 ` [Patch v5 35/48] UefiCpuPkg/MpInitLib: Place APs in safe loop before hand-off to OS Jeff Fan
2016-08-02  8:59 ` [Patch v5 36/48] OvmfPkg: Add MpInitLib reference in DSC files Jeff Fan
2016-08-02 11:39   ` Laszlo Ersek
2016-08-02  8:59 ` [Patch v5 37/48] QuarkPlatformPkg: " Jeff Fan
2016-08-02  8:59 ` [Patch v5 38/48] UefiCpuPkg/CpuMpPei: Consume MpInitLib to produce CPU MP PPI services Jeff Fan
2016-08-02  8:59 ` [Patch v5 39/48] UefiCpuPkg/CpuMpPei: Remove unused files and codes Jeff Fan
2016-08-02  8:59 ` [Patch v5 40/48] UefiCpuPkg/CpuMpPei: Delete PeiMpServices.c and PeiMpServices.h Jeff Fan
2016-08-02  8:59 ` [Patch v5 41/48] UefiCpuPkg/CpuDxe: Consume MpInitLib to produce CPU MP Protocol services Jeff Fan
2016-08-02  8:59 ` [Patch v5 42/48] UefiCpuPkg/CpuDxe: Move SetMtrrsFromBuffer() location Jeff Fan
2016-08-02  8:59 ` [Patch v5 43/48] UefiCpuPkg/CpuDxe: Remove unused codes and files Jeff Fan
2016-08-02  8:59 ` [Patch v5 44/48] UefiCpuPkg/CpuDxe: Remove PcdCpuMaxLogicalProcessorNumber consuming Jeff Fan
2016-08-02  8:59 ` [Patch v5 45/48] MdePkg/MpService.h: Fixed typo in function header to match PI spec Jeff Fan
2016-08-02  8:59 ` [Patch v5 46/48] MdePkg/MpService.h: Trim whitespace at end of line Jeff Fan
2016-08-02  8:59 ` [Patch v5 47/48] UefiCpuPkg/CpuDxe: Fixed typo in function header to match PI spec Jeff Fan
2016-08-02  8:59 ` [Patch v5 48/48] UefiCpuPkg/PiSmmCpuDxeSmm: Add gEfiVariableArchProtocolGuid dependency Jeff Fan
2016-08-19  1:19   ` Laszlo Ersek
2016-08-19  2:00     ` Fan, Jeff
2016-08-19  2:26       ` Laszlo Ersek
2016-08-19  2:45         ` Zeng, Star
2016-08-19  2:57           ` Zeng, Star
2016-08-19 13:19             ` Laszlo Ersek
2016-08-23 15:33             ` Laszlo Ersek
2016-08-24  2:39               ` Zeng, Star
2016-08-24  3:27                 ` Laszlo Ersek
     [not found]                   ` <ea6bfac6-1f9c-a0f6-c4ce-0b147136f34e@intel.com>
2016-08-24  8:16                     ` Zeng, Star
2016-08-24 11:53                     ` Laszlo Ersek
2016-08-24 13:42                       ` Zeng, Star
2016-08-25  8:00                         ` Fan, Jeff
2016-08-30 13:45                           ` Laszlo Ersek
2016-09-01  1:11                             ` Fan, Jeff
2016-09-01 17:46                               ` Laszlo Ersek
2016-09-02  0:49                                 ` Fan, Jeff
2016-08-19 14:28         ` Laszlo Ersek
2016-08-02 18:55 ` [Patch v5 00/48] MP Initialize Library Kinney, Michael D

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