From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by ml01.01.org (Postfix) with ESMTP id DD5FA1A1DEB for ; Tue, 2 Aug 2016 10:17:45 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 02 Aug 2016 10:17:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,461,1464678000"; d="scan'208";a="858373027" Received: from orsmsx104.amr.corp.intel.com ([10.22.225.131]) by orsmga003.jf.intel.com with ESMTP; 02 Aug 2016 10:17:37 -0700 Received: from orsmsx153.amr.corp.intel.com (10.22.226.247) by ORSMSX104.amr.corp.intel.com (10.22.225.131) with Microsoft SMTP Server (TLS) id 14.3.248.2; Tue, 2 Aug 2016 10:17:37 -0700 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.118]) by ORSMSX153.amr.corp.intel.com ([169.254.12.206]) with mapi id 14.03.0248.002; Tue, 2 Aug 2016 10:17:37 -0700 From: "Kinney, Michael D" To: "Fan, Jeff" , "edk2-devel@lists.01.org" , "Kinney, Michael D" CC: "Tian, Feng" , "Mudusuru, Giri P" , Laszlo Ersek Thread-Topic: [Patch v5 01/48] UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions Thread-Index: AQHR7JxCx1AxSMOZSECta2M93v4WWaA16byQ Date: Tue, 2 Aug 2016 17:17:36 +0000 Message-ID: References: <1470128388-17960-1-git-send-email-jeff.fan@intel.com> <1470128388-17960-2-git-send-email-jeff.fan@intel.com> In-Reply-To: <1470128388-17960-2-git-send-email-jeff.fan@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMmI5YTIyOGEtOTYyYS00ZDFkLTkxYWYtYjYxZmE5M2Y1MzBjIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6ImdNUFdRK1NISWFQRmp5Mzh1RVAzVHRYSFBYYTlIMmpjYmttdzRaYlZ6ZHM9In0= x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Subject: Re: [Patch v5 01/48] UefiCpuPkg/LocalApic.h: Remove duplicated/conflicted definitions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 02 Aug 2016 17:17:46 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Jeff, The copyright dates need to be updated to 2016 in the following 2 files: SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c With those updates, Reviewed-by: Michael Kinney Mike > -----Original Message----- > From: Fan, Jeff > Sent: Tuesday, August 2, 2016 1:59 AM > To: edk2-devel@lists.01.org > Cc: Kinney, Michael D ; Tian, Feng ; > Mudusuru, Giri P ; Laszlo Ersek > Subject: [Patch v5 01/48] UefiCpuPkg/LocalApic.h: Remove duplicated/confl= icted > definitions >=20 > #define MSR_IA32_APIC_BASE_ADDRESS is duplicated with #define MSR_IA32_AP= IC_BASE > defined in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could re= move it > and update the modules to use MSR_IA32_APIC_BASE from ArchitecturalMsr.h. >=20 > Structure MSR_IA32_APIC_BASE conflicts with #define MSR_IA32_APIC_BASE de= fined > in UefiCpuPkg/Include/Register/ArchitecturalMsr.h, so we could remove it = and > update the modules to use structure MSR_IA32_APIC_BASE_REGISTER from > ArchitecturalMsr.h. >=20 > v5: > 1. Update SourceLevelDebugPkg to use APIC Base MSR from ArchitecturalMs= r.h. >=20 > Cc: Michael Kinney > Cc: Feng Tian > Cc: Giri P Mudusuru > Cc: Laszlo Ersek > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jeff Fan > Reviewed-by: Giri P Mudusuru > Reviewed-by: Laszlo Ersek > --- > .../DebugAgent/DebugAgentCommon/DebugAgent.h | 1 + > .../Library/DebugAgent/DebugAgentCommon/DebugMp.c | 5 ++- > UefiCpuPkg/CpuMpPei/CpuMpPei.h | 1 + > UefiCpuPkg/CpuMpPei/PeiMpServices.c | 20 ++++----- > UefiCpuPkg/Include/Register/LocalApic.h | 20 +-------- > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 29 ++++++------ > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 51 +++++++++++-----= ------ > 7 files changed, 58 insertions(+), 69 deletions(-) >=20 > diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Debu= gAgent.h > b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.h > index 64e4c3e..18b93a3 100644 > --- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.= h > +++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugAgent.= h > @@ -34,6 +34,7 @@ > #include > #include > #include > +#include >=20 > #include > #include > diff --git a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/Debu= gMp.c > b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c > index bdb6742..db9eb6a 100644 > --- a/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c > +++ b/SourceLevelDebugPkg/Library/DebugAgent/DebugAgentCommon/DebugMp.c > @@ -141,6 +141,8 @@ IsBsp ( > IN UINT32 ProcessorIndex > ) > { > + MSR_IA32_APIC_BASE_REGISTER MsrApicBase; > + > // > // If there are less than 2 CPUs detected, then the currently executin= g CPU > // must be the BSP. This avoids an access to an MSR that may not be s= upported > @@ -150,7 +152,8 @@ IsBsp ( > return TRUE; > } >=20 > - if (AsmMsrBitFieldRead64 (MSR_IA32_APIC_BASE_ADDRESS, 8, 8) =3D=3D 1) = { > + MsrApicBase.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); > + if (MsrApicBase.Bits.BSP =3D=3D 1) { > if (mDebugMpContext.BspIndex !=3D ProcessorIndex) { > AcquireMpSpinLock (&mDebugMpContext.MpContextSpinLock); > mDebugMpContext.BspIndex =3D ProcessorIndex; > diff --git a/UefiCpuPkg/CpuMpPei/CpuMpPei.h b/UefiCpuPkg/CpuMpPei/CpuMpPe= i.h > index b2e578b..0d1a14a 100644 > --- a/UefiCpuPkg/CpuMpPei/CpuMpPei.h > +++ b/UefiCpuPkg/CpuMpPei/CpuMpPei.h > @@ -25,6 +25,7 @@ >=20 > #include > #include > +#include >=20 > #include > #include > diff --git a/UefiCpuPkg/CpuMpPei/PeiMpServices.c b/UefiCpuPkg/CpuMpPei/Pe= iMpServices.c > index e784377..e06fdf1 100644 > --- a/UefiCpuPkg/CpuMpPei/PeiMpServices.c > +++ b/UefiCpuPkg/CpuMpPei/PeiMpServices.c > @@ -1,7 +1,7 @@ > /** @file > Implementation of Multiple Processor PPI services. >=20 > - Copyright (c) 2015, Intel Corporation. All rights reserved.
> + Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD License > which accompanies this distribution. The full text of the license may= be found at > @@ -729,9 +729,9 @@ PeiSwitchBSP ( > IN BOOLEAN EnableOldBSP > ) > { > - PEI_CPU_MP_DATA *PeiCpuMpData; > - UINTN CallerNumber; > - MSR_IA32_APIC_BASE ApicBaseMsr; > + PEI_CPU_MP_DATA *PeiCpuMpData; > + UINTN CallerNumber; > + MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; >=20 > PeiCpuMpData =3D GetMpHobData (); > if (PeiCpuMpData =3D=3D NULL) { > @@ -774,9 +774,9 @@ PeiSwitchBSP ( > // > // Clear the BSP bit of MSR_IA32_APIC_BASE > // > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS); > - ApicBaseMsr.Bits.Bsp =3D 0; > - AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64); > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); > + ApicBaseMsr.Bits.BSP =3D 0; > + AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); >=20 > PeiCpuMpData->BSPInfo.State =3D CPU_SWITCH_STATE_IDLE; > PeiCpuMpData->APInfo.State =3D CPU_SWITCH_STATE_IDLE; > @@ -805,9 +805,9 @@ PeiSwitchBSP ( > // > // Set the BSP bit of MSR_IA32_APIC_BASE on new BSP > // > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS); > - ApicBaseMsr.Bits.Bsp =3D 1; > - AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64); > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); > + ApicBaseMsr.Bits.BSP =3D 1; > + AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); > // > // Set old BSP enable state > // > diff --git a/UefiCpuPkg/Include/Register/LocalApic.h > b/UefiCpuPkg/Include/Register/LocalApic.h > index 346cce6..cfb6d76 100644 > --- a/UefiCpuPkg/Include/Register/LocalApic.h > +++ b/UefiCpuPkg/Include/Register/LocalApic.h > @@ -1,7 +1,7 @@ > /** @file > IA32 Local APIC Definitions. >=20 > - Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
> + Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD License > which accompanies this distribution. The full text of the license may= be found at > @@ -16,11 +16,6 @@ > #define __LOCAL_APIC_H__ >=20 > // > -// Definitions for IA32 architectural MSRs > -// > -#define MSR_IA32_APIC_BASE_ADDRESS 0x1B > - > -// > // Definition for Local APIC registers and related values > // > #define XAPIC_ID_OFFSET 0x20 > @@ -53,19 +48,6 @@ > #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2 > #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3 >=20 > -typedef union { > - struct { > - UINT32 Reserved0:8; ///< Reserved. > - UINT32 Bsp:1; ///< Processor is BSP. > - UINT32 Reserved1:1; ///< Reserved. > - UINT32 Extd:1; ///< Enable x2APIC mode. > - UINT32 En:1; ///< xAPIC global enable/disable. > - UINT32 ApicBaseLow:20; ///< APIC Base physical address. The actual= field width > depends on physical address width. > - UINT32 ApicBaseHigh:32; > - } Bits; > - UINT64 Uint64; > -} MSR_IA32_APIC_BASE; > - > // > // Local APIC Version Register. > // > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > index 1fca66e..8d0fb02 100644 > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > @@ -3,7 +3,7 @@ >=20 > This local APIC library instance supports xAPIC mode only. >=20 > - Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
> + Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD License > which accompanies this distribution. The full text of the license may= be found at > @@ -15,6 +15,7 @@ > **/ >=20 > #include > +#include > #include >=20 > #include > @@ -67,7 +68,7 @@ GetLocalApicBaseAddress ( > VOID > ) > { > - MSR_IA32_APIC_BASE ApicBaseMsr; > + MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; >=20 > if (!LocalApicBaseAddressMsrSupported ()) { > // > @@ -77,10 +78,10 @@ GetLocalApicBaseAddress ( > return PcdGet32 (PcdCpuLocalApicBaseAddress); > } >=20 > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS); > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); >=20 > - return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32))= + > - (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12); > + return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + > + (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); > } >=20 > /** > @@ -97,7 +98,7 @@ SetLocalApicBaseAddress ( > IN UINTN BaseAddress > ) > { > - MSR_IA32_APIC_BASE ApicBaseMsr; > + MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; >=20 > ASSERT ((BaseAddress & (SIZE_4KB - 1)) =3D=3D 0); >=20 > @@ -108,12 +109,12 @@ SetLocalApicBaseAddress ( > return; > } >=20 > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS); > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); >=20 > - ApicBaseMsr.Bits.ApicBaseLow =3D (UINT32) (BaseAddress >> 12); > - ApicBaseMsr.Bits.ApicBaseHigh =3D (UINT32) (RShiftU64((UINT64) BaseAdd= ress, 32)); > + ApicBaseMsr.Bits.ApicBase =3D (UINT32) (BaseAddress >> 12); > + ApicBaseMsr.Bits.ApicBaseHi =3D (UINT32) (RShiftU64((UINT64) BaseAddre= ss, 32)); >=20 > - AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64); > + AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); > } >=20 > /** > @@ -246,18 +247,18 @@ GetApicMode ( > { > DEBUG_CODE ( > { > - MSR_IA32_APIC_BASE ApicBaseMsr; > + MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; >=20 > // > // Check to see if the CPU supports the APIC Base Address MSR > // > if (LocalApicBaseAddressMsrSupported ()) { > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS)= ; > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); > // > // Local APIC should have been enabled > // > - ASSERT (ApicBaseMsr.Bits.En !=3D 0); > - ASSERT (ApicBaseMsr.Bits.Extd =3D=3D 0); > + ASSERT (ApicBaseMsr.Bits.EN !=3D 0); > + ASSERT (ApicBaseMsr.Bits.EXTD =3D=3D 0); > } > } > ); > diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > index 38f5370..4c42696 100644 > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > @@ -4,7 +4,7 @@ > This local APIC library instance supports x2APIC capable processors > which have xAPIC and x2APIC modes. >=20 > - Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
> + Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
> This program and the accompanying materials > are licensed and made available under the terms and conditions of the = BSD License > which accompanies this distribution. The full text of the license may= be found at > @@ -16,6 +16,7 @@ > **/ >=20 > #include > +#include > #include >=20 > #include > @@ -68,7 +69,7 @@ GetLocalApicBaseAddress ( > VOID > ) > { > - MSR_IA32_APIC_BASE ApicBaseMsr; > + MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; >=20 > if (!LocalApicBaseAddressMsrSupported ()) { > // > @@ -78,10 +79,10 @@ GetLocalApicBaseAddress ( > return PcdGet32 (PcdCpuLocalApicBaseAddress); > } >=20 > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS); > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); >=20 > - return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32))= + > - (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12); > + return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + > + (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); > } >=20 > /** > @@ -98,7 +99,7 @@ SetLocalApicBaseAddress ( > IN UINTN BaseAddress > ) > { > - MSR_IA32_APIC_BASE ApicBaseMsr; > + MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; >=20 > ASSERT ((BaseAddress & (SIZE_4KB - 1)) =3D=3D 0); >=20 > @@ -109,12 +110,12 @@ SetLocalApicBaseAddress ( > return; > } >=20 > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS); > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); >=20 > - ApicBaseMsr.Bits.ApicBaseLow =3D (UINT32) (BaseAddress >> 12); > - ApicBaseMsr.Bits.ApicBaseHigh =3D (UINT32) (RShiftU64((UINT64) BaseAdd= ress, 32)); > + ApicBaseMsr.Bits.ApicBase =3D (UINT32) (BaseAddress >> 12); > + ApicBaseMsr.Bits.ApicBaseHi =3D (UINT32) (RShiftU64((UINT64) BaseAddre= ss, 32)); >=20 > - AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64); > + AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); > } >=20 > /** > @@ -301,7 +302,7 @@ GetApicMode ( > VOID > ) > { > - MSR_IA32_APIC_BASE ApicBaseMsr; > + MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; >=20 > if (!LocalApicBaseAddressMsrSupported ()) { > // > @@ -310,12 +311,12 @@ GetApicMode ( > return LOCAL_APIC_MODE_XAPIC; > } >=20 > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS); > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); > // > // Local APIC should have been enabled > // > - ASSERT (ApicBaseMsr.Bits.En !=3D 0); > - if (ApicBaseMsr.Bits.Extd !=3D 0) { > + ASSERT (ApicBaseMsr.Bits.EN !=3D 0); > + if (ApicBaseMsr.Bits.EXTD !=3D 0) { > return LOCAL_APIC_MODE_X2APIC; > } else { > return LOCAL_APIC_MODE_XAPIC; > @@ -339,8 +340,8 @@ SetApicMode ( > IN UINTN ApicMode > ) > { > - UINTN CurrentMode; > - MSR_IA32_APIC_BASE ApicBaseMsr; > + UINTN CurrentMode; > + MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; >=20 > if (!LocalApicBaseAddressMsrSupported ()) { > // > @@ -355,9 +356,9 @@ SetApicMode ( > case LOCAL_APIC_MODE_XAPIC: > break; > case LOCAL_APIC_MODE_X2APIC: > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS)= ; > - ApicBaseMsr.Bits.Extd =3D 1; > - AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64); > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); > + ApicBaseMsr.Bits.EXTD =3D 1; > + AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); > break; > default: > ASSERT (FALSE); > @@ -369,12 +370,12 @@ SetApicMode ( > // Transition from x2APIC mode to xAPIC mode is a two-step proc= ess: > // x2APIC -> Local APIC disabled -> xAPIC > // > - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS)= ; > - ApicBaseMsr.Bits.Extd =3D 0; > - ApicBaseMsr.Bits.En =3D 0; > - AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64); > - ApicBaseMsr.Bits.En =3D 1; > - AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64); > + ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); > + ApicBaseMsr.Bits.EXTD =3D 0; > + ApicBaseMsr.Bits.EN =3D 0; > + AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); > + ApicBaseMsr.Bits.EN =3D 1; > + AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); > break; > case LOCAL_APIC_MODE_X2APIC: > break; > -- > 2.7.4.windows.1