From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) (using TLSv1 with cipher CAMELLIA256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 164D21A1E28 for ; Thu, 27 Oct 2016 16:15:40 -0700 (PDT) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP; 27 Oct 2016 16:15:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,406,1473145200"; d="scan'208";a="24950807" Received: from orsmsx103.amr.corp.intel.com ([10.22.225.130]) by orsmga004.jf.intel.com with ESMTP; 27 Oct 2016 16:15:39 -0700 Received: from orsmsx116.amr.corp.intel.com (10.22.240.14) by ORSMSX103.amr.corp.intel.com (10.22.225.130) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 27 Oct 2016 16:15:38 -0700 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.50]) by ORSMSX116.amr.corp.intel.com ([10.22.240.14]) with mapi id 14.03.0248.002; Thu, 27 Oct 2016 16:15:38 -0700 From: "Kinney, Michael D" To: Leo Duran , "edk2-devel@lists.01.org" , "Kinney, Michael D" CC: "Gao, Liming" , "Fan, Jeff" Thread-Topic: [edk2] [PATCH] UefiCpuPkg: Move GetProcessorLocation() to SmmCpuFeaturesLib library. Thread-Index: AQHSMKHCuIz5jZyGbkqpkSasc5VoAaC87XMw Date: Thu, 27 Oct 2016 23:15:37 +0000 Message-ID: References: <1477607390-8225-1-git-send-email-leo.duran@amd.com> <1477607390-8225-2-git-send-email-leo.duran@amd.com> In-Reply-To: <1477607390-8225-2-git-send-email-leo.duran@amd.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOWYyNWZjMWEtZmU1MC00ZjgxLWIwNzktYzZlYjU2NDNmZjc5IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IlpCbWNYaVZOMVBZdW5UN3V0bHJaZFdleWJTRFwveVZvN2RWTTZMbHZcL21YYz0ifQ== x-originating-ip: [10.22.254.138] MIME-Version: 1.0 Subject: Re: [PATCH] UefiCpuPkg: Move GetProcessorLocation() to SmmCpuFeaturesLib library. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 27 Oct 2016 23:15:40 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Leo, This looks like a good proposed change to the SmmFeaturesLib and PiSmmCpuDxeSmm module. Adding UefiCpuPkg maintainer Jeff Fan to the Cc list. There are 3 implementations of the SmmFeaturesLib in edk2/master. This patch needs to update all 3, or some of the platforms in=20 edk2/master will no longer build: * OvmfPkg\Library\SmmCpuFeaturesLib * QuarkSocPkg\QuarkNorthCluster\Library\SmmCpuFeaturesLib * UefiCpuPkg\Library\SmmCpuFeaturesLib Thanks, Mike > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Le= o Duran > Sent: Thursday, October 27, 2016 3:30 PM > To: edk2-devel@lists.01.org > Cc: Leo Duran ; Gao, Liming > Subject: [edk2] [PATCH] UefiCpuPkg: Move GetProcessorLocation() to SmmCpu= FeaturesLib > library. >=20 > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver > 2) Add SmmCpuFeaturesGetProcessorLocation() to SmmCpuFeaturesLib library >=20 > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Leo Duran > --- > UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h | 17 +++ > .../Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c | 118 +++++++++++++++= +++++ > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 121 +--------------= ------ > 3 files changed, 136 insertions(+), 120 deletions(-) >=20 > diff --git a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h > b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h > index 4478003..dd14ec5 100644 > --- a/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h > +++ b/UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h > @@ -398,4 +398,21 @@ SmmCpuFeaturesAllocatePageTableMemory ( > IN UINTN Pages > ); >=20 > +/** > + Get Package ID/Core ID/Thread ID of a processor. > + > + APIC ID must be an initial APIC ID. > + > + The algorithm assumes the target system has symmetry across physical p= ackage > boundaries > + with respect to the number of logical processors per package, number o= f cores per > package. > + > + @param ApicId APIC ID of the target logical processor. > + @param Location Returns the processor location information. > +**/ > +VOID > +SmmCpuFeaturesGetProcessorLocation ( > + IN UINT32 ApicId, > + OUT EFI_CPU_PHYSICAL_LOCATION *Location > + ); > + > #endif > diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > index 1754f2d..1e300f3 100644 > --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c > @@ -673,3 +673,121 @@ SmmCpuFeaturesAllocatePageTableMemory ( > return NULL; > } >=20 > +/** > + Get Package ID/Core ID/Thread ID of a processor. > + > + APIC ID must be an initial APIC ID. > + > + The algorithm below assumes the target system has symmetry across phys= ical package > boundaries > + with respect to the number of logical processors per package, number o= f cores per > package. > + > + @param ApicId APIC ID of the target logical processor. > + @param Location Returns the processor location information. > +**/ > +VOID > +SmmCpuFeaturesGetProcessorLocation ( > + IN UINT32 ApicId, > + OUT EFI_CPU_PHYSICAL_LOCATION *Location > + ) > +{ > + UINTN ThreadBits; > + UINTN CoreBits; > + UINT32 RegEax; > + UINT32 RegEbx; > + UINT32 RegEcx; > + UINT32 RegEdx; > + UINT32 MaxCpuIdIndex; > + UINT32 SubIndex; > + UINTN LevelType; > + UINT32 MaxLogicProcessorsPerPackage; > + UINT32 MaxCoresPerPackage; > + BOOLEAN TopologyLeafSupported; > + > + ASSERT (Location !=3D NULL); > + > + ThreadBits =3D 0; > + CoreBits =3D 0; > + TopologyLeafSupported =3D FALSE; > + > + // > + // Check if the processor is capable of supporting more than one logic= al processor. > + // > + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); > + ASSERT ((RegEdx & BIT28) !=3D 0); > + > + // > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > + // > + > + // > + // Get the max index of basic CPUID > + // > + AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > + > + // > + // If the extended topology enumeration leaf is available, it > + // is the preferred mechanism for enumerating topology. > + // > + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > + AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, N= ULL); > + // > + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input= value for > + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf = is not > + // supported on that processor. > + // > + if ((RegEbx & 0xffff) !=3D 0) { > + TopologyLeafSupported =3D TRUE; > + > + // > + // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration param= eters to extract > + // the SMT sub-field of x2APIC ID. > + // > + LevelType =3D (RegEcx >> 8) & 0xff; > + ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > + if ((RegEbx & 0xffff) > 1 ) { > + ThreadBits =3D RegEax & 0x1f; > + } else { > + // > + // HT is not supported > + // > + ThreadBits =3D 0; > + } > + > + // > + // Software must not assume any "level type" encoding > + // value to be related to any sub-leaf index, except sub-leaf 0. > + // > + SubIndex =3D 1; > + do { > + AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &R= egEcx, NULL); > + LevelType =3D (RegEcx >> 8) & 0xff; > + if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > + CoreBits =3D (RegEax & 0x1f) - ThreadBits; > + break; > + } > + SubIndex++; > + } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID= ); > + } > + } > + > + if (!TopologyLeafSupported) { > + AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); > + MaxLogicProcessorsPerPackage =3D (RegEbx >> 16) & 0xff; > + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > + AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); > + MaxCoresPerPackage =3D (RegEax >> 26) + 1; > + } else { > + // > + // Must be a single-core processor. > + // > + MaxCoresPerPackage =3D 1; > + } > + > + ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > + CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > + } > + > + Location->Thread =3D ApicId & ~((-1) << ThreadBits); > + Location->Core =3D (ApicId >> ThreadBits) & ~((-1) << CoreBits); > + Location->Package =3D (ApicId >> (ThreadBits+ CoreBits)); > +} > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > index 40f2a17..2bfb1e8 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService =3D { > }; >=20 > /** > - Get Package ID/Core ID/Thread ID of a processor. > - > - APIC ID must be an initial APIC ID. > - > - The algorithm below assumes the target system has symmetry across phys= ical package > boundaries > - with respect to the number of logical processors per package, number o= f cores per > package. > - > - @param ApicId APIC ID of the target logical processor. > - @param Location Returns the processor location information. > -**/ > -VOID > -SmmGetProcessorLocation ( > - IN UINT32 ApicId, > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > - ) > -{ > - UINTN ThreadBits; > - UINTN CoreBits; > - UINT32 RegEax; > - UINT32 RegEbx; > - UINT32 RegEcx; > - UINT32 RegEdx; > - UINT32 MaxCpuIdIndex; > - UINT32 SubIndex; > - UINTN LevelType; > - UINT32 MaxLogicProcessorsPerPackage; > - UINT32 MaxCoresPerPackage; > - BOOLEAN TopologyLeafSupported; > - > - ASSERT (Location !=3D NULL); > - > - ThreadBits =3D 0; > - CoreBits =3D 0; > - TopologyLeafSupported =3D FALSE; > - > - // > - // Check if the processor is capable of supporting more than one logic= al processor. > - // > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); > - ASSERT ((RegEdx & BIT28) !=3D 0); > - > - // > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > - // > - > - // > - // Get the max index of basic CPUID > - // > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > - > - // > - // If the extended topology enumeration leaf is available, it > - // is the preferred mechanism for enumerating topology. > - // > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, N= ULL); > - // > - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input= value for > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf = is not > - // supported on that processor. > - // > - if ((RegEbx & 0xffff) !=3D 0) { > - TopologyLeafSupported =3D TRUE; > - > - // > - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration param= eters to extract > - // the SMT sub-field of x2APIC ID. > - // > - LevelType =3D (RegEcx >> 8) & 0xff; > - ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > - if ((RegEbx & 0xffff) > 1 ) { > - ThreadBits =3D RegEax & 0x1f; > - } else { > - // > - // HT is not supported > - // > - ThreadBits =3D 0; > - } > - > - // > - // Software must not assume any "level type" encoding > - // value to be related to any sub-leaf index, except sub-leaf 0. > - // > - SubIndex =3D 1; > - do { > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &R= egEcx, NULL); > - LevelType =3D (RegEcx >> 8) & 0xff; > - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > - CoreBits =3D (RegEax & 0x1f) - ThreadBits; > - break; > - } > - SubIndex++; > - } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID= ); > - } > - } > - > - if (!TopologyLeafSupported) { > - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); > - MaxLogicProcessorsPerPackage =3D (RegEbx >> 16) & 0xff; > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); > - MaxCoresPerPackage =3D (RegEax >> 26) + 1; > - } else { > - // > - // Must be a single-core processor. > - // > - MaxCoresPerPackage =3D 1; > - } > - > - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > - } > - > - Location->Thread =3D ApicId & ~((-1) << ThreadBits); > - Location->Core =3D (ApicId >> ThreadBits) & ~((-1) << CoreBits); > - Location->Package =3D (ApicId >> (ThreadBits+ CoreBits)); > -} > - > -/** > Gets processor information on the requested processor at the instant t= his call is > made. >=20 > @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_= PROTOCOL > instance. > @@ -280,7 +161,7 @@ SmmAddProcessor ( > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D=3D INVALID_= APIC_ID) { > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D ProcessorId; > gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag =3D 0; > - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate- > >ProcessorInfo[Index].Location); > + SmmCpuFeaturesGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuP= rivate- > >ProcessorInfo[Index].Location); >=20 > *ProcessorNumber =3D Index; > gSmmCpuPrivate->Operation[Index] =3D SmmCpuAdd; > -- > 1.9.1 >=20 > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel