From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7613181DB1 for ; Fri, 28 Oct 2016 14:12:19 -0700 (PDT) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP; 28 Oct 2016 14:12:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,411,1473145200"; d="scan'208";a="779232521" Received: from orsmsx108.amr.corp.intel.com ([10.22.240.6]) by FMSMGA003.fm.intel.com with ESMTP; 28 Oct 2016 14:12:19 -0700 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.50]) by ORSMSX108.amr.corp.intel.com ([10.22.240.6]) with mapi id 14.03.0248.002; Fri, 28 Oct 2016 14:12:18 -0700 From: "Kinney, Michael D" To: Leo Duran , "edk2-devel@lists.01.org" CC: "Gao, Liming" , "lersek@redhat.com" , "Fan, Jeff" Thread-Topic: [v3] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library Thread-Index: AQHSMUIvBzycoUW3rUSvfbsz4wQt36C+V69Q Date: Fri, 28 Oct 2016 21:12:17 +0000 Message-ID: References: <1477676325-18717-1-git-send-email-leo.duran@amd.com> In-Reply-To: <1477676325-18717-1-git-send-email-leo.duran@amd.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiMTk5MmQ0MDEtYWU3NS00YjVkLTkwNDAtYWNjNzU2Njg5ZWFjIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Ik1PMXhrNG43bzZpM3F1Q3ZLQVVvOG5MbWpud1BYXC9xRmtmYTRobzRFdjBnPSJ9 x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Subject: Re: [v3] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 28 Oct 2016 21:12:19 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Leo, I tested your patch on Quark and it builds and boots. Here is a slightly updated version of the patch that makes the following ch= anges: * Follow Jeff Fan suggestion to pass in Package, Core, Thread as 3 paramete= rs. This removes the dependency on PiPei.h and MpService.h from LocalApicLib.= h so LocalApicLib can be used from more than just PEI/DXE phases. I also m= ade these three OUT parameters OPTIONAL. * Change tabs to spaces and fix other minor format issues to pass checks fr= om BaseTools/Scripts/PatchCheck.py I have also tested this updated patch on Quark and it also builds and boots= . >>From cc932ca811e052a0a3ae103a9db9614b3807d4ed Mon Sep 17 00:00:00 2001 From: Leo Duran Date: Fri, 28 Oct 2016 10:38:45 -0700 Subject: [Patch] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib library 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. 2) Remove ExtractProcessorLocation() from MpInitLib library. 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. Cc: Jeff Fan Cc: Laszlo Ersek Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran --- UefiCpuPkg/Include/Library/LocalApicLib.h | 21 +++ UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 148 +++++++++++++++++= ++++ .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 148 +++++++++++++++++= ++++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 133 +----------------= - UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 126 +----------------= - 5 files changed, 329 insertions(+), 247 deletions(-) diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include= /Library/LocalApicLib.h index cd4e613..d73198f 100644 --- a/UefiCpuPkg/Include/Library/LocalApicLib.h +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h @@ -410,6 +410,27 @@ GetApicMsiValue ( IN BOOLEAN LevelTriggered, IN BOOLEAN AssertionLevel ); + +/** + Get Package ID/Core ID/Thread ID of a processor. + + The algorithm assumes the target system has symmetry across physical pac= kage + boundaries with respect to the number of logical processors per package, + number of cores per package. + + @param[in] InitialApicId Must be the initial APIC ID of the target lo= gical + processor. + @param[out] Package Returns the processor package ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +GetProcessorLocation( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ); =20 #endif =20 diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Li= brary/BaseXApicLib/BaseXApicLib.c index 8d0fb02..7ddee1b 100644 --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c @@ -941,3 +941,151 @@ GetApicMsiValue ( } return MsiData.Uint64; } + +/** + Get Package ID/Core ID/Thread ID of a processor. + + The algorithm assumes the target system has symmetry across physical pac= kage + boundaries with respect to the number of logical processors per package, + number of cores per package. + + @param[in] InitialApicId Must be the initial APIC ID of the target lo= gical + processor. + @param[out] Package Returns the processor package ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +GetProcessorLocation( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + BOOLEAN TopologyLeafSupported; + UINTN ThreadBits; + UINTN CoreBits; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + + // + // Check if the processor is capable of supporting more than one logical= processor. + // + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + if (VersionInfoEdx.Bits.HTT =3D=3D 0) { + if (Thread !=3D NULL) { + *Thread =3D 0; + } + if (Core !=3D NULL) { + *Core =3D 0; + } + if (Package !=3D NULL) { + *Package =3D 0; + } + return; + } + + ThreadBits =3D 0; + CoreBits =3D 0; + + // + // Assume three-level mapping of APIC ID: Package:Core:SMT. + // + + TopologyLeafSupported =3D FALSE; + // + // Get the max index of basic CPUID + // + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + + // + // If the extended topology enumeration leaf is available, it + // is the preferred mechanism for enumerating topology. + // + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + 0, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + // + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not + // supported on that processor. + // + if (ExtendedTopologyEbx.Uint32 !=3D 0) { + TopologyLeafSupported =3D TRUE; + + // + // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract + // the SMT sub-field of x2APIC ID. + // + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; + ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; + + // + // Software must not assume any "level type" encoding + // value to be related to any sub-leaf index, except sub-leaf 0. + // + SubIndex =3D 1; + do { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + SubIndex, + &ExtendedTopologyEax.Uint32, + NULL, + &ExtendedTopologyEcx.Uint32, + NULL + ); + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; + if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { + CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; + break; + } + SubIndex++; + } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); + } + } + + if (!TopologyLeafSupported) { + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL)= ; + MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL= , NULL); + MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; + } + else { + // + // Must be a single-core processor. + // + MaxCoresPerPackage =3D 1; + } + + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / Max= CoresPerPackage - 1) + 1); + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + } + + if (Thread !=3D NULL) { + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); + } + if (Core !=3D NULL) { + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + } + if (Package !=3D NULL) { + *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); + } +} diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index 4c42696..c620211 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -1036,3 +1036,151 @@ GetApicMsiValue ( } return MsiData.Uint64; } + +/** + Get Package ID/Core ID/Thread ID of a processor. + + The algorithm assumes the target system has symmetry across physical pac= kage + boundaries with respect to the number of logical processors per package, + number of cores per package. + + @param[in] InitialApicId Must be the initial APIC ID of the target lo= gical + processor. + @param[out] Package Returns the processor package ID. + @param[out] Core Returns the processor core ID. + @param[out] Thread Returns the processor thread ID. +**/ +VOID +GetProcessorLocation( + IN UINT32 InitialApicId, + OUT UINT32 *Package OPTIONAL, + OUT UINT32 *Core OPTIONAL, + OUT UINT32 *Thread OPTIONAL + ) +{ + BOOLEAN TopologyLeafSupported; + UINTN ThreadBits; + UINTN CoreBits; + CPUID_VERSION_INFO_EBX VersionInfoEbx; + CPUID_VERSION_INFO_EDX VersionInfoEdx; + CPUID_CACHE_PARAMS_EAX CacheParamsEax; + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; + UINT32 MaxCpuIdIndex; + UINT32 SubIndex; + UINTN LevelType; + UINT32 MaxLogicProcessorsPerPackage; + UINT32 MaxCoresPerPackage; + + // + // Check if the processor is capable of supporting more than one logical= processor. + // + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); + if (VersionInfoEdx.Bits.HTT =3D=3D 0) { + if (Thread !=3D NULL) { + *Thread =3D 0; + } + if (Core !=3D NULL) { + *Core =3D 0; + } + if (Package !=3D NULL) { + *Package =3D 0; + } + return; + } + + ThreadBits =3D 0; + CoreBits =3D 0; + + // + // Assume three-level mapping of APIC ID: Package:Core:SMT. + // + + TopologyLeafSupported =3D FALSE; + // + // Get the max index of basic CPUID + // + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); + + // + // If the extended topology enumeration leaf is available, it + // is the preferred mechanism for enumerating topology. + // + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + 0, + &ExtendedTopologyEax.Uint32, + &ExtendedTopologyEbx.Uint32, + &ExtendedTopologyEcx.Uint32, + NULL + ); + // + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not + // supported on that processor. + // + if (ExtendedTopologyEbx.Uint32 !=3D 0) { + TopologyLeafSupported =3D TRUE; + + // + // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract + // the SMT sub-field of x2APIC ID. + // + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; + ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; + + // + // Software must not assume any "level type" encoding + // value to be related to any sub-leaf index, except sub-leaf 0. + // + SubIndex =3D 1; + do { + AsmCpuidEx( + CPUID_EXTENDED_TOPOLOGY, + SubIndex, + &ExtendedTopologyEax.Uint32, + NULL, + &ExtendedTopologyEcx.Uint32, + NULL + ); + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; + if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { + CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; + break; + } + SubIndex++; + } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); + } + } + + if (!TopologyLeafSupported) { + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL)= ; + MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL= , NULL); + MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; + } + else { + // + // Must be a single-core processor. + // + MaxCoresPerPackage =3D 1; + } + + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / Max= CoresPerPackage - 1) + 1); + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); + } + + if (Thread !=3D NULL) { + *Thread =3D InitialApicId & ((1 << ThreadBits) - 1); + } + if (Core !=3D NULL) { + *Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1); + } + if (Package !=3D NULL) { + *Package =3D (InitialApicId >> (ThreadBits + CoreBits)); + } +} diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index c3fe721..f205b6b 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( } =20 /** - Get CPU Package/Core/Thread location information. - - @param[in] InitialApicId CPU APIC ID - @param[out] Location Pointer to CPU location information -**/ -VOID -ExtractProcessorLocation ( - IN UINT32 InitialApicId, - OUT EFI_CPU_PHYSICAL_LOCATION *Location - ) -{ - BOOLEAN TopologyLeafSupported; - UINTN ThreadBits; - UINTN CoreBits; - CPUID_VERSION_INFO_EBX VersionInfoEbx; - CPUID_VERSION_INFO_EDX VersionInfoEdx; - CPUID_CACHE_PARAMS_EAX CacheParamsEax; - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; - - // - // Check if the processor is capable of supporting more than one logical= processor. - // - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); - if (VersionInfoEdx.Bits.HTT =3D=3D 0) { - Location->Thread =3D 0; - Location->Core =3D 0; - Location->Package =3D 0; - return; - } - - ThreadBits =3D 0; - CoreBits =3D 0; - - // - // Assume three-level mapping of APIC ID: Package:Core:SMT. - // - - TopologyLeafSupported =3D FALSE; - // - // Get the max index of basic CPUID - // - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); - - // - // If the extended topology enumeration leaf is available, it - // is the preferred mechanism for enumerating topology. - // - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx ( - CPUID_EXTENDED_TOPOLOGY, - 0, - &ExtendedTopologyEax.Uint32, - &ExtendedTopologyEbx.Uint32, - &ExtendedTopologyEcx.Uint32, - NULL - ); - // - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not - // supported on that processor. - // - if (ExtendedTopologyEbx.Uint32 !=3D 0) { - TopologyLeafSupported =3D TRUE; - - // - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract - // the SMT sub-field of x2APIC ID. - // - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); - ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; - - // - // Software must not assume any "level type" encoding - // value to be related to any sub-leaf index, except sub-leaf 0. - // - SubIndex =3D 1; - do { - AsmCpuidEx ( - CPUID_EXTENDED_TOPOLOGY, - SubIndex, - &ExtendedTopologyEax.Uint32, - NULL, - &ExtendedTopologyEcx.Uint32, - NULL - ); - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { - CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; - break; - } - SubIndex++; - } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); - } - } - - if (!TopologyLeafSupported) { - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL= ); - MaxLogicProcessorsPerPackage =3D VersionInfoEbx.Bits.MaximumAddressabl= eIdsForLogicalProcessors; - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NUL= L, NULL); - MaxCoresPerPackage =3D CacheParamsEax.Bits.MaximumAddressableIdsForL= ogicalProcessors + 1; - } else { - // - // Must be a single-core processor. - // - MaxCoresPerPackage =3D 1; - } - - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / M= axCoresPerPackage - 1) + 1); - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); - } - - Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); - Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) -= 1); - Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); -} - -/** Worker function for SwitchBSP(). =20 Worker function for SwitchBSP(), assigned to the AP which is intended @@ -1451,7 +1325,12 @@ MpInitLibGetProcessorInfo ( // // Get processor location information // - ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, &P= rocessorInfoBuffer->Location); + GetProcessorLocation ( + CpuMpData->CpuData[ProcessorNumber].ApicId, + &ProcessorInfoBuffer->Location.Package, + &ProcessorInfoBuffer->Location.Core, + &ProcessorInfoBuffer->Location.Thread + ); =20 if (HealthData !=3D NULL) { HealthData->Uint32 =3D CpuMpData->CpuData[ProcessorNumber].Health; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/CpuService.c index 40f2a17..93ebb9e 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService =3D { }; =20 /** - Get Package ID/Core ID/Thread ID of a processor. - - APIC ID must be an initial APIC ID. - - The algorithm below assumes the target system has symmetry across physic= al package boundaries - with respect to the number of logical processors per package, number of = cores per package. - - @param ApicId APIC ID of the target logical processor. - @param Location Returns the processor location information. -**/ -VOID -SmmGetProcessorLocation ( - IN UINT32 ApicId, - OUT EFI_CPU_PHYSICAL_LOCATION *Location - ) -{ - UINTN ThreadBits; - UINTN CoreBits; - UINT32 RegEax; - UINT32 RegEbx; - UINT32 RegEcx; - UINT32 RegEdx; - UINT32 MaxCpuIdIndex; - UINT32 SubIndex; - UINTN LevelType; - UINT32 MaxLogicProcessorsPerPackage; - UINT32 MaxCoresPerPackage; - BOOLEAN TopologyLeafSupported; - - ASSERT (Location !=3D NULL); - - ThreadBits =3D 0; - CoreBits =3D 0; - TopologyLeafSupported =3D FALSE; - - // - // Check if the processor is capable of supporting more than one logical= processor. - // - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); - ASSERT ((RegEdx & BIT28) !=3D 0); - - // - // Assume three-level mapping of APIC ID: Package:Core:SMT. - // - - // - // Get the max index of basic CPUID - // - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); - - // - // If the extended topology enumeration leaf is available, it - // is the preferred mechanism for enumerating topology. - // - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NUL= L); - // - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not - // supported on that processor. - // - if ((RegEbx & 0xffff) !=3D 0) { - TopologyLeafSupported =3D TRUE; - - // - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramet= ers to extract - // the SMT sub-field of x2APIC ID. - // - LevelType =3D (RegEcx >> 8) & 0xff; - ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); - if ((RegEbx & 0xffff) > 1 ) { - ThreadBits =3D RegEax & 0x1f; - } else { - // - // HT is not supported - // - ThreadBits =3D 0; - } - - // - // Software must not assume any "level type" encoding - // value to be related to any sub-leaf index, except sub-leaf 0. - // - SubIndex =3D 1; - do { - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &Reg= Ecx, NULL); - LevelType =3D (RegEcx >> 8) & 0xff; - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { - CoreBits =3D (RegEax & 0x1f) - ThreadBits; - break; - } - SubIndex++; - } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); - } - } - - if (!TopologyLeafSupported) { - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); - MaxLogicProcessorsPerPackage =3D (RegEbx >> 16) & 0xff; - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); - MaxCoresPerPackage =3D (RegEax >> 26) + 1; - } else { - // - // Must be a single-core processor. - // - MaxCoresPerPackage =3D 1; - } - - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / M= axCoresPerPackage - 1) + 1); - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); - } - - Location->Thread =3D ApicId & ~((-1) << ThreadBits); - Location->Core =3D (ApicId >> ThreadBits) & ~((-1) << CoreBits); - Location->Package =3D (ApicId >> (ThreadBits+ CoreBits)); -} - -/** Gets processor information on the requested processor at the instant thi= s call is made. =20 @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_PR= OTOCOL instance. @@ -280,7 +161,12 @@ SmmAddProcessor ( gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D=3D INVALID_AP= IC_ID) { gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D ProcessorId; gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag =3D 0; - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate->Proce= ssorInfo[Index].Location); + GetProcessorLocation ( + (UINT32)ProcessorId, + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Package, + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Core, + &gSmmCpuPrivate->ProcessorInfo[Index].Location.Thread + ); =20 *ProcessorNumber =3D Index; gSmmCpuPrivate->Operation[Index] =3D SmmCpuAdd; --=20 2.6.3.windows.1 Best regards, Mike > -----Original Message----- > From: Leo Duran [mailto:leo.duran@amd.com] > Sent: Friday, October 28, 2016 10:39 AM > To: edk2-devel@lists.01.org > Cc: Gao, Liming ; lersek@redhat.com; Fan, Jeff > ; Kinney, Michael D ; Leo= Duran > > Subject: [v3] UefiCpuPkg: Move GetProcessorLocation() to LocalApicLib lib= rary >=20 > 1) Remove SmmGetProcessorLocation() from PiSmmCpuDxeSmm driver. > 2) Remove ExtractProcessorLocation() from MpInitLib library. > 3) Add GetProcessorLocation() to BaseXApicLib and BaseXApicX2ApicLib. >=20 > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Leo Duran > --- > UefiCpuPkg/Include/Library/LocalApicLib.h | 18 +++ > UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c | 130 +++++++++++++++= ++++++ > .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 130 +++++++++++++++= ++++++ > UefiCpuPkg/Library/MpInitLib/MpLib.c | 128 +--------------= ----- > UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c | 121 +--------------= ---- > 5 files changed, 280 insertions(+), 247 deletions(-) >=20 > diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h > b/UefiCpuPkg/Include/Library/LocalApicLib.h > index cd4e613..4abf64c 100644 > --- a/UefiCpuPkg/Include/Library/LocalApicLib.h > +++ b/UefiCpuPkg/Include/Library/LocalApicLib.h > @@ -21,6 +21,9 @@ > #define LOCAL_APIC_MODE_XAPIC 0x1 ///< xAPIC mode. > #define LOCAL_APIC_MODE_X2APIC 0x2 ///< x2APIC mode. >=20 > +#include > +#include > + > /** > Retrieve the base address of local APIC. >=20 > @@ -410,6 +413,21 @@ GetApicMsiValue ( > IN BOOLEAN LevelTriggered, > IN BOOLEAN AssertionLevel > ); > + > +/** > +Get Package ID/Core ID/Thread ID of a processor. > + > +The algorithm assumes the target system has symmetry across physical pac= kage > boundaries > +with respect to the number of logical processors per package, number of = cores per > package. > + > +@param InitialApicId Must be the initial APIC ID of the target logical= processor. > +@param Location Returns the processor location information. > +**/ > +VOID > +GetProcessorLocation( > + IN UINT32 InitialApicId, > + OUT EFI_CPU_PHYSICAL_LOCATION *Location > +); >=20 > #endif >=20 > diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > index 8d0fb02..219f99f 100644 > --- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c > @@ -941,3 +941,133 @@ GetApicMsiValue ( > } > return MsiData.Uint64; > } > + > +/** > +Get Package ID/Core ID/Thread ID of a processor. > + > +The algorithm assumes the target system has symmetry across physical pac= kage > boundaries > +with respect to the number of logical processors per package, number of = cores per > package. > + > +@param InitialApicId Must be the initial APIC ID of the target logical= processor. > +@param Location Returns the processor location information. > +**/ > +VOID > +GetProcessorLocation( > +IN UINT32 InitialApicId, > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > +) > +{ > + BOOLEAN TopologyLeafSupported; > + UINTN ThreadBits; > + UINTN CoreBits; > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > + UINT32 MaxCpuIdIndex; > + UINT32 SubIndex; > + UINTN LevelType; > + UINT32 MaxLogicProcessorsPerPackage; > + UINT32 MaxCoresPerPackage; > + > + // > + // Check if the processor is capable of supporting more than one logica= l > processor. > + // > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); > + if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > + Location->Thread =3D 0; > + Location->Core =3D 0; > + Location->Package =3D 0; > + return; > + } > + > + ThreadBits =3D 0; > + CoreBits =3D 0; > + > + // > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > + // > + > + TopologyLeafSupported =3D FALSE; > + // > + // Get the max index of basic CPUID > + // > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > + > + // > + // If the extended topology enumeration leaf is available, it > + // is the preferred mechanism for enumerating topology. > + // > + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + 0, > + &ExtendedTopologyEax.Uint32, > + &ExtendedTopologyEbx.Uint32, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + // > + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for > + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not > + // supported on that processor. > + // > + if (ExtendedTopologyEbx.Uint32 !=3D 0) { > + TopologyLeafSupported =3D TRUE; > + > + // > + // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramete= rs to > extract > + // the SMT sub-field of x2APIC ID. > + // > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > + ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > + > + // > + // Software must not assume any "level type" encoding > + // value to be related to any sub-leaf index, except sub-leaf 0. > + // > + SubIndex =3D 1; > + do { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + SubIndex, > + &ExtendedTopologyEax.Uint32, > + NULL, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > + if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > + CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > + break; > + } > + SubIndex++; > + } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > + } > + } > + > + if (!TopologyLeafSupported) { > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL)= ; > + MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, > NULL); > + MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > + } > + else { > + // > + // Must be a single-core processor. > + // > + MaxCoresPerPackage =3D 1; > + } > + > + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); > + } > + > + Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > + Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1= ); > + Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); > +} > diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > index 4c42696..16395a3 100644 > --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c > @@ -1036,3 +1036,133 @@ GetApicMsiValue ( > } > return MsiData.Uint64; > } > + > +/** > +Get Package ID/Core ID/Thread ID of a processor. > + > +The algorithm assumes the target system has symmetry across physical pac= kage > boundaries > +with respect to the number of logical processors per package, number of = cores per > package. > + > +@param InitialApicId Must be the initial APIC ID of the target logical= processor. > +@param Location Returns the processor location information. > +**/ > +VOID > +GetProcessorLocation( > +IN UINT32 InitialApicId, > +OUT EFI_CPU_PHYSICAL_LOCATION *Location > +) > +{ > + BOOLEAN TopologyLeafSupported; > + UINTN ThreadBits; > + UINTN CoreBits; > + CPUID_VERSION_INFO_EBX VersionInfoEbx; > + CPUID_VERSION_INFO_EDX VersionInfoEdx; > + CPUID_CACHE_PARAMS_EAX CacheParamsEax; > + CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > + CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > + CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > + UINT32 MaxCpuIdIndex; > + UINT32 SubIndex; > + UINTN LevelType; > + UINT32 MaxLogicProcessorsPerPackage; > + UINT32 MaxCoresPerPackage; > + > + // > + // Check if the processor is capable of supporting more than one logica= l > processor. > + // > + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32); > + if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > + Location->Thread =3D 0; > + Location->Core =3D 0; > + Location->Package =3D 0; > + return; > + } > + > + ThreadBits =3D 0; > + CoreBits =3D 0; > + > + // > + // Assume three-level mapping of APIC ID: Package:Core:SMT. > + // > + > + TopologyLeafSupported =3D FALSE; > + // > + // Get the max index of basic CPUID > + // > + AsmCpuid(CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > + > + // > + // If the extended topology enumeration leaf is available, it > + // is the preferred mechanism for enumerating topology. > + // > + if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + 0, > + &ExtendedTopologyEax.Uint32, > + &ExtendedTopologyEbx.Uint32, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + // > + // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input v= alue for > + // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is= not > + // supported on that processor. > + // > + if (ExtendedTopologyEbx.Uint32 !=3D 0) { > + TopologyLeafSupported =3D TRUE; > + > + // > + // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration paramete= rs to > extract > + // the SMT sub-field of x2APIC ID. > + // > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > + ASSERT(LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > + ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > + > + // > + // Software must not assume any "level type" encoding > + // value to be related to any sub-leaf index, except sub-leaf 0. > + // > + SubIndex =3D 1; > + do { > + AsmCpuidEx( > + CPUID_EXTENDED_TOPOLOGY, > + SubIndex, > + &ExtendedTopologyEax.Uint32, > + NULL, > + &ExtendedTopologyEcx.Uint32, > + NULL > + ); > + LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > + if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > + CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits; > + break; > + } > + SubIndex++; > + } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID); > + } > + } > + > + if (!TopologyLeafSupported) { > + AsmCpuid(CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NULL)= ; > + MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > + if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > + AsmCpuidEx(CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, NULL, > NULL); > + MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > + } > + else { > + // > + // Must be a single-core processor. > + // > + MaxCoresPerPackage =3D 1; > + } > + > + ThreadBits =3D (UINTN)(HighBitSet32(MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > + CoreBits =3D (UINTN)(HighBitSet32(MaxCoresPerPackage - 1) + 1); > + } > + > + Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > + Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits) - 1= ); > + Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); > +} > diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c > b/UefiCpuPkg/Library/MpInitLib/MpLib.c > index c3fe721..f3380bb 100644 > --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c > +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c > @@ -58,132 +58,6 @@ IsBspExecuteDisableEnabled ( > } >=20 > /** > - Get CPU Package/Core/Thread location information. > - > - @param[in] InitialApicId CPU APIC ID > - @param[out] Location Pointer to CPU location information > -**/ > -VOID > -ExtractProcessorLocation ( > - IN UINT32 InitialApicId, > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > - ) > -{ > - BOOLEAN TopologyLeafSupported; > - UINTN ThreadBits; > - UINTN CoreBits; > - CPUID_VERSION_INFO_EBX VersionInfoEbx; > - CPUID_VERSION_INFO_EDX VersionInfoEdx; > - CPUID_CACHE_PARAMS_EAX CacheParamsEax; > - CPUID_EXTENDED_TOPOLOGY_EAX ExtendedTopologyEax; > - CPUID_EXTENDED_TOPOLOGY_EBX ExtendedTopologyEbx; > - CPUID_EXTENDED_TOPOLOGY_ECX ExtendedTopologyEcx; > - UINT32 MaxCpuIdIndex; > - UINT32 SubIndex; > - UINTN LevelType; > - UINT32 MaxLogicProcessorsPerPackage; > - UINT32 MaxCoresPerPackage; > - > - // > - // Check if the processor is capable of supporting more than one logic= al processor. > - // > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &VersionInfoEdx.Uint32= ); > - if (VersionInfoEdx.Bits.HTT =3D=3D 0) { > - Location->Thread =3D 0; > - Location->Core =3D 0; > - Location->Package =3D 0; > - return; > - } > - > - ThreadBits =3D 0; > - CoreBits =3D 0; > - > - // > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > - // > - > - TopologyLeafSupported =3D FALSE; > - // > - // Get the max index of basic CPUID > - // > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > - > - // > - // If the extended topology enumeration leaf is available, it > - // is the preferred mechanism for enumerating topology. > - // > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > - AsmCpuidEx ( > - CPUID_EXTENDED_TOPOLOGY, > - 0, > - &ExtendedTopologyEax.Uint32, > - &ExtendedTopologyEbx.Uint32, > - &ExtendedTopologyEcx.Uint32, > - NULL > - ); > - // > - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input= value for > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf = is not > - // supported on that processor. > - // > - if (ExtendedTopologyEbx.Uint32 !=3D 0) { > - TopologyLeafSupported =3D TRUE; > - > - // > - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration param= eters to extract > - // the SMT sub-field of x2APIC ID. > - // > - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > - ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > - ThreadBits =3D ExtendedTopologyEax.Bits.ApicIdShift; > - > - // > - // Software must not assume any "level type" encoding > - // value to be related to any sub-leaf index, except sub-leaf 0. > - // > - SubIndex =3D 1; > - do { > - AsmCpuidEx ( > - CPUID_EXTENDED_TOPOLOGY, > - SubIndex, > - &ExtendedTopologyEax.Uint32, > - NULL, > - &ExtendedTopologyEcx.Uint32, > - NULL > - ); > - LevelType =3D ExtendedTopologyEcx.Bits.LevelType; > - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > - CoreBits =3D ExtendedTopologyEax.Bits.ApicIdShift - ThreadBits= ; > - break; > - } > - SubIndex++; > - } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID= ); > - } > - } > - > - if (!TopologyLeafSupported) { > - AsmCpuid (CPUID_VERSION_INFO, NULL, &VersionInfoEbx.Uint32, NULL, NU= LL); > - MaxLogicProcessorsPerPackage =3D > VersionInfoEbx.Bits.MaximumAddressableIdsForLogicalProcessors; > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &CacheParamsEax.Uint32, NULL, N= ULL, NULL); > - MaxCoresPerPackage =3D > CacheParamsEax.Bits.MaximumAddressableIdsForLogicalProcessors + 1; > - } else { > - // > - // Must be a single-core processor. > - // > - MaxCoresPerPackage =3D 1; > - } > - > - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > - } > - > - Location->Thread =3D InitialApicId & ((1 << ThreadBits) - 1); > - Location->Core =3D (InitialApicId >> ThreadBits) & ((1 << CoreBits)= - 1); > - Location->Package =3D (InitialApicId >> (ThreadBits + CoreBits)); > -} > - > -/** > Worker function for SwitchBSP(). >=20 > Worker function for SwitchBSP(), assigned to the AP which is intended > @@ -1451,7 +1325,7 @@ MpInitLibGetProcessorInfo ( > // > // Get processor location information > // > - ExtractProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, > &ProcessorInfoBuffer->Location); > + GetProcessorLocation (CpuMpData->CpuData[ProcessorNumber].ApicId, > &ProcessorInfoBuffer->Location); >=20 > if (HealthData !=3D NULL) { > HealthData->Uint32 =3D CpuMpData->CpuData[ProcessorNumber].Health; > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > index 40f2a17..67cd0a0 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c > @@ -27,125 +27,6 @@ EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService =3D { > }; >=20 > /** > - Get Package ID/Core ID/Thread ID of a processor. > - > - APIC ID must be an initial APIC ID. > - > - The algorithm below assumes the target system has symmetry across phys= ical package > boundaries > - with respect to the number of logical processors per package, number o= f cores per > package. > - > - @param ApicId APIC ID of the target logical processor. > - @param Location Returns the processor location information. > -**/ > -VOID > -SmmGetProcessorLocation ( > - IN UINT32 ApicId, > - OUT EFI_CPU_PHYSICAL_LOCATION *Location > - ) > -{ > - UINTN ThreadBits; > - UINTN CoreBits; > - UINT32 RegEax; > - UINT32 RegEbx; > - UINT32 RegEcx; > - UINT32 RegEdx; > - UINT32 MaxCpuIdIndex; > - UINT32 SubIndex; > - UINTN LevelType; > - UINT32 MaxLogicProcessorsPerPackage; > - UINT32 MaxCoresPerPackage; > - BOOLEAN TopologyLeafSupported; > - > - ASSERT (Location !=3D NULL); > - > - ThreadBits =3D 0; > - CoreBits =3D 0; > - TopologyLeafSupported =3D FALSE; > - > - // > - // Check if the processor is capable of supporting more than one logic= al processor. > - // > - AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx); > - ASSERT ((RegEdx & BIT28) !=3D 0); > - > - // > - // Assume three-level mapping of APIC ID: Package:Core:SMT. > - // > - > - // > - // Get the max index of basic CPUID > - // > - AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL); > - > - // > - // If the extended topology enumeration leaf is available, it > - // is the preferred mechanism for enumerating topology. > - // > - if (MaxCpuIdIndex >=3D CPUID_EXTENDED_TOPOLOGY) { > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, N= ULL); > - // > - // If CPUID.(EAX=3D0BH, ECX=3D0H):EBX returns zero and maximum input= value for > - // basic CPUID information is greater than 0BH, then CPUID.0BH leaf = is not > - // supported on that processor. > - // > - if ((RegEbx & 0xffff) !=3D 0) { > - TopologyLeafSupported =3D TRUE; > - > - // > - // Sub-leaf index 0 (ECX=3D 0 as input) provides enumeration param= eters to extract > - // the SMT sub-field of x2APIC ID. > - // > - LevelType =3D (RegEcx >> 8) & 0xff; > - ASSERT (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT); > - if ((RegEbx & 0xffff) > 1 ) { > - ThreadBits =3D RegEax & 0x1f; > - } else { > - // > - // HT is not supported > - // > - ThreadBits =3D 0; > - } > - > - // > - // Software must not assume any "level type" encoding > - // value to be related to any sub-leaf index, except sub-leaf 0. > - // > - SubIndex =3D 1; > - do { > - AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &R= egEcx, NULL); > - LevelType =3D (RegEcx >> 8) & 0xff; > - if (LevelType =3D=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) { > - CoreBits =3D (RegEax & 0x1f) - ThreadBits; > - break; > - } > - SubIndex++; > - } while (LevelType !=3D CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID= ); > - } > - } > - > - if (!TopologyLeafSupported) { > - AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL); > - MaxLogicProcessorsPerPackage =3D (RegEbx >> 16) & 0xff; > - if (MaxCpuIdIndex >=3D CPUID_CACHE_PARAMS) { > - AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL); > - MaxCoresPerPackage =3D (RegEax >> 26) + 1; > - } else { > - // > - // Must be a single-core processor. > - // > - MaxCoresPerPackage =3D 1; > - } > - > - ThreadBits =3D (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / > MaxCoresPerPackage - 1) + 1); > - CoreBits =3D (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1); > - } > - > - Location->Thread =3D ApicId & ~((-1) << ThreadBits); > - Location->Core =3D (ApicId >> ThreadBits) & ~((-1) << CoreBits); > - Location->Package =3D (ApicId >> (ThreadBits+ CoreBits)); > -} > - > -/** > Gets processor information on the requested processor at the instant t= his call is > made. >=20 > @param[in] This A pointer to the EFI_SMM_CPU_SERVICE_= PROTOCOL > instance. > @@ -280,7 +161,7 @@ SmmAddProcessor ( > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D=3D INVALID_= APIC_ID) { > gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId =3D ProcessorId; > gSmmCpuPrivate->ProcessorInfo[Index].StatusFlag =3D 0; > - SmmGetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate- > >ProcessorInfo[Index].Location); > + GetProcessorLocation ((UINT32)ProcessorId, &gSmmCpuPrivate- > >ProcessorInfo[Index].Location); >=20 > *ProcessorNumber =3D Index; > gSmmCpuPrivate->Operation[Index] =3D SmmCpuAdd; > -- > 1.9.1