From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E165981E4B for ; Wed, 16 Nov 2016 08:28:37 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP; 16 Nov 2016 08:28:42 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,500,1473145200"; d="scan'208";a="5109900" Received: from orsmsx101.amr.corp.intel.com ([10.22.225.128]) by orsmga002.jf.intel.com with ESMTP; 16 Nov 2016 08:28:42 -0800 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.63]) by ORSMSX101.amr.corp.intel.com ([169.254.8.189]) with mapi id 14.03.0248.002; Wed, 16 Nov 2016 08:28:42 -0800 From: "Kinney, Michael D" To: "Fan, Jeff" , "edk2-devel@lists.01.org" , "Kinney, Michael D" CC: "Tian, Feng" Thread-Topic: [PATCH 2/2] MdeModulePkg/PiSmmCpuDxeSmm: Check RegisterCpuInterruptHandler status Thread-Index: AQHSQBZ3Kh/1AOa8X0Ougs2h7I8WAqDby9gg Date: Wed, 16 Nov 2016 16:28:41 +0000 Message-ID: References: <20161116143343.15432-1-jeff.fan@intel.com> <20161116143343.15432-3-jeff.fan@intel.com> In-Reply-To: <20161116143343.15432-3-jeff.fan@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTkxYzA2MTUtNjVmZi00OWZmLWJjY2ItOWI2YWI2Nzk3ZDk2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6IityUjJUVkwrMGo0TzdnXC94bmhtS09QUmt5S0tnU2ptXC9idng1T1g4QWJRWT0ifQ== x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Subject: Re: [PATCH 2/2] MdeModulePkg/PiSmmCpuDxeSmm: Check RegisterCpuInterruptHandler status X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Nov 2016 16:28:38 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Jeff, Shouldn't this ASSERT() be moved into the implementation of SmmRegisterExceptionHandler()? This will make sure the PiSmmCpuDxeSmm driver uses the right lib instance=20 for exceptions that module registers and for exceptions other SMM modules register through the EFI_SMM_CPU_SERVICE_PROTOCOL. Mike > -----Original Message----- > From: Fan, Jeff > Sent: Wednesday, November 16, 2016 6:34 AM > To: edk2-devel@lists.01.org > Cc: Tian, Feng ; Kinney, Michael D > Subject: [PATCH 2/2] MdeModulePkg/PiSmmCpuDxeSmm: Check RegisterCpuInterr= uptHandler > status >=20 > Once platform selects the incorrect instance, the caller could know it fr= om > return status and ASSERT(). >=20 > Cc: Feng Tian > Cc: Michael D Kinney > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jeff Fan > --- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 4 +++- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 5 ++++- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 4 +++- > 3 files changed, 10 insertions(+), 3 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > index a871bef..f2e2ceb 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c > @@ -27,6 +27,7 @@ SmmInitPageTable ( > { > UINTN PageFaultHandlerHookAddress; > IA32_IDT_GATE_DESCRIPTOR *IdtEntry; > + EFI_STATUS Status; >=20 > // > // Initialize spin lock > @@ -49,7 +50,8 @@ SmmInitPageTable ( > // > // Register SMM Page Fault Handler > // > - SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_PAGE_FAULT= , > SmiPFHandler); > + Status =3D SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32= _PAGE_FAULT, > SmiPFHandler); > + ASSERT_EFI_ERROR (Status); > } >=20 > // > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > index 329574e..350a6a2 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c > @@ -1384,5 +1384,8 @@ InitIdtr ( > VOID > ) > { > - SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_DEBUG, > DebugExceptionHandler); > + EFI_STATUS Status; > + > + Status =3D SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_D= EBUG, > DebugExceptionHandler); > + ASSERT_EFI_ERROR (Status); > } > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > index 9cee784..c49fb26 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c > @@ -102,6 +102,7 @@ SmmInitPageTable ( > UINTN Index; > UINTN PageFaultHandlerHookAddress; > IA32_IDT_GATE_DESCRIPTOR *IdtEntry; > + EFI_STATUS Status; >=20 > // > // Initialize spin lock > @@ -160,7 +161,8 @@ SmmInitPageTable ( > // > // Register Smm Page Fault Handler > // > - SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32_PAGE_FAULT= , > SmiPFHandler); > + Status =3D SmmRegisterExceptionHandler (&mSmmCpuService, EXCEPT_IA32= _PAGE_FAULT, > SmiPFHandler); > + ASSERT_EFI_ERROR (Status); > } >=20 > // > -- > 2.9.3.windows.2