From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9E16181F3A for ; Wed, 16 Nov 2016 17:30:34 -0800 (PST) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga101.jf.intel.com with ESMTP; 16 Nov 2016 17:30:39 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.31,650,1473145200"; d="scan'208";a="192352295" Received: from orsmsx108.amr.corp.intel.com ([10.22.240.6]) by fmsmga004.fm.intel.com with ESMTP; 16 Nov 2016 17:30:39 -0800 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.63]) by ORSMSX108.amr.corp.intel.com ([169.254.2.107]) with mapi id 14.03.0248.002; Wed, 16 Nov 2016 17:30:38 -0800 From: "Kinney, Michael D" To: "Fan, Jeff" , "Yao, Jiewen" , "edk2-devel@lists.01.org" , "Kinney, Michael D" CC: "Tian, Feng" , "Zeng, Star" , Laszlo Ersek , Paolo Bonzini Thread-Topic: [PATCH V3 0/6] Enable SMM page level protection. Thread-Index: AQHSO/o2adOnpFb2KUmuLWCcSPmA26Dc5eCA//+Dd0A= Date: Thu, 17 Nov 2016 01:30:38 +0000 Message-ID: References: <1478854859-11096-1-git-send-email-jiewen.yao@intel.com> <542CF652F8836A4AB8DBFAAD40ED192A4A2DF9C8@shsmsx102.ccr.corp.intel.com> In-Reply-To: <542CF652F8836A4AB8DBFAAD40ED192A4A2DF9C8@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiOTQ4YTczYWQtMTBjMC00NTYzLWEwMmEtMTc3ZDI5NzBkNDNhIiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Im82RXlxbm16YjNmTGptU3B1U0VoNlRVc1BNUnZUbkIxOFRvTkNlVnZydkE9In0= x-originating-ip: [10.22.254.140] MIME-Version: 1.0 Subject: Re: [PATCH V3 0/6] Enable SMM page level protection. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 17 Nov 2016 01:30:34 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Jiewen, The new file MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c and the=20 new code in MdeModulePkg/Core/PiSmmCore/Page.c are based on the algorithms and implementation from MdeModulePkg/Core/Dxe/Misc/MemoryAttributesTable.c= =20 and MdeModulePkg/Core/Dxe/Mem/Page.c. Also, the new GUID gEdkiiPiSmmMemoryAttributesTableGuid and its associated structure are based on the EFI_MEMORY_ATTRIBUTES_TABLE and GUID from the=20 UEFI Specification. I recommend you update the commit messages to highlight that these new=20 components are based on the Memory Attributes Table feature from the UEFI Specification and the existing DXE Core implementation that supports that feature. With those commit message updates, Series Reviewed-by: Michael Kinney Mike > -----Original Message----- > From: Fan, Jeff > Sent: Wednesday, November 16, 2016 4:45 PM > To: Yao, Jiewen ; edk2-devel@lists.01.org > Cc: Tian, Feng ; Zeng, Star ; K= inney, > Michael D ; Laszlo Ersek ;= Paolo > Bonzini > Subject: RE: [PATCH V3 0/6] Enable SMM page level protection. >=20 > Reviewed-by: Jeff Fan >=20 > Thanks! >=20 > -----Original Message----- > From: Yao, Jiewen > Sent: Friday, November 11, 2016 5:01 PM > To: edk2-devel@lists.01.org > Cc: Fan, Jeff; Tian, Feng; Zeng, Star; Kinney, Michael D; Laszlo Ersek; P= aolo Bonzini > Subject: [PATCH V3 0/6] Enable SMM page level protection. >=20 >=20 > =3D=3D=3D=3D below is V3 description =3D=3D=3D=3D > 1) PiSmmCpu: Fix CpuIndex corruption issue due to stack malposition. > (Many thanks to Laszlo Ersek for catching it.) > 2) PiSmmCpu: Add ASSERT for CpuIndex check. > 3) PiSmmCpu: Use DEBUG_VERBOSE for page table update. > 4) PiSmmCpu: Do not report DEBUG message for Ap non present when PcdCpuSm= mSyncMode=3D=3D1 > (Relex mode). > 5) PiSmmCpu: Do not report DEBUG message for AP removed when > PcdCpuHotPlugSupport=3D=3DTRUE. >=20 > Tested combination: > 1) XD disabled > 2) XD enabled in SMM and disabled in non-SMM. > 3) XD enabled in SMM and enabled in non-SMM. >=20 > =3D=3D=3D=3D below is V2 description =3D=3D=3D=3D > 1) PiSmmCpu: resolve OVMF multiple processors boot hang issue. > 2) PiSmmCpu: Add debug info on StartupAp() fails. > 3) PiSmmCpu: Add ASSERT for AllocatePages(). > 4) PiSmmCpu: Add protection detail in commit message. > 5) UefiCpuPkg.dsc: Add page table footprint info in commit message. >=20 > =3D=3D=3D=3D below is V1 description =3D=3D=3D=3D > This series patch enables SMM page level protection. > Features are: > 1) PiSmmCore reports SMM PE image code/data information in > EdkiiPiSmmMemoryAttributeTable, if the SMM image is page aligned. > 2) PiSmmCpu consumes EdkiiPiSmmMemoryAttributeTable and set XD for data p= age and RO > for code page. > 3) PiSmmCpu enables Static Paging for X64 according to PcdCpuSmmStaticPag= eTable. If > it is true, 1G paging for above 4G is used as long as it is supported. > 4) PiSmmCpu sets importance data structure to be read only, such as Gdt, = Idt, > SmmEntrypoint, and PageTable itself. >=20 > tested platform: > 1) Intel internal platform (X64). > 2) EDKII Quark IA32 > 3) EDKII Vlv2 X64 > 4) EDKII OVMF IA32 and IA32X64. (with -smp 8) >=20 > Cc: Jeff Fan > Cc: Feng Tian > Cc: Star Zeng > Cc: Michael D Kinney > Cc: Laszlo Ersek > Cc: Paolo Bonzini > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao >=20 > Jiewen Yao (6): > MdeModulePkg/Include: Add PiSmmMemoryAttributesTable.h > MdeModulePkg/dec: Add gEdkiiPiSmmMemoryAttributesTableGuid. > MdeModulePkg/PiSmmCore: Add MemoryAttributes support. > UefiCpuPkg/dec: Add PcdCpuSmmStaticPageTable. > UefiCpuPkg/PiSmmCpuDxeSmm: Add paging protection. > QuarkPlatformPkg/dsc: enable Smm paging protection. >=20 > MdeModulePkg/Core/PiSmmCore/Dispatcher.c | 66 + > MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c | 1509 ++++++++++= ++++++++++ > MdeModulePkg/Core/PiSmmCore/Page.c | 775 +++++++++- > MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 40 + > MdeModulePkg/Core/PiSmmCore/PiSmmCore.h | 91 ++ > MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf | 2 + > MdeModulePkg/Core/PiSmmCore/Pool.c | 16 + > MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable.h | 51 + > MdeModulePkg/MdeModulePkg.dec | 3 + > QuarkPlatformPkg/Quark.dsc | 6 + > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 71 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.S | 75 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.asm | 75 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm | 79 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.S | 226 +-- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.asm | 36 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm | 36 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c | 37 +- > UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c | 4 +- > UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 135 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c | 144 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h | 156 +- > UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf | 5 +- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 871 ++++++++++= + > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 39 +- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 15 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 274 +++- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.S | 59 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.asm | 62 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 69 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.S | 250 +--- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.asm | 35 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiException.nasm | 31 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 30 +- > UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c | 7 +- > UefiCpuPkg/UefiCpuPkg.dec | 8 + > 36 files changed, 4585 insertions(+), 803 deletions(-) create mode 1006= 44 > MdeModulePkg/Core/PiSmmCore/MemoryAttributesTable.c > create mode 100644 MdeModulePkg/Include/Guid/PiSmmMemoryAttributesTable.= h > create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c >=20 > -- > 2.7.4.windows.1