From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8AFEB81FC2 for ; Thu, 15 Dec 2016 10:16:23 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga103.jf.intel.com with ESMTP; 15 Dec 2016 10:16:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,353,1477983600"; d="scan'208";a="18612912" Received: from orsmsx101.amr.corp.intel.com ([10.22.225.128]) by orsmga002.jf.intel.com with ESMTP; 15 Dec 2016 10:16:23 -0800 Received: from orsmsx158.amr.corp.intel.com (10.22.240.20) by ORSMSX101.amr.corp.intel.com (10.22.225.128) with Microsoft SMTP Server (TLS) id 14.3.248.2; Thu, 15 Dec 2016 10:16:22 -0800 Received: from orsmsx113.amr.corp.intel.com ([169.254.9.227]) by ORSMSX158.amr.corp.intel.com ([10.22.240.20]) with mapi id 14.03.0248.002; Thu, 15 Dec 2016 10:16:22 -0800 From: "Kinney, Michael D" To: "Wu, Hao A" , "edk2-devel@lists.01.org" , "Kinney, Michael D" CC: "Fan, Jeff" Thread-Topic: [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016) Thread-Index: AQHSVeTMHhMXQZ0aT0GmzoQ9KGyfR6EJUqLA Date: Thu, 15 Dec 2016 18:16:21 +0000 Message-ID: References: <1481704400-12044-1-git-send-email-hao.a.wu@intel.com> In-Reply-To: <1481704400-12044-1-git-send-email-hao.a.wu@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ctpclassification: CTP_IC x-titus-metadata-40: eyJDYXRlZ29yeUxhYmVscyI6IiIsIk1ldGFkYXRhIjp7Im5zIjoiaHR0cDpcL1wvd3d3LnRpdHVzLmNvbVwvbnNcL0ludGVsMyIsImlkIjoiYTYyNjZlZTMtMTQ2Ny00ZTQzLWFhOTctZjBhZGI5NmIyMWM2IiwicHJvcHMiOlt7Im4iOiJDVFBDbGFzc2lmaWNhdGlvbiIsInZhbHMiOlt7InZhbHVlIjoiQ1RQX0lDIn1dfV19LCJTdWJqZWN0TGFiZWxzIjpbXSwiVE1DVmVyc2lvbiI6IjE1LjkuNi42IiwiVHJ1c3RlZExhYmVsSGFzaCI6Ik9DeUxEWDNkRHRsVmFuS0xnRWpMOHhMd2xqbmVLQXlwK09mQjlxaFpncVE9In0= x-originating-ip: [10.22.254.139] MIME-Version: 1.0 Subject: Re: [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016) X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 15 Dec 2016 18:16:23 -0000 Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Series Reviewed-by: Michael Kinney Mike > -----Original Message----- > From: Wu, Hao A > Sent: Wednesday, December 14, 2016 12:33 AM > To: edk2-devel@lists.01.org > Cc: Wu, Hao A ; Kinney, Michael D ; > Fan, Jeff > Subject: [PATCH 0/4] Update CPUID & MSR header files with SDM (Sep.2016) >=20 > https://bugzilla.tianocore.org/show_bug.cgi?id=3D176 >=20 > According to the latest version (Sep.'16) of Intel(R) 64 and IA-32 > Architectures Software Developer's Manual (SDM), this patch series will > update the MSR and CPUID related definitions in .h files under > UefiCpuPkg/Include/Register. >=20 > Cc: Michael Kinney > Cc: Jeff Fan >=20 > Hao Wu (4): > UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016) > UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016) > UefiCpuPkg/Include: Add Goldmont MSR header file with SDM (Sep.2016) > UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016) >=20 > UefiCpuPkg/Application/Cpuid/Cpuid.c | 115 +- > UefiCpuPkg/Include/Register/ArchitecturalMsr.h | 159 +- > UefiCpuPkg/Include/Register/Cpuid.h | 363 +++- > UefiCpuPkg/Include/Register/Msr.h | 3 +- > UefiCpuPkg/Include/Register/Msr/AtomMsr.h | 167 +- > UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h | 43 +- > UefiCpuPkg/Include/Register/Msr/Core2Msr.h | 286 +-- > UefiCpuPkg/Include/Register/Msr/CoreMsr.h | 64 +- > UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h | 2515 ++++++++++++++++= ++++++ > UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h | 451 ++-- > UefiCpuPkg/Include/Register/Msr/HaswellMsr.h | 62 +- > UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h | 416 ++-- > UefiCpuPkg/Include/Register/Msr/NehalemMsr.h | 340 +-- > UefiCpuPkg/Include/Register/Msr/P6Msr.h | 6 +- > UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h | 146 +- > UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h | 26 +- > UefiCpuPkg/Include/Register/Msr/PentiumMsr.h | 8 +- > UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 537 ++--- > UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h | 411 ++-- > UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h | 1189 +++++++++- > UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h | 2 +- > UefiCpuPkg/Include/Register/Msr/XeonDMsr.h | 456 +--- > UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h | 74 +- > UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h | 314 +-- > 24 files changed, 5323 insertions(+), 2830 deletions(-) > create mode 100644 UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h >=20 > -- > 1.9.5.msysgit.0